MAX1340BETX+ ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsApplications♦ Low-Power DAC: 1.5mAClosed-Loop Controls for Optical Components♦ Evaluation Kit Avail ..
MAX1340BETX+ ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsFeatures♦ Internal Reference or External Single-Ended/such as an internal ±1°C accurate temperature ..
MAX13412EESA+ ,RS-485 Transceiver with Integrated Low-Dropout Regulator and AutoDirection Controlapplications, this reduces the cost and size of the sys-tem by reducing the number of optical isola ..
MAX1342BETX ,4.096 V, 12-bit, multichannel ADC/DAC with FIFO, temperature sensing, and GPIO portELECTRICAL CHARACTERISTICS(AV = DV = 2.7V to 3.6V (MAX1341/MAX1343/MAX1347/MAX1349), external refer ..
MAX1342BETX+ ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsELECTRICAL CHARACTERISTICS(AV = DV = 4.75V to 5.25V, external reference V = 4.096V, f = 3.6MHz (50% ..
MAX1342BETX+ ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsFeaturesThe devices are guaranteed to operate with a supply ♦ Analog Single-Supply Operationvoltage ..
MAX397CPI+ ,Precision, 16-Channel/Dual 8-Channel, Low-Voltage, CMOS Analog MultiplexersMAX396/MAX397 Precision, 16-Channel/Dual 8-Channel,Low-Voltage, CMOS Analog Multiplexers
MAX397CWI ,Precision, 16-Channel/Dual 8-Channel, Low-Voltage, CMOS Analog MultiplexersApplicationsMAX396CWI 0°C to +70°C 28 Wide SOSample-and-Hold Circuits Automatic Test EquipmentMAX39 ..
MAX397EPI ,Precision, 16-Channel/Dual 8-Channel, Low-Voltage, CMOS Analog MultiplexersFeaturesThe MAX396/MAX397 low-voltage, CMOS analog multi- ' Pin Compatible with MAX306/MAX307,plexe ..
MAX397EWI ,Precision, 16-Channel/Dual 8-Channel, Low-Voltage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +5V ±10%, V- = -5V ±10%, GND = 0V, V = V = 2.4V, V = ..
MAX398 ,Precision, 8-Channel/Dual 4-Channel, Low-Voltage, CMOS Analog MultiplexersApplicationsMAX398CGE 0°C to +70°C 16 QFN-EP* G1655-3Sample-and-Hold CircuitsMAX398CEE 0°C to +70°C ..
MAX3982UTE+ ,SFP Copper-Cable Preemphasis DriverApplicationsSFP Active Copper-Cable Assemblies Ordering InformationBackplanesTEMP PIN- PKGPARTRANGE ..
MAX1340BETX+-MAX1342BETX+-MAX1348BETX+
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports
General DescriptionThe MAX1340/MAX1342/MAX1346/MAX1348 integrate a
multichannel, 12-bit, analog-to-digital converter (ADC)
and a quad, 12-bit, digital-to-analog converter (DAC) in a
single IC. The devices also include a temperature sensor
and configurable general-purpose I/O ports (GPIOs) with
a 25MHz SPI™-/QSPI™-/MICROWIRE™-compatible seri-
al interface. The ADC is available in a 4 or an 8 input-
channel version. The four DAC outputs settle within 2.0µs,
and the ADC has a 225ksps conversion rate.
All devices include an internal reference (4.096V) provid-
ing a well-regulated, low-noise reference for both the
ADC and DAC. Programmable reference modes for the
ADC and DAC allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal ±1°C accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown™ allow
users to minimize both power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and low
digital feedthrough (0.5nV•s) of the integrated quad
DACs make these devices ideal for digital control of fast-
response closed-loop systems.
The devices are guaranteed to operate with a supply
voltage from +4.75V to +5.25V The devices consume
2.5mA at 225ksps throughput, only 22µA at 1ksps
throughput, and under 0.2µA in the shutdown mode. The
MAX1342/MAX1348 offer four GPIOs that can be config-
ured as inputs or outputs.
The MAX1340/MAX1342/MAX1346/MAX1348 are avail-
able in 36-pin thin QFN packages. All devices are speci-
fied over the -40°C to +85°C temperature range.
ApplicationsClosed-Loop Controls for Optical Components
and Base Stations
System Supervision and Control
Data-Acquisition Systems
Features12-Bit, 225ksps ADCAnalog Multiplexer with True-Differential
Track/Hold (T/H)8 Single-Ended Channels or 4 Differential
Channels (Unipolar or Bipolar)
(MAX1340/MAX1342)4 Single-Ended Channels or 2 Differential
Channels (Unipolar or Bipolar)(MAX1346/MAX1348)
Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB DNL12-Bit, Quad, 2µs Settling DAC
Ultra-Low Glitch Energy (4nV•s)Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: ±0.5 LSB INLInternal Reference or External Single-Ended/
Differential ReferenceInternal Reference Voltage (4.096V)Internal ±1°C Accurate Temperature SensorOn-Chip FIFO Capable of Storing 16 ADCConversion Results and One Temperature ResultOn-Chip Channel-Scan Mode and Internal Data-Averaging FeaturesAnalog Single-Supply Operation
+4.75V to +5.25VDigital Supply: 2.7V to AVDD25MHz, SPI/QSPI/MICROWIRE Serial InterfaceAutoShutdown Between ConversionsLow-Power ADC2.5mA at 225ksps
22µA at 1ksps
0.2µA at ShutdownLow-Power DAC: 1.5mAEvaluation Kit Available (Order MAX1258EVKIT)
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Ordering Information/Selector Guide19-3332; Rev 3; 3/08
EVALUATION KIT
AVAILABLE
Pin Configurations appear at end of data sheet.
PARTTEMP RANGEPIN-PACKAGE
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS**
ADC
CHANNELS
DAC
CHANNELSGPIOs
MAX1340BETX-40°C to +85°C36 Thin QFN-EP*4.0964.75 to 5.2512840
MAX1342BETX-40°C to +85°C36 Thin QFN-EP*4.0964.75 to 5.2512844
MAX1346BETX-40°C to +85°C36 Thin QFN-EP*4.0964.75 to 5.2512440
MAX1348BETX-40°C to +85°C36 Thin QFN-EP*4.0964.75 to 5.2512444
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
*EP = Exposed pad.
**Number of resolution bits refers to both DAC and ADC.
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= 4.75V to 5.25V, external reference VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD= DVDD= 5V, TA= +25°C. Outputs are unloaded, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND.........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
DVDDto AVDD.......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND.........................-0.3V to (DVDD + 0.3V)
Analog Inputs, Analog Outputs and REF_
to AGND...............................................-0.3V to (AVDD + 0.3V)
Maximum Current into Any Pin (except AGND, DGND, AVDD,
DVDD, and OUT_)...........................................................50mA
Maximum Current into OUT_.............................................100mA
Continuous Power Dissipation (TA= +70°C)
36-Pin Thin QFN (6mm x 6mm)
(derate 26.3mW/°C above +70°C)......................2105.3mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ADC
DC ACCURACY (Note 1)Resolution12Bits
Integral NonlinearityINL±0.5±1.0LSB
Differential NonlinearityDNL±0.5±1.0LSB
Offset Error±0.5±4.0LSB
Gain Error(Note 2)±0.5±4.0LSB
Gain Temperature Coefficient±0.8ppm/°C
Channel-to-Channel Offset±0.1LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, VIN = 4.096VP-P, 225ksps, fCLK = 3.6MHz)Signal-to-Noise Plus DistortionSINAD70dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)THD-76dBc
Spurious-Free Dynamic RangeSFDR72dBc
Intermodulation DistortionIMDfIN1 = 9.9kHz, fIN2 = 10.2kHz76dBc
Full-Linear BandwidthSINAD > 70dB100kHz
Full-Power Bandwidth-3dB point1MHz
CONVERSION RATE (Note 3)External reference0.8µs
Power-Up TimetPUInternal reference (Note 4)218onver si onl ockycl es
Note:If the package power dissipation is not exceeded, one output at a time may be shorted to AVDD, DVDD, AGND, or DGND
indefinitely.
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= 4.75V to 5.25V, external reference VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD= DVDD= 5V, TA= +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQ(Note 5)0.6µs
Internally clocked5.5Conversion TimetCONVExternally clocked3.6µs
External-Clock FrequencyfCLKExternally clocked conversion (Note 5)0.13.6MHz
Duty Cycle4060%
Aperture Delay30ns
Aperture Jitter< 50ps
ANALOG INPUTSUnipolar0VREFInput-Voltage Range (Note 6)Bipolar-VREF/2VREF/2V
Input Leakage Current±0.01±1µA
Input Capacitance24pF
INTERNAL TEMPERATURE SENSORTA = +25°C±0.7Measurement Error (Notes 5, 7)TA = TMIN to TMAX±1.0±3.0°C
Temperature Resolution1/8°C/LSB
INTERNAL REFERENCEREF1 Output Voltage(Note 8)4.0664.0964.126V
REF1 Voltage Temperature
CoefficientTCREF±30ppm/°C
REF1 Output Impedance6.5kΩ
REF1 Short-Circuit CurrentVREF = 4.096V0.63mA
EXTERNAL REFERENCEREF1 Input-Voltage RangeVREF1REF mode 11 (Note 4)1AVDD +
0.05V
REF mode 011AVDD +
0.05REF2 Input-Voltage Range
(Note 4)VREF2
REF mode 1101
VREF = 4.096V, fSAMPLE = 225ksps4080REF1 Input Current (Note 9)IREF1Acquisition between conversions±0.01±1µA
VREF = 4.096V, fSAMPLE = 225ksps4080REF2 Input CurrentIREF2Acquisition between conversions±0.01±1µA
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DAC
DC ACCURACY (Note 10)Resolution12Bits
Integral NonlinearityINL±0.5±4LSB
Differential NonlinearityDNLGuaranteed monotonic±1.0LSB
Offset ErrorVOS(Note 8)±3±10mV
Offset-Error Drift±10ppm of
FS/°C
Gain ErrorGE(Note 8)±5±10LSB
Gain Temperature Coefficient±8ppm of
FS/°C
DAC OUTPUTNo load0.02AVDD -
Output-Voltage Range
10kΩ load to either rail0.1AVDD -
DC Output Impedance0.5Ω
Capacitive Load(Note 11)1nF
Resistive Load to AGNDRLAVDD = 4.75V, VREF = 4.096V, gain error
< 2%500Ω
From power-down mode, AVDD = 5V25Wake-Up Time (Note 12)From power-down mode, AVDD = 2.7V21µs
1kΩ Output TerminationProgrammed in power-down mode1kΩ
100kΩ Output TerminationAt wake-up or programmed in
power-down mode100kΩ
DYNAMIC PERFORMANCE (Notes 5, 13)Output-Voltage Slew RateSRPositive and negative3V/µs
Output-Voltage Settling TimetSTo 1 LSB, 400 - C00 hex (Note 7)25µs
Digital FeedthroughCode 0, all digital inputs from 0 to DVDD0.5nV•s
Major Code Transition Glitch
ImpulseBetween codes 2047 and 20484nV•s
From VREF660Output Noise (0.1Hz to 50MHz)Using internal reference720µVP-P
From VREF260Output Noise (0.1Hz to 500kHz)Using internal reference320µVP-P
DAC-to-DAC Transition
Crosstalk0.5nV•s
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= 4.75V to 5.25V, external reference VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD= DVDD= 5V, TA= +25°C. Outputs are unloaded, unless otherwise noted.)
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL REFERENCEREF1 Output Voltage4.0664.0964.126V
REF1 Temperature CoefficientTCREF±30ppm/°C
REF1 Short-Circuit CurrentVREF = 4.096V0.63mA
EXTERNAL-REFERENCE INPUTREF1 Input-Voltage RangeVREF1REF modes 01, 10, and 11 (Note 4)0.7AVDDV
REF1 Input ImpedanceRREF170100130kΩ
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)Input-Voltage HighVIHDVDD = 2.7V to 5.25V2.4V
DVDD = 3.6V to 5.25V0.8Input-Voltage LowVILDVDD = 2.7V to 3.6V0.6V
Input Leakage CurrentIL±0.01±10µA
Input CapacitanceCIN15pF
DIGITAL OUTPUT (DOUT) (Note 14)Output-Voltage LowVOLISINK = 2mA0.4V
Output-Voltage HighVOHISOURCE = 2mADVDD -
0.5V
Tri-State Leakage Current±10µA
Tri-State Output CapacitanceCOUT15pF
DIGITAL OUTPUT (EOC) (Note 14)Output-Voltage LowVOLISINK = 2mA0.4V
Output-Voltage HighVOHISOURCE = 2mADVDD -
0.5V
Tri-State Leakage Current±10µA
Tri-State Output CapacitanceCOUT15pF
DIGITAL OUTPUTS (GPIO_) (Note 14)ISINK = 2mA0.4GPIOC_ Output-Voltage LowISINK = 4mA0.8V
GPIOC_ Output-Voltage HighISOURCE = 2mADVDD -
0.5V
GPIOA_ Output-Voltage LowISINK = 15mA0.8V
GPIOA_ Output-Voltage HighISOURCE = 15mADVDD -
0.8V
Tri-State Leakage Current±10µA
Tri-State Output CapacitanceCOUT15pF
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= 4.75V to 5.25V, external reference VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD= DVDD= 5V, TA= +25°C. Outputs are unloaded, unless otherwise noted.)
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS (Note 15)Digital Positive-Supply VoltageDVDD4.75AVDDV
Idle, all blocks shut down0.24µADigital Positive-Supply CurrentDIDDOnly ADC on, external reference1mA
Analog Positive-Supply VoltageAVDD4.755.25V
Idle, all blocks shut down0.22µA
fSAMPLE = 225ksps2.84.2Only ADC on,
external referencefSAMPLE = 100ksps2.6Analog Positive-Supply CurrentAIDD
All DACs on, no load, internal reference1.54.0
REF1 Positive-Supply RejectionPSRRAVDD = 4.75V-80dB
DAC Positive-Supply RejectionPSRDOutput code = FFFhex, AVDD = 4.75V to
5.25V±0.1±0.5mV
ADC Positive-Supply RejectionPSRAFull-scale input, AVDD = 4.75V to 5.25V±0.06±0.5mV
TIMING CHARACTERISTICS (Figures 6–13)SCLK Clock PeriodtCP40ns
SCLK Pulse-Width HightCH40/60 duty cycle16ns
SCLK Pulse-Width LowtCL60/40 duty cycle16ns
GPIO Output Rise/Fall After
CS RisetGODCLOAD = 20pF100ns
GPIO Input Setup Before CS FalltGSU0ns
LDAC Pulse WidthtLDACPWL20ns
CLOAD = 20pF, SLOW = 01.812.0SCLK Fall to DOUT Transition
(Note 16)tDOTCLOAD = 20pF, SLOW = 11040ns
CLOAD = 20pF, SLOW = 01.812.0SCLK Rise to DOUT Transition
(Notes 16, 17)tDOTCLOAD = 20pF, SLOW = 11040ns
CS Fall to SCLK Fall Setup TimetCSS10nsC LK Fal l to CS Ri se S etup Ti m etCSH02000ns
DIN to SCLK Fall Setup TimetDS10ns
DIN to SCLK Fall Hold TimetDH0ns
CS Pulse-Width HightCSPWH50ns
CS Rise to DOUT DisabletDODCLOAD = 20pF25ns
CS Fall to DOUT EnabletDOECLOAD = 20pF1.525.0ns
EOC Fall to CS FalltRDS30ns
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= 4.75V to 5.25V, external reference VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD= DVDD= 5V, TA= +25°C. Outputs are unloaded, unless otherwise noted.)
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
CKSEL = 01 (voltage conversion)9
CKSEL = 10 (voltage conversion),
internal reference on9
CS or CNVST Rise to EOC Fall—
Internally Clocked
Conversion Time
tDOV
CKSEL = 10 (voltage conversion),
internal reference initially off80
CKSEL = 00, CKSEL = 01 (temp sense)40nsCNVST Pulse WidthtCSWCKSEL = 01 (voltage conversion)1.4µs
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= 4.75V to 5.25V, external reference VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD= DVDD= 5V, TA= +25°C. Outputs are unloaded, unless otherwise noted.)
Note 1:Tested at DVDD= AVDD= +5.25V.
Note 2:Offset nulled.
Note 3:No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles, multiplied by the
clock period.
Note 4:See Table 5 for reference-mode details.
Note 5:Not production tested. Guaranteed by design.
Note 6:See the ADC/DAC Referencessection.
Note 7:Fast automated test, excludes self-heating effects.
Note 8:Specified over the -40°C to +85°C temperature range.
Note 9:REFSEL[1:0] = 00 or when DACs are not powered up.
Note 10:DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11:The DAC buffers are guaranteed by design to be stable with a 1nF load.
Note 12:Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13:All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Note 14:Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15:All digital inputs at either DVDDor DGND. DVDDshould not exceed AVDD.
Note 16:See the Reset Registersection and Table 9 for details on programming the SLOW bit.
Note 17:Clock mode 11 only.
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Typical Operating Characteristics(AVDD= DVDD= 5V, external VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor
at REF, TA= +25°C, unless otherwise noted.)
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1340 toc01
SUPPLY VOLTAGE (V)
ANALOG SHUTDOWN CURRENT (
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
MAX1340 toc02
TEMPERATURE (°C)
ANALOG SHUTDOWN CURRENT (
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1340 toc03
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1340 toc04
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1340 toc05
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
ADC OFFSET ERROR
vs. TEMPERATURE
MAX1340 toc06
TEMPERATURE (°C)
OFFSET ERROR (LSB)
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1340 toc07
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
ADC GAIN ERROR
vs. TEMPERATURE
MAX1340 toc08
TEMPERATURE (°C)
GAIN ERROR (LSB)
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATEMAX1340 toc09
SAMPLING RATE (ksps)
ADC EXTERNAL REFERENCE INPUT CURRENT (
0300
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Portsypical Operating Characteristics (continued)(AVDD= DVDD= 5V, external VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor
at REF, TA= +25°C, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. SAMPLING RATEMAX1340 toc10
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT (mA)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1340 toc11
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1340 toc12
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1340 toc13
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX1340 toc14
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
MAX1340 toc15
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY
DAC FULL-SCALE ERROR
vs. TEMPERATURE
MAX1340 toc16
TEMPERATURE (°C)
DAC FULL-SCALE ERROR (LSB)
INTERNAL REFERENCE
EXTERNAL REFERENCE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGEMAX1340 toc17
REFERENCE VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)312
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
MAX1340 toc18
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR (LSB)2015105
030
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Portsypical Operating Characteristics (continued)(AVDD= DVDD= 5V, external VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor
at REF, TA= +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1340 toc19
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1340 toc20
SUPPLY VOLTAGE (V)
ADC REFERENCE SUPPLY CURRENT (
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
MAX1340 toc21
TEMPERATURE (°C)
INTERNAL REFERENCE SUPPLY CURRENT (
ADC FFT PLOTMAX1340 toc22
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fSAMPLE = 32.768kHz
fANALOG_)N = 10.080kHz
fCLK = 5.24288MHz
SINAD = 71.27dBc
SNR = 71.45dBc
THD = 85.32dBc
SFDR = 87.25dBc
ADC IMD PLOTMAX1340 toc23
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fCLK = 5.24288MHz
fIN1 = 9.0kHz
fIN2 = 11.0kHz
AIN = -6dBFS
IMD = 82.99dBc
ADC CROSSTALK PLOTMAX1340 toc24
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fCLK = 5.24288MHz
fIN1 = 10.080kHz
fIN2 = 8.0801kHz
SNR = 72.00dBc
THD = 85.24dBc
ENOB = 11.65 BITS
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENTMAX1340 toc25
OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)300
DAC OUTPUT = MIDSCALE
SINKING
SOURCING
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENTMAX1340 toc26
SOURCE CURRENT (mA)
GPIO OUTPUT VOLTAGE (V)604020100
GPIOA0–A3 OUTPUTS
GPIOB0–B3,
C0–C3 OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SINK CURRENTMAX1340 toc27
SINK CURRENT (mA)
GPIO OUTPUT VOLTAGE (mV)604020
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Portsypical Operating Characteristics (continued)(AVDD= DVDD= 5V, external VREF= 4.096V, fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor
at REF, TA= +25°C, unless otherwise noted.)
TEMPERATURE SENSOR ERROR
vs. TEMPERATUREMAX1340 toc28
TEMPERATURE (°C)
TEMPERATURE SENSOR ERROR (35-1510
DAC-TO-DAC CROSSTALK
RLOAD = 10kΩ, CLOAD = 100pF
MAX1340 toc29
100µs
VOUTA
2V/div
VOUTB
10mV/div
AC-COUPLED
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1340 toc30
1µs
VOUT
2V/div
2V/div
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1340 toc31
1µs
VOUT
2V/div
2V/div
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pFMAX1340 toc32
1µs
VOUT
20mV/div
AC-COUPLED
2V/div
DAC DIGITAL FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pF,
CS = HIGH, DIN = LOWMAX1340 toc33
200ns
VOUT
100mV/div
AC-COUPLED
SCLK
2V/div
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1340 toc34
2µs
VOUT_
2V/div
VLDAC
2V/div
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1340 toc35
1µs
VOUT_
2V/div
VLDAC
2V/div
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pF MAX1340 toc36
200µs
VDAC-OUT
2mV/div
AC-COUPLED
VREF2
2V/div
ADC REFERENCE SWITCHING
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Pin Description
MAX1340MAX1342MAX1346MAX1348NAMEFUNCTION1, 2, 16–19,
24, 2516–19
1, 2, 16–19,
24, 25, 31,
16–19, 31,D.C.Do Not Connect. Do not connect to this pin.333EOCActive-Low End-of-Conversion Output. Data is valid after the
falling edge of EOC.444DVDDDigital Positive Power Input. Bypass DVDD to DGND with a
0.1µF capacitor.555DGNDDigital Ground. Connect DGND to AGND.666DOUT
Serial Data Output. Data is clocked out on the falling edge of
the SCLK clock in clock modes 00, 01, and 10. Data is
clocked out on the rising edge of the SCLK clock in clock
mode 11. High impedance when CS is high.777SCLK
Serial Clock Input. Clocks data in and out of the serial
interface. (Duty cycle must be 40% to 60%.) See Table 4 for
details on programming the clock mode.888DINSerial Data Input. DIN data is latched into the serial interface
on the falling edge of SCLK.
9–129–129–129–12OUT0–
OUT3DAC Outputs131313AVDDPositive Analog Power Input. Bypass AVDD to AGND with a
0.1µF capacitor.141414AGNDAnalog Ground
15, 23, 32,
15, 23, 32,
15, 23, 32,
15, 23, 32,N.C.No Connection. Not internally connected.202020LDAC
Active-Low Load DAC. LDAC is an asynchronous active-low
input that updates the DAC outputs. Drive LDAC low to make
the DAC registers transparent.212121CS
Active-Low Chip-Select Input. When CS is low, the serial
interface is enabled. When CS is high, DOUT is high
impedance.222222RES_SEL
Reset Select. Selects DAC wake-up mode. Set RES_SEL low
to wake up the DAC outputs with a 100kΩ resistor to GND or
set RES_SEL high to wake up the DAC outputs with a 100kΩ
resistor to VREF. Set RES_SEL high to power up the DAC input
register to FFFh. Set RES_SEL low to power up the DAC input
register to 000h.
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Pin Description (continued)
MAX1340MAX1342MAX1346MAX1348NAMEFUNCTION262626REF1
Reference 1 Input. Reference voltage. Leave unconnected to
use the internal reference (4.096V). REF1 is the positive
reference in ADC external differential reference mode. Bypass
REF1 to AGND with a 0.1µF capacitor in external reference
mode only. See the ADC/DAC References section.
27–31, 3427–31, 34——AIN0–AIN5Analog Inputs35——REF2/AIN6
Reference 2 Input/Analog Input Channel 6. See Table 5 for
details on programming the setup register. REF2 is the
negative reference in the ADC external differential reference
mode.36——CNVST/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 5
for details on programming the setup register.1, 2—1, 2GPIOA0,
GPIOA1
General-Purpose I/O A0, A1. GPIOA0, GPIOA1 can sink and
source 15mA.24, 25—24, 25GPIOC0,
GPIOC1
General-Purpose I/O C0, C1. GPIOC0, GPIOC1 can sink 4mA
and source 2mA.—27–3027–30AIN0–AIN3Analog Inputs—3535REF2
Reference 2 Input. See Table 5 for details on programming the
setup register. REF2 is the negative reference in the ADC
external differential reference mode.—3636CNVSTActive-Low Conversion Start Input. See Table 5 details on
programming the setup register.
————EPExposed Paddle. Must be externally connected to AGND. Do
not use as a ground connect.
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Detailed DescriptionThe MAX1340/MAX1342/MAX1346/MAX1348 integrate
a multichannel 12-bit ADC, and a quad 12-bit DAC in a
single IC. The devices also include a temperature sen-
sor and configurable GPIOs with a 25MHz SPI-/QSPI-
/MICROWIRE-compatible serial interface. The ADC is
available in a 4 or an 8 input-channel version. The four
DAC outputs settle within 2.0µs, and the ADC has a
225ksps conversion rate.
All devices include an internal reference (4.096V) pro-
viding a well-regulated, low-noise reference for both the
ADC and DAC. Programmable reference modes for the
ADC and DAC allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal ±1°C accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown allow
users to minimize both power consumption and proces-
sor requirements. The low glitch energy (4nV•s) and
low digital feedthrough (0.5nV•s) of the integrated quad
DACs make these devices ideal for digital control of
fast-response closed-loop systems.
The devices are guaranteed to operate with a supply
voltage from +4.75V to +5.25V. The devices consume
2.5mA at 225ksps throughput, only 22µA at 1ksps
throughput, and under 0.2µA in the shutdown mode.
The MAX1342/MAX1348 offer four GPIOs that can be
configured as inputs or outputs.
Figure 1 shows the MAX1342 functional diagram. The
MAX1342/MAX1348 only include the GPIO A0, A1, GPIO
C0, C1 blocks. The MAX1340/MAX1346 exclude the
GPIOs. The output-conditioning circuitry takes the internal
parallel data bus and converts it to a serial data format at
DOUT, with the appropriate wake-up timing. The arith-
metic logic unit (ALU) performs the averaging function.
SPI-Compatible Serial InterfaceThe MAX1340/MAX1342/MAX1346/MAX1348 feature a
serial interface that is compatible with SPI and
MICROWIRE devices. For SPI, ensure the SPI bus mas-
ter (typically a microcontroller (µC)) runs in master
mode so that it generates the serial clock signal. Select
the SCLK frequency of 25MHz or less, and set the
clock polarity (CPOL) and phase (CPHA) in the µC con-
trol registers to the same value. The MAX1340/
MAX1342/MAX1346/MAX1348 operate with SCLK idling
high or low, and thus operate with CPOL = CPHA = 0 or
CPOL = CPHA = 1. Set CSlow to latch any input data
at DIN on the falling edge of SCLK. Output data at
DOUT is updated on the falling edge of SCLK in clock
modes 00, 01, and 10. Output data at DOUT is updated
on the rising edge of SCLK in clock mode 11. See
Figures 6–11. Bipolar true-differential results and tem-
perature-sensor results are available in two’s comple-
ment format, while all other results are in binary.
A high-to-low transition on CSinitiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CSlow between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interfacesection
and Tables 10, 17, and 18.
Write to the GPIOs (if applicable) by issuing a command
byte to the appropriate register. Writing to the
MAX1342/MAX1348 GPIOs requires 1 additional byte fol-
lowing the command byte.See Tables 12–16 for details
on GPIO configuration, writes, and reads. See the GPIO
Commandsection. Command bytes written to the
GPIOs on devices without GPIOs are ignored.
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO PortsDOUT
EOC
ADDRESS
AIN0
AIN5
REF2/
AIN6
CNVST/
AIN7
REF1
DIN
SCLK
GPIOA0,
GPIOA1
GPIOC0,
GPIOC1
AVDD
SPI
PORT
GPIO
CONTROL
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
USER-PROGRAMMABLE
I/O
OSCILLATOROUT0
OUT1
OUT2
MAX1342
12-BIT
SAR
ADC
LOGIC
CONTROL
TEMPERATURE
SENSOR
FIFO AND
ALU
LDACRES_SELAGND
T/H
REF2
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INTERNAL
REFERENCE
OUT3
DGND
DVDD
CNVST
Figure 1. MAX1342 Functional Diagram
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Table 1. Command Byte (MSB First)
REGISTER NAMEBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0Conversion*1XCHSEL2CHSEL1CHSEL0SCAN1SCAN0TEMP
Setup01CKSEL1CKSEL0REFSEL1REFSEL0DIFFSEL1DIFFSEL0
ADC Averaging001AVGONNAVG1NAVG0NSCAN1NSCAN0
DAC Select0001XXXX
Reset00001RESETSLOWFBGON
GPIO Configure**00000011
GPIO Write**00000010
GPIO Read**00000001
No Operation00000000
X = Don’t care.
*CHESL2 bit is only valid on the MAX1340/MAX1342.Set CHSEL2 to zero on the MAX1346/MAX1348.
**Only applicable on the MAX1342/MAX1348.
Power-Up Default StateThe MAX1340/MAX1342/MAX1346/MAX1348 power up
with all blocks in shutdown (including the reference). All
registers power up in state 00000000, except for the
setup register and the DAC input register. The setup
register powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high and powers up to 000h
when RES_SEL is low.
12-Bit ADCThe MAX1340/MAX1342/MAX1346/MAX1348 ADCs use
a fully differential successive-approximation register
(SAR) conversion technique and on-chip track-and-
hold (T/H) circuitry to convert temperature and voltage
signals into 12-bit digital results. The analog inputs
accept both single-ended and differential input signals.
Single-ended signals are converted using a unipolar
transfer function, and differential signals are converted
using a selectable bipolar or unipolar transfer function.
See the ADC Transfer Functionssection for more data.
ADC Clock ModesWhen addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVSTto request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOCgoes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOCgoes high when CSor CNVSTgo low.
EOCis always high in clock mode 11.
Single-Ended or Differential ConversionsThe MAX1340/MAX1342/MAX1346/MAX1348 use a fully
differential ADC for all conversions. When a pair of
inputs are connected as a differential pair, each input is
connected to the ADC. When configured in single-
ended mode, the positive input is the single-ended
channel and the negative input is referred to AGND.
See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7. AIN0–AIN3 are available on all devices.
AIN0–AIN7 are available on the MAX1340/MAX1342.
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
Unipolar or Bipolar ConversionsAddress the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Portsthe setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to VREF1.A nega-
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to ±VREF1/2. The digital
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
In single-ended mode, the MAX1340/MAX1342/
MAX1346/MAX1348 always operate in unipolar mode.
The analog inputs are internally referenced to AGND
with a full-scale input range from 0 to the selected refer-
ence voltage.
Analog Input (T/H)The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1340/MAX1342/MAX1346/
MAX1348. In track mode, a positive input capacitor is
connected to AIN0–AIN7 in single-ended mode and
AIN0, AIN2, AIN4, and AIN6 in differential mode. A neg-
ative input capacitor is connected to AGND in single-
ended mode or AIN1, AIN3, AIN5, and AIN7 in
differential mode. For external T/H timing, use clock
mode 01. After the T/H enters hold mode, the difference
between the sampled positive and negative input volt-
ages is converted. The input capacitance charging rate
determines the time required for the T/H to acquire an
input signal. If the input signal’s source impedance is
high, the required acquisition time lengthens.
Any source impedance below 300Ωdoes not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening tACQ (only in clock mode 01) or by placing
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
Input BandwidthThe ADC’s input-tracking circuitry has a 1MHz small-sig-
nal bandwidth, making it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
Analog-Input ProtectionInternal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDDand AGND, allowing
the inputs to swing from (AGND - 0.3V) to (AVDD+
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
Internal FIFOThe MAX1340/MAX1342/MAX1346/MAX1348 contain a
first-in/first-out (FIFO) buffer that holds up to 16 ADC
results plus one temperature result. The internal FIFO
allows the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measure-
ment is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the Temperature
Measurementssection for details on converting the dig-
ital code to a temperature.
AIN0–AIN7
(SINGLE-ENDED),
AIN0, AIN2,
AIN4, AIN6
(DIFFERENTIAL)
COMPARATOR
HOLDACQ
ACQ
HOLD
ACQ
HOLD
AVDD / 2
REF1
AGND
CIN+
CIN-
DAC
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5, AIN7
(DIFFERENTIAL)
Figure 2. Equivalent Input Circuit
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
12-Bit DACIn addition to the 12-bit ADC, the MAX1340/MAX1342/
MAX1346/MAX1348 also include four voltage-output,
12-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential nonlin-
earity error. Each DAC has a 2µs settling time and ultra-
low glitch energy (4nV•s). The 12-bit DAC code is
unipolar binary with 1 LSB = VREF / 4096.
DAC Digital InterfaceFigure 1 shows the functional diagram of the MAX1342.
The shift register converts a serial 16-bit word to parallel
data for each input register operating with a clock rate
up to 25MHz. The SPI-compatible digital interface to the
shift register consists of CS, SCLK, DIN, and DOUT.
Serial data at DIN is loaded on the falling edge of SCLK.
Pull CSlow to begin a write sequence. Begin a write to
the DAC by writing 0001XXXX as a command byte. The
last 4 bits of the DAC select register are don’t-care bits.
See Table 10. Write another 2 bytes to the DAC inter-
face register following the command byte to select the
appropriate DAC and the data to be written to it. See
Tables 17 and 18.
The four double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The four 12-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAClow or by writing the
appropriate DAC command sequence at DIN. See
Table 17. The outputs of the DACs are buffered through
four rail-to-rail op amps.
The MAX1340/MAX1342/MAX1346/MAX1348 DAC out-
put-voltage range is based on the internal reference or
an external reference. Write to the setup register (see
Table 5) to program the reference. If using an external
voltage reference, bypass REF1 with a 0.1µF capacitor
to AGND. The internal reference is 4.096V. When using
an external reference, the voltage range is 0.7V to AVDD.
DAC Transfer FunctionSee Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up ModesThe state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AVDDor
AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩinternal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AVDDto wake up all DAC outputs
at FFFh. While RES_SEL is high, the 100kΩpullup
resistor pulls the DAC outputs to VREF1and the output
buffers are powered down.
DAC Power-Up ModesSee Table 18 for a description of the DAC power-up
and power-down modes.
GPIOsIn addition to the internal ADC and DAC, the
MAX1342/MAX1348 also provide four GPIO channels,
GPIOA0, GPIOA1, GPIOC0, GPIOC1.Read and write to
the GPIOs as detailed in Table 1and Tables 12–16. Also,
see the GPIO Commandsection. See Figures 11 and 12
for GPIO timing.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1342/MAX1348 following the command byte.
DAC CONTENTS
MSBLSBANALOG OUTPUT0000000000000⎛⎜⎞⎟VREF4095
4096⎛⎜⎞⎟=+⎛⎜⎞⎟VV
REFREF2048
40962⎛⎜⎞⎟VREF2047
4096⎛⎜⎞⎟VREF1
4096⎛⎜⎞⎟VREF2049
Table 2. DAC Output Code Table
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO PortsThe GPIOs can sink and source current. The
MAX1342/MAX1348 GPIOA0 and GPIOA1 can sink and
source up to 15mA. GPIOC0 and GPIOC1 can sink 4mA
and source 2mA. See Table 3.
Clock Modes
Internal ClockThe MAX1340/MAX1342/MAX1346/MAX1348 can oper-
ate from an internal oscillator. The internal oscillator is
active in clock modes 00, 01, and 10. Figures 6, 7, and
8 show how to start an ADC conversion in the three
internally timed conversion modes.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
External ClockSet CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
3.6MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figure 9 for clock mode 11 timing. See the ADC
Conversions in Clock Mode 11 section.
ADC/DAC ReferencesAddress the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to pro-
gram the ADC for internal reference use without a
wake-up delay. Set REFSEL[1:0] = 10 to program the
DAC for external reference, REF1. When using REF1 or
REF2/AIN_ in external reference, connect a 0.1µF
capacitor to AGND. Set REFSEL[1:0] = 01 to program
the ADC and DAC for external-reference mode. The
DAC uses REF1 as its external reference, while the
ADC uses REF2 as its external reference. Set
REFSEL[1:0] = 11 to program the ADC for external dif-
ferential reference mode. REF1 is the positive reference
and REF2 is the negative reference in the ADC external
differential mode.
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
Temperature MeasurementsIssue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
See Table 4. The MAX1340/MAX1342/MAX1346/
MAX1348perform temperature measurements with an
internal diode-connected transistor. The diode bias cur-
rent changes from 68µA to 4µA to produce a tempera-
ture-dependent bias voltage difference. The second
conversion result at 4µA is subtracted from the first at
68µA to calculate a digital value that is proportional to
absolute temperature. The output data appearing at
DOUT is the digital code above, minus an offset to
adjust from Kelvin to Celsius.
The reference voltage used for the temperature mea-
surements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8 of a
degree Celsius. On every scan where a temperature
measurement is requested, the temperature conversion
is carried out first. The first 2 bytes of data read from
the FIFO contain the result of the temperature measure-
ment. If another temperature measurement is per-
formed before the first temperature result is read out,
the old measurement is overwritten by the new result.
Temperature results are in degrees Celsius (two’s com-
plement). See the Applications Informationsection for
information on how to perform temperature measure-
ments in each clock mode.
Register DescriptionsThe MAX1340/MAX1342/MAX1346/MAX1348 communi-
cate between the internal registers and the external cir-
cuitry through the SPI-compatible serial interface. Table
1 details the command byte, the registers, and the bit
names. Tables 4–12 show the various functions within
the conversion register, setup register, unipolar-mode
register, bipolar-mode register, ADC averaging regis-
ter, DAC select register, reset register, and GPIO com-
mand register, respectively.
Conversion RegisterSelect active analog input channels, scan modes, and a
single temperature measurement per scan by issuing a
command byte to the conversion register. Table 4
details channel selection, the four scan modes, and how
to request a temperature measurement. Start a scan by
writing to the conversion register when in clock mode 10
or 11, or by applying a low pulse to the CNVSTpin when
in clock mode 00 or 01. See Figures 6 and 7 for timing
specifications for starting a scan with CNVST.
MAX1342/MAX1348
CURRENTGPIOA0, GPIOA1
(mA)
GPIOC0, GPIOC1
(mA)Sink154
Source152
Table 3. GPIO Maximum Sink/Source
Current
MAX1340/MAX1342/MAX1346/MAX1348
12-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO PortsA conversion is not performed if it is requested on a
channel or one of the channel pairs that has been con-
figured as CNVSTor REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel. For the
MAX1346/MAX1348, the CHSEL2 bit must be zero.
Channels 4–7 are invalid. Any scans or averages on
these channels can cause corrupt data.
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
Setup RegisterIssue a command byte to the setup register to config-
ure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acqui-
sition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog-input
channels for differential operation.
The ADC reference is always on if any of the following
conditions are true:The FBGON bit is set to one in the reset register.At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.At least one DAC is powered down through the
100kΩto VREFand REFSEL[1:0] = 00.
If any of the above conditions exist, the ADC reference is
always on, but there is a 188 clock-cycle delay before
temperature-sensor measurements begin, if requested.
Table 4. Conversion Register*
BIT
NAMEBITFUNCTION7 (MSB)S et to one to sel ect conver si on r eg i ster .6Don’t care.
CHSEL25
Analog-input channel select
(MAX1340/MAX1342). Set to 0 on
MAX1346/MAX1348.
CHSEL14Analog-input channel select.
CHSEL03Analog-input channel select.
SCAN12Scan-mode select.
SCAN01Scan-mode select.
TEMP0 (LSB)
Set to one to take a single temp-
erature measurement. The first
conversion result of a scan contains
temperature information.
CHSEL2**CHSEL1CHSEL0
SELEC T ED H AN N ELN ) 00AIN001AIN110AIN211AIN300AIN401AIN510AIN611AIN7
SCAN1SCAN0
SCAN MODE
(CHANNEL N IS SELECTED BY
BITS CHSEL2, CHSEL1, AND CHSEL0)0Scans channels 0 through N.Scans channels N through the highest
numbered channel.cans channel N r epeated l y. The AD C
aver ag ing reg i ster sets the numb er ofesul ts.N o scan. C onver ts channel N once onl y.
*See below for bit details.
**Channels 4–7 are invalid on the MAX1346/MAX1348. Set
CHSEL2 bit to 0 on those devices.
