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MAX13042EETD+ |MAX13042EETDMAXIMN/a169avai1.62V to 3.6V Improved High-Speed LLT


MAX13042EETD+ ,1.62V to 3.6V Improved High-Speed LLTApplicationsUCSP is a trademark of Maxim Integrated Products, Inc.CMOS Logic-Level Portable POS Sys ..
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MAX13042EETD+
1.62V to 3.6V Improved High-Speed LLT
General Description
The MAX13042E–MAX13045E 4-channel, bidirectional
level translators provide the level shifting necessary for
100Mbps data transfer in multivoltage systems. The
MAX13042E–MAX13045E are ideally suited for level
translation in systems with four channels. Externally
applied voltages, VCCand VL, set the logic levels on
either side of the device. Logic signals present on theside of the device appear as a high-voltage logic
signal on the VCCside of the device and vice-versa.
The MAX13042E–MAX13045E operate at full speed
with external drivers that source as little as 4mA output
current or larger. Each input/output (I/O) channel is
pulled up to VCC or VLby an internal 30µA current
source, allowing the MAX13042E–MAX13045E to be
driven by either push-pull or open-drain drivers.
The MAX13042E–MAX13045E feature an enable (EN)
input that places the devices into a low-power shutdown
mode when driven low. The MAX13042E–MAX13045E
feature an automatic shutdown mode that disables the
part when VCCis less than VL. The state of I/O VCC_and
I/O VL_during shutdown is chosen by selecting the
appropriate part version. (See the Ordering Information/
Selector Guide).
The MAX13042E–MAX13045E operate with VCCvolt-
ages from +2.2V to +3.6V and VLvoltages from +1.62V
to +3.2V, making them ideal for data transfer between
low-voltage ASIC/PLDs and higher voltage systems.
The MAX13042E–MAX13045E are available in 12-bump
UCSP™ (1.54mm x 2.12mm) and 14-pin TDFN (3mm x
3mm) packages, and operate over the extended -40°C
to +85°C temperature range.
Applications
Features
Compatible with 4mA Input Drivers or Larger100Mbps Guaranteed Data RateFour Bidirectional ChannelsEnable Input±15kV ESD Protection on I/O VCC_Lines+1.62V ≤VL+3.2V and +2.2V ≤VCC+3.6V
Supply Voltage Range
12-Bump UCSP (1.54mm x 2.12mm) and
14-Pin TDFN (3mm x 3mm) Lead-Free Packages
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT

19-0792; Rev 0; 4/07
EVALUATION KITAVAILABLE
Ordering Information/Selector Guide

GNDGNDGND
+1.8V
SYSTEM
CONTROLLER
+3.3V
SYSTEMVCC
I/O VL_I/O VCC_DATA DATA
+3.3V+1.8V
1μF0.1μF0.1μF
MAX13042E–
MAX13045E4ypical Operating Circuit
PARTPIN-
PACKAGE
I/O VL_ STATE DURING
SHUTDOWN
I/O VCC_ STATE DURING
SHUTDOWN
TOP
MARKPKG CODE
MAX13042EEBC+T
12 UCSP-12High ImpedanceHigh ImpedanceADQB12-3
MAX13042EETD+T14 TDFN-EP**High ImpedanceHigh ImpedanceADET1433-2
Note:
All devices operate over the -40°C to +85°C temperature
range.
*Future product—contact factory for availability.
**EP = Exposed paddle.
Pin Configurations appear at end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information/Selector Guide continued at end of
data sheet.

CMOS Logic-Level
Translation
Low-Voltage ASIC Level
Translation
Cell Phones
SPI™, MICROWIRE™
Level Translation
Portable POS Systems
Portable Communication
Devices
GPS
Telecommunications
Equipment
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VCC, VL.....................................................................-0.3V to +4V
I/O VCC_..................................................... -0.3V to (VCC+ 0.3V)
I/O VL_...........................................................-0.3V to (VL+ 0.3V)
EN.............................................................................-0.3V to +4V
Short-Circuit Duration I/O VL_, I/O VCC_to GND.......Continuous
Continuous Power Dissipation (TA= +70°C)
12-Bump UCSP (derate 6.5mW/°C above +70°C)......519mW
14-Pin TDFN (derate 24.4mW/°C above +70°C).......1951mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS

(VCC= +2.2V to +3.6V, VL= +1.62V to +3.2V, EN = VL, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC=
+3.3V, VL= +1.8V, and TA= +25°C.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLIES

VL Supply RangeVL1.623.2V
VCC Supply RangeVCC2.23.6V
Supply Current from VCCIQVCCI/O VCC_ = VCC, I/O VL_ = VL25µA
Supply Current from VLIQVLI/O VCC_ = VCC, I/O VL_ = VL10µA
VCC Shutdown Supply CurrentISHDN-VCCTA = +25°C, EN = GND0.11µA
TA = +25°C, EN = GND0.11VL Shutdown-Mode Supply
CurrentISHDN-VLTA = +25°C, EN = VL, VCC = GND0.14µA
I/O VCC_, I/O VL_ Tri-State
Leakage CurrentILEAKTA = +25°C, EN = GND0.12 µA
EN Input Leakage CurrentILEAK_ENTA = +25°C1µA
VL - VCC Shutdown Threshold
HighVTH_HVCC rising (Note 3)00.1VL0.8V
VL - VCC Shutdown Threshold
LowVTH_LVCC falling (Note 3)00.12VL0.8V
I/O VCC_ Pulldown Resistance
During ShutdownRVCC_PD_SDMAX13043E/MAX13045E1016.523kΩ
I/O VL_ Pulldown Resistance
During ShutdownRVL_PD_SDMAX13044E/MAX13045E1016.523kΩ
I/O VL_ Pullup CurrentIVL_PU_I/O VL_ = GND, I/O VCC_ = GND2065µA
I/O VCC_ Pullup CurrentIVCC_PU_I/O VCC_ = GND, I/O VL_ = GND2065µA
I/O VL_ to I/O VCC_ DC
ResistanceRIOVL_IOVCC(Note 4)3kΩ
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ESD PROTECTION

I/O VL_, ENHuman Body Model±2kV
Human Body Model, CVCC = 1µF±15
IEC 61000-4-2 Air-Gap Discharge,
CVCC = 1µF±15I/O VCC_
IEC 61000-4-2 Contact Discharge,
CVCC = 1µF±8
LOGIC LEVELS

I/O VL_ Input-Voltage High
ThresholdVIHL(Note 5)VL - 0.2V
I/O VL_ Input-Voltage Low
ThresholdVILL(Note 5)0.15V
I/O VCC_ Input-Voltage High
ThresholdVIHC(Note 5)VCC -
0.4V
I/O VCC_ Input-Voltage Low
ThresholdVILC(Note 5)0.2V
EN Input-Voltage-High
ThresholdVIHVL - 0.4V
EN Input-Voltage-Low
ThresholdVIL0.4V
I/O VL_ Output-Voltage HighVOHLI/O VL_ source current = 20µA2/3 VLV
I/O VL_ Output-Voltage LowVOLLI/O V L _ si nk cur r ent = 20µA, I/O V C C _ < 0.2V 1/3 VLV
I/O VCC_ Output-Voltage HighVOHCI/O VCC_ source current = 20µA2/3 VCCV
I/O VCC_ Output-Voltage LowVOLCI/O V C C _ si nk cur r ent = 20µA,
I/O V L _ < 0.15V 1/3 VCCV
RISE-/FALL-TIME ACCELERATOR STAGE

On falling edge3.5Accelerator Pulse DurationOn rising edge3.5ns
VL = 1.62V24VL Output Accelerator Source
ImpedanceVL = 3.2V11Ω
VCC = 2.2V13VCC Output Accelerator Source
ImpedanceVCC = 3.6V9Ω
VL = 1.62V14VL Output Accelerator Sink
ImpedanceVL = 3.2V10Ω
VCC = 2.2V11VCC Output Accelerator Sink
ImpedanceVCC = 3.6V9Ω
ELECTRICAL CHARACTERISTICS (continued)

(VCC= +2.2V to +3.6V, VL= +1.62V to +3.2V, EN = VL, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC=
+3.3V, VL= +1.8V, and TA= +25°C.) (Notes 1, 2)
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

I/O VCC_ Rise TimetRVCCFigure 12.5ns
I/O VCC_ Fall TimetFVCCFigure 12.5ns
I/O VL_ Rise TimetRVLFigure 22.5ns
I/O VL_ Fall TimetFVLFigure 22.5ns
Propagation Delay
(Driving I/O VL_)tPVL-VCCFigure 16.5ns
Propagation Delay
(Driving I/O VCC_)tPVCC-VLFigure 26.5ns
Channel-to-Channel SkewtSKEW(Note 4)0.7ns
Propagation Delay From I/O VL_
to I/O VCC_ after ENtEN-VCCFigure 35µs
Propagation Delay From I/O VCC_
to I/O VL_ after ENtEN-VLFigure 35µs
Maximum Data RatePush-pull operation100Mbps
TIMING CHARACTERISTICS

(+2.2V ≤VCC≤+3.6V, +1.62V ≤VL≤+3.2V; CIOVL_≤15pF, CIOVCC_≤10pF; RSOURCE< 150Ω, rise/fall time < 3ns, EN = VL, = -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, VL= +1.8V, and TA= +25°C.) (Notes 1, 2)
Note 1:
All units are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed by
correlation and design and not production tested.
Note 2:
VLmust be less than or equal to VCCduring normal operation. However, VLcan be greater than VCCduring startup and
shutdown conditions.
Note 3:
When VCCis below VLby more than the VL- VCCshutdown threshold, the device turns off its pullup generators and the I/Os
enter their respective shutdown states.
Note 4:
Guaranteed by design.
Note 5:
Input thresholds are referenced to the boost circuit.
Typical Operating Characteristics

(VCC= 3.3V, VL= 1.8V, CIOVCC_= 10pF, CIOVL_= 15pF, RSOURCE= 150Ω, data rate = 100Mbps, push-pull driver, TA= +25°C,
unless otherwise noted.)
VL SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING ONE I/O VL_)
MAX13042E toc01
VCC SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
VL SUPPLY CURRENT vs. VL SUPPLY
VOLTAGE (DRIVING ONE I/O VCC_)
MAX13042E toc02
VL SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
VCC = 3.6V
VCC SUPPLY CURRENT vs. VCC SUPPLY
VOLTAGE (DRIVING ONE I/O VL_)
MAX13042E toc03
VL SUPPLY VOLTAGE (V)
CC
SUPPLY CURRENT (mA)
2.42.63.43.6
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
Typical Operating Characteristics (continued)

(VCC= 3.3V, VL= 1.8V, CIOVCC_= 10pF, CIOVL_= 15pF, RSOURCE= 150Ω, data rate = 100Mbps, push-pull driver, TA= +25°C,
unless otherwise noted.)
VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE
(DRIVING ONE I/O VCC_)

VL SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX13042E toc04
VCC = 3.6V
SUPPLY CURRENT vs. TEMPERATURE
(DRIVING ONE I/O VCC_)

TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX13042E toc05
IVCC
IVL
SUPPLY CURRENT vs. TEMPERATURE
(DRIVING ONE I/O VL_)
MAX13042E toc06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
IVCC
IVL
CAPACITIVE LOAD (pF)
SUPPLY CURRENT (
MAX13042E toc07152025303540
VL SUPPLY CURRENT vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING ONE I/O VCC_)
VCC SUPPLY CURRENT vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING ONE I/O VL_)
CAPACITIVE LOAD (pF)
SUPPLY CURRENT (mA)
MAX13042E toc08152025303540
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
MAX13042E toc09152025303540
RISE/FALL TIME vs. CAPACITIVE LOAD ON
I/O VCC_ (DRIVING I/O VL_)
tRVCC
tFVCC
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
MAX13042E toc10152025303540
RISE/FALL TIME vs. CAPACITIVE LOAD ON
I/O VL_ (DRIVING I/O VCC_)
tFVL
tRVL
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VCC_ (DRIVING I/O VL_)

CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
MAX13042E toc11152025303540
tPHL
tPLH
PROPAGATION DELAY vs. CAPACITIVE
LOAD ON I/O VL_ (DRIVING I/O VCC_)
MAX13042E toc12
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)203540
tPHL
tPLH
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
Pin Description
PIN
UCSPTDFNNAMEFUNCTION
8I/O VCC4Input/Output 4. Referenced to VCC.10I/O VCC3Input/Output 3. Referenced to VCC.12I/O VCC2Input/Output 2. Referenced to VCC.14I/O VCC1Input/Output 1. Referenced to VCC.9VCC
Power-Supply Voltage, +2.2V to +3.6V. Bypass VCC to GND with a
0.1µF ceramic capacitor. For full ESD protection, connect an
additional 1µF ceramic capacitor from VCC to GND as close to the
VCC input as possible.6VLLogic Supply Voltage, +1.62V to +3.2V. Bypass VL to GND with a
0.1µF ceramic capacitor placed as close to the device as possible.2ENEnable Input. Drive EN to GND for shutdown mode, or drive EN to
VL or VCC for normal operation.13GNDGround7I/O VL4Input/Output 4. Referenced to VL.5I/O VL3Input/Output 3. Referenced to VL.3I/O VL2Input/Output 2. Referenced to VL.1I/O VL1Input/Output 1. Referenced to VL.4, 11N.C.No Connection. Leave N.C. unconnected.EPEPExposed Pad. Connect exposed pad to GND.ypical Operating Characteristics (continued)
(VCC= 3.3V, VL= 1.8V, CIOVCC_= 10pF, CIOVL_= 15pF, RSOURCE= 150Ω, data rate = 100Mbps, push-pull driver, TA= +25°C,
unless otherwise noted.)
TYPICAL I/O VL_ DRIVING
(FREQUENCY = 26MHz, CIOVCC_ = 40pF)

MAX1342E toc13
I/O VL_
1V/div
I/O VCC_
2V/div
10ns/div
TYPICAL I/O VCC_ DRIVING
(FREQUENCY = 26MHz, CIOVL_ = 15pF)

MAX1342E toc14
I/O VL_
1V/div
I/O VCC_
2V/div
10ns/div
MAX13042E–MAX13045E
1.62V to 3.6V Improved High-Speed LLT
Test Circuits/Timing Diagrams

MAX13042E–MAX13045E
tFVCCtRVCC
I/O VL_I/O VCC_
150ΩVCC
10%10%
90%90%
50%50%
50%50%
VCC
CIOVCC
tPLHtPHL
tPVL-VCC = tPLH OR tPHL
VCCENVL
I/O VCC_
I/O VL_
Figure 1. Push-Pull Driving I/O VL_Test Circuit and Timing
MAX13042E–MAX13045E
tFVLtRVL VCC
10%10%
90%90%
50%50%
50%50%
VCC
CIOVL
I/O VCC_VLVCCEN
150Ω
I/O VL_
I/O VL_I/O VCC_
tPLHtPHL
tPVCC-VL = tPLH OR tPHL
Figure 2. Push-Pull Driving I/O VCC_Test Circuit and Timing
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