IC Phoenix
 
Home ›  MM24 > MAX1295ACEI+,265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
MAX1295ACEI+ Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
MAX1295ACEI+ |MAX1295ACEIMAXIM/DALLASN/a2avai265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface


MAX1295ACEI+ ,265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacitor a ..
MAX1295BCEI ,265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V, COM = GND, REFADJ = V , V = +2.5V, 4.7μF capacitor a ..
MAX1295BEEI ,265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD8 2 27 D11Industrial Control Systems Data LoggingD7 3 26 VDDEnergy Management Patient ..
MAX1296ACEG ,420ksps / +5V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = +5V ±10%, COM = GND, REFADJ = V , V = +2.5V, 4.7μF capacitor at REF ..
MAX1296AEEG+ ,420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceELECTRICAL CHARACTERISTICS(V = +5V ±10%, COM = GND, REFADJ = V , V = +2.5V, 4.7µF capacitor at REF ..
MAX1296BCEG ,420ksps / +5V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel InterfaceFeaturesThe MAX1294/MAX1296 low-power, 12-bit analog-to-♦ 12-Bit Resolution, ±0.5LSB Linearitydigit ..
MAX3800UTJ+T ,3.2Gbps Adaptive Equalizer and Cable DriverELECTRICAL CHARACTERISTICS(V = +3.14V to +3.46V, T = 0°C to +85°C. Typical values are at V = +3.3V ..
MAX3801UGG ,PLASTIC ENCAPSULATED DEVICESapplications. The equalizer includes differential CML data inputs and outputs, a loss-of-signal (LO ..
MAX3801UTG+ ,3.2Gbps Adaptive EqualizerELECTRICAL CHARACTERISTICS(V = +3.14V to +3.46V, T = 0°C to +85°C. Typical values are at V = +3.3V ..
MAX3801UTG+T ,3.2Gbps Adaptive EqualizerApplicationsTEMP PIN- PACKAGESDH/SONET Transmission EquipmentPARTRANGE PACKAGE CODEMAX3801UGG 0°C t ..
MAX3802UGK ,3.2Gbps Quad Adaptive Cable Equalizer with Cable DriverApplications ESD Protection on Cable Inputs and OutputsHigh-Speed Links in Communications and Data ..
MAX3802UGK-D ,3.2Gbps Quad Adaptive Cable Equalizer with Cable DriverApplications● High-Speed Links in Communications and Data Ordering Information Systems● Backplane ..


MAX1295ACEI+
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
General Description
The MAX1295/MAX1297 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed 12-bit parallel interface. They operate with
a single +2.7V to +3.6V analog supply.
Power consumption is only 5.4mW at the maximum
sampling rate of 265ksps. Two software-selectable
power-down modes enable the MAX1295/MAX1297 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can reduce sup-
ply current below 10µA at lower sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1295 has
six input channels and the MAX1297 has two (three
input channels and one input channel, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, combined
with ease of use and small package size, make these con-
verters ideal for battery-powered and data-acquisition
applications or for other circuits with demanding power-
consumption and space requirements.
The MAX1295/MAX1297 tri-states INTwhen CSgoes high.
Refer to MAX1265/MAX1267 if tri-stating INTis not desired.
The MAX1295 is offered in a 28-pin QSOP package, while
the MAX1297 comes in a 24-pin QSOP. For pin-compati-
ble +5V, 12-bit versions, refer to the MAX1294/MAX1296
data sheet.
Applications

Industrial Control SystemsData Logging
Energy ManagementPatient Monitoring
Data-Acquisition SystemsTouchscreens
Features
12-Bit Resolution, ±0.5 LSB Linearity+3V Single-Supply OperationInternal +2.5V ReferenceSoftware-Configurable Analog Input Multiplexer
6-Channel Single-Ended/
3-Channel Pseudo-Differential (MAX1295)
2-Channel Single-Ended/
1-Channel Pseudo-Differential (MAX1297)
Software-Configurable Unipolar/Bipolar
Analog Inputs
Low Current
1.9mA (265ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)
Internal 3MHz Full-Power Bandwidth Track/HoldParallel 12-Bit InterfaceSmall Footprint
28-Pin QSOP (MAX1295)
24-Pin QSOP (MAX1297)
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

19-1530; Rev 3; 12/02
EVALUATION KIT
AVAILABLE
Ordering Information
Pin Configurations
Typical Operating Circuits appear at end of data sheet.

D10
D11
VDD
REF
REFADJ
GND
COM
CH0
CH1
CH2
CH3
CH4
CH5
CLK
INT
QSOP

TOP VIEW
MAX1295
Pin Configurations continued at end of data sheet.
PARTTEMP RANGEPIN-PACKAGEINL
(LSB)
MAX1295ACEI
0°C to +70°C28 QSOP±0.5
MAX1295BCEI0°C to +70°C28 QSOP±1
MAX1295AEEI-40°C to +85°C28 QSOP±0.5
MAX1295BEEI-40°C to +85°C28 QSOP±1
MAX1297ACEG
0°C to +70°C24 QSOP±0.5
MAX1297BCEG0°C to +70°C24 QSOP±1
MAX1297AEEG-40°C to +85°C24 QSOP±0.5
MAX1297BEEG-40°C to +85°C24 QSOP±1
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VDD= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
CH0–CH5, COM to GND............................-0.3V to (VDD+ 0.3V)
REF, REFADJ to GND.................................-0.3V to (VDD+ 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT) to GND.......-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C)........667mW
Operating Temperature Ranges
MAX1295_C__/MAX1297_C__........................0°C to +70°C
MAX1295_E__/MAX1297_E__......................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
External acquisition or external clock mode
Internal acquisition/internal clock mode
MAX129_A
External acquisition/internal clock mode
External clock mode
-3dB rolloff
SINAD > 68dB
fIN= 125kHz (Note 4)
fIN1= 49kHz, fIN2= 52kHz
MAX129_B
No missing codes over temperature
CONDITIONS
50Aperture Delay625tACQTrack/Hold Acquisition Time
2.53.03.5µs
tCONVConversion Time (Note 5)
MHz3Full-Power Bandwidth
kHz250Full-Linear Bandwidth-78Channel-to-Channel Crosstalk76IMDIntermodulation Distortion80SFDRSpurious-Free Dynamic RangeTotal Harmonic Distortion
(including 5th-order harmonic)-78THD
±0.5INLRelative Accuracy (Note 2)
Bits12RESResolution6770SINADSignal-to-Noise Plus Distortion
LSB±0.2Channel-to-Channel Offset
Matching
ppm/°C±2.0Gain Temperature Coefficient
LSB±1
LSB±1DNLDifferential Nonlinearity
LSB±4Offset Error
LSB±4Gain Error (Note 3)
UNITSMINTYPMAXSYMBOLPARAMETER

Internal acquisition/internal clock mode
External acquisition or external clock mode
<200ps<50Aperture Jitter
MHz0.14.8fCLKExternal Clock Frequency3070Duty Cycle
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS
(fIN(sine-wave)= 50kHz, VIN= 2.5VP-P, 265ksps, external fCLK= 4.8MHz, bipolar input mode)
CONVERSION RATE
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)

(VDD= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), = TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER

0 to 0.5mA output load
To power down the internal reference
For small adjustments
On/off-leakage-current, VIN= 0 or VDD
Unipolar, VCOM= 0
Bipolar, VCOM= VREF / 21.0VDD +
50mVVREFREF Input Voltage Range4.710Capacitive Bypass at REF0.011Capacitive Bypass at REFADJ
mV/mA0.2Load Regulation (Note 7)VDD- 1REFADJ High Threshold±100REFADJ Input Range15REF Short-Circuit Current2.492.52.51REF Output Voltage12CINInput Capacitance±0.01±1Multiplexer Leakage Current
Analog Input Voltage Range
Single-Ended and Differential
(Note 6)
0 VREF
-VREF/2+VREF/2VIN= VDD
ISOURCE= 1mA
ISINK= 1.6mA
VIN= 0 or VDD
VREF= 2.5V, fSAMPLE= 265ksps±0.1±1ILEAKAGEThree-State Leakage CurrentVDD- 0.5VOHOutput Voltage High0.4VOLOutput Voltage Low15CINInput Capacitance±0.1±1IINInput Leakage Current200VHYSInput Hysteresis0.8VILInput Voltage Low2.0VIHInput Voltage High 200300IREFREF Input Current= VDD2.73.6VDDAnalog Supply Voltage15COUTThree-State Output Capacitance
Internal reference2.52.8
ppm/°C±20TCREFREF Temperature Coefficient
Shutdown mode2
External reference1.92.3
0.91.2Positive Supply Current
Shutdown mode210µA
Power-Supply RejectionPSRVDD= 2.7V to 3.6V, full-scale input±0.4±0.9mV
IDD
Operating mode,
fSAMPLE= 265ksps
Internal reference
External referenceStandby mode
CONVERSION RATE (continued)ANALOG INPUTS
INTERNAL REFERENCE
EXTERNAL REFERENCE AT REF
DIGITAL INPUTS AND OUTPUTS
POWER REQUIREMENTS
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

tTR2070nsCLOAD= 20pF, Figure 1RDRise to Output Disableto CLK Fall Setup TimetCWS40nsCLK Pulse Width HighCLK Period
tCH40Fall to Output Data ValidtDO2070nsFall to INTHigh DelaytINT1100nsFall to Output Data ValidtDO2110ns
CLOAD= 20pF, Figure 1
CLOAD= 20pF, Figure 1
CLOAD= 20pF, Figure 1
tCP208
CLK Pulse Width LowtCL40ns
Data Valid to WRRise TimetDS40nsRise to Data Valid Hold TimetDH0ns
CLK Fall to WRHold TimetCWH40nsto CLK or WRSetup TimetCSWS60ns
CLK or WRto CSHold TimetCSWH0nsPulse WidthtCS100nsPulse Width (Note 8)tWR60ns
tTC20100nsCLOAD= 20pF, Figure 1
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONS
Rise to Output Disable
Note 1:
Tested at VDD= +3V, COM = GND, unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:
Offset nulled.
Note 4:
On channel is grounded; sine wave applied to off channels.
Note 5:
Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Note 6:
Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD.
Note 7:
External load should not change during conversion for specified accuracy.
Note 8:
When bit 5 is set low for internal acquisition, WRmust not return low until after the first falling clock edge of the conversion.
TIMING CHARACTERISTICS

(VDD= +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF= +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle),= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
6kΩ
3kΩ
DOUT
DOUT
VDD
a) HIGH-Z TO VOH AND VOL TO VOHb) HIGH-Z TO VOL AND VOH TO VOL

CLOAD
20pF
CLOAD
20pF
Figure 1. Load Circuits for Enable/Disable Times
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1295/7toc01
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1295/7toc02
DIGITAL OUTPUT CODE
DNL (LSB)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1295/7 toc03
VDD (V)
IDD
(mA)
RL = ∞
CODE = 101010100000
SUPPLY CURRENT vs. TEMPERATURE
MAX1295/7 toc04
TEMPERATURE (°C)
IDD
(mA)
RL = ∞
CODE = 101010100000
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX1295/7 toc05
VDD (V)
STANDBY I
STANDBY CURRENT
vs. TEMPERATURE
MAX1295/7 toc06
TEMPERATURE (°C)
STANDBY I
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1295/7 toc07
VDD (V)
POWER-DOWN I
POWER-DOWN CURRENT
vs. TEMPERATURE
MAX1295/7 toc08
TEMPERATURE (°C)
POWER-DOWN I
Typical Operating Characteristics
(VDD= +3V, VREF= +2.500V, fCLK= 4.8MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
0.11k100k10110010k1M
SUPPLY CURRENT
vs. SAMPLE FREQUENCY

MAX1295/7toc02a
fSAMPLE (Hz)
IDD
10,000
WITH EXTERNAL REFERENCE
WITH INTERNAL REFERENCE
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interfaceypical Operating Characteristics (continued)

(VDD= +3V, VREF= +2.500V, fCLK= 4.8MHz, CL= 20pF, TA = +25°C, unless otherwise noted.)
MAX1295/7toc10
REF
(mA)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1295/7 toc11
VDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
MAX1295/7 toc12
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1295/7 toc13
VDD (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1295/7 toc14
TEMPERATURE (°C)
GAIN ERROR (LSB)
MAX1295/7toc09
REF
(V)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
VDD (V)
FFT PLOT
MAX1295/7toc15
FREQUENCY (kHz)
AMPLITUDE (dB)
VDD = 3V
fIN = 50kHz
fSAMPLE = 250ksps
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
1010
INT111112121313
CLK141466778899554433221
Three-State Digital I/O Line (D0)
INTgoes low when the conversion is complete and output data is ready.
Active-Low Read Select. If CSis low, a falling edge on RDenables the read
operation on the data bus.
Active-Low Write Select. When CSis low in the internal acquisition mode, a rising
edge on WRlatches in configuration data and starts an acquisition plus a conver-
sion cycle. When CSis low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
In internal clock mode, connect this pin to either VDDor GND.
Three-State Digital I/O Line (D4)
Three-State Digital I/O Line (D3)
Three-State Digital I/O Line (D2)
Three-State Digital I/O Line (D1)
Three-State Digital I/O Line (D5)
Three-State Digital I/O Line (D6)
Three-State Digital I/O Line (D7)
Three-State Digital Output (D8)
Three-State Digital Output (D9)
GND1923
REFADJ2024
CH2—19
CH11620
CH01721
COM1822
CH3—18
CH4—17
CH5—161515
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with
a 0.01µF capacitor. When using an external reference, connect REFADJ to VDDto
disable the internal bandgap reference.
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to ±0.5 LSB during conversion.
Analog Input Channel 3
Analog Input Channel 4
Analog Input Channel 5
Active-Low Chip Select. When CSis high, digital outputs (INT, D11–D0) are high
impedance.
PIN
MAX1297MAX1295
NAMEFUNCTION
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description (continued)
PIN
MAX1297

REF2125
MAX1295
NAME

Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor
to GND when using the internal reference.
FUNCTION
22VDDAnalog +2.7V to +3.6V Power Supply. Bypass with a 0.1µF capacitor to GND.23D11Three-State Digital Output (D11)24D10Three-State Digital Output (D10)
_______________Detailed Description
Converter Operation

The MAX1295/MAX1297 ADCs use a successive-
approximation (SAR) conversion technique and an input
track/hold (T/H) stage to convert an analog input signal
to a 12-bit digital output. This output format provides an
easy interface to standard microprocessors (µPs). Figure
2 shows the simplified internal architecture of the
MAX1295/MAX1297.
Single-Ended and
Pseudo-Differential Operation

The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1295
(Figure 3a) and to CH0–CH1 for the MAX1297 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
T/H
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
17kΩ
SUCCESSIVE-
APPROXIMATION
REGISTER
CHARGE REDISTRIBUTION
12-BIT DAC
CLOCK
ANALOG
INPUT
MULTIPLEXER
CONTROL LOGIC
LATCHES
REFREFADJ
1.22V
REFERENCE
D0–D11
12-BIT DATA BUS
(CH5)
(CH4)
(CH3)
(CH2)
CH1
CH0
COM
CLK
INT
( ) ARE FOR MAX1295 ONLY.
VDD
GND
MAX1295
MAX1297
AV =
COMP
Figure 2. Simplified Functional Diagram of 6-/2-Channel MAX1295/MAX1297
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
BIT

PD1, PD0
D7, D6
PD1
and PD0select the various clock and power-down modes.
Full Power-Down Mode. Clock mode is unaffected.ACQMODACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
NAMEFUNCTIONAL DESCRIPTION0
Standby Power-Down Mode. Clock mode is unaffected.1Normal Operation Mode. External clock mode selected.Normal Operation Mode. Internal clock mode selected.SGL/DIF
SGL/DIF= 0: Pseudo-Differential Analog Input Mode
SGL/DIF= 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference
between two channels is measured (Tables 2, 4).UNI/BIP
UNI/BIP= 0: Bipolar Mode
UNI/BIP= 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to VREFcan be converted; in bipolar mode, the
signal can range from -VREF/2 to +VREF/2.
D2, D1, D0A2, A1, A0Address bits A2, A1, A0 select which of the 6/2 (MAX1295/MAX1297) channels is to be converted
(Tables 2, 3).
Table 1. Control-Byte Functional Description

the analog inputs. This configuration is pseudo-differ-
ential in that only the signal at IN+ is sampled. The
return side (IN-) must remain stable within ±0.5 LSB
(±0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. At the
end of the acquisition interval, the T/H switch opens,
retaining charge on CHOLDas a sample of the signal
at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at
the comparator’s positive input. The capacitive digital-
to-analog converter (DAC) adjusts during the remain-
Figure 3a. MAX1295 Simplified Input StructureFigure 3b. MAX1297 Simplified Input Structure
CH0
CH1
CH2
CH3
CH4
CH5
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800Ω
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3, AND CH4/CH5
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
CH0
CH1
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
800Ω
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR+
12pF
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
MAX1295/MAX1297
265ksps, +3V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface

der of the conversion cycle to restore node ZERO to 0V
within the limits of 12-bit resolution. This action is equiv-
alent to transferring a 12pF (VIN+- VIN-) charge from
CHOLDto the binary-weighted capacitive DAC, which in
turn forms a digital representation of the analog input
signal.
Analog Input Protection

Internal protection diodes, which clamp the analog
input to VDDand GND, allow each input channel to
swing within (GND - 300mV) to (VDD+ 300mV) without
damage. However, for accurate conversions near full
scale, both inputs must not exceed (VDD+ 50mV) or be
less than (GND - 50mV).
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
Track/Hold

The MAX1295/MAX1297 T/H stage enters its tracking
mode on WR’s rising edge. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this is approximately 1µs after writing the control
byte.
In single-ended operation, IN- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, IN- connects to the nega-
tive “-” input, and the difference of |(IN+) - (IN-)|is sam-
pled. At the beginning of the next conversion, the
positive input connects back to IN+ and CHOLD
charges to the input signal.
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
tACQ= 9 (RS+ RIN) CIN
where RSis the source impedance of the input signal,
RIN(800Ω) is the input resistance, and CIN(12pF) is
the input capacitance of the ADC. Source impedances
below 3kΩhave no significant impact on the MAX1295/
MAX1297’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.CH0+0-01
CH2*CH4*
-00+
CH3*
0
CH1COM

CH5*
+-00-11-+1
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF= 1)
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF= 0)CH0
+0-0-1
CH2*CH4*
00+-
CH3*

CH1

CH5*
-+00-11-+1
*Channels CH2–CH5 apply to MAX1295 only.
*Channels CH2–CH5 apply to MAX1295 only.
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED