MAX1284BESA+-MAX1284BESA+T Fast Delivery |IC PHOENIX CO.,LIMITED

MAX1284BESA+T ,400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal ReferenceApplicationsPIN- SUPPLYPART TEMP RANGEPortable Data LoggingPACKAGE VOLTAGE (V)Data AcquisitionMAX12 ..
MAX1285BCSA ,400ksps/300ksps / Single-Supply / Low-Power / Serial 12-Bit ADCs with Internal ReferenceELECTRICAL CHARACTERISTICS—MAX1284 (continued)(V = +4.5V to +5.5V; f = 6.4MHz, 50% duty cycle, 16 c ..
MAX1286EKA ,150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCsFeaturesThe MAX1286–MAX1289 are low-cost, micropower, seri-♦ Single-Supply Operational output 12-bi ..
MAX1286ETA+ ,150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCsELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V, V = +2.5V for MAX1287/MAX1289, or VDD = +4.75V to +5 ..
MAX1287EKA+T ,150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCsApplicationsLow-Power Data Acquisition PART PIN-PACKAGE TOP MARKPortable Temperature MonitorsMAX128 ..
MAX128AEAI ,Multirange, +5V, 12-Bit DAS with 2-Wire Serial Interface
MAX3784AUTE+ ,5Gbps PCB EqualizerELECTRICAL CHARACTERISTICS(V = +3V to +3.6V, T = 0°C to +85°C. Typical values are at V = +3.3V and ..
MAX3784AUTE+T ,5Gbps PCB EqualizerFeaturesThe MAX3784/MAX3784A 5Gbps equalizers provide♦ Spans 40in (1m) of FR-4 PCBcompensation for ..
MAX3784UGE-T ,5Gbps PCB EqualizerApplicationsChassis Life ExtensionTOP VIEW4.25Gbps Fibre Channel12 11 9104x Multiplexed 1.25Gbps Et ..
MAX3785UTT+ ,6.25Gbps, 1.8V PC Board EqualizerApplicationsPin ConfigurationsHSBI for ≤ 6.4GbpsTOP VIEW (BUMPS ON BOTTOM OF DIE)Double IEEE 802.3a ..
MAX3786UTJ ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationMAX378619-2727; Rev 2; 6/041.5Gbps Serial ATA-Compatible Mux/Buffer withLoopback and Equalization
MAX3786UTJ+ ,1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and EqualizationApplications+Denotes lead-free package.*EP = Exposed pad.1.5Gbps Serial ATA RedundancyTypical Appli ..

MAX1284BESA+-MAX1284BESA+T
400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
General Description
The MAX1284/MAX1285 12-bit analog-to-digital con-
verters (ADCs) combine a high-bandwidth track/hold
(T/H), a serial interface with high conversion speed, an
internal +2.5V reference, and low power consumption.
The MAX1284 operates from a single +4.5V to +5.5V
supply. The MAX1285 operates from a single +2.7V to
+3.6V supply.
The 3-wire serial interface connects directly to
SPI™/QSPI™/ MICROWIRE™ devices without external
logic. The devices use an external serial-interface clock
to perform successive-approximation analog-to-digital
conversions.
Low power, ease of use, and small package size make
these converters ideal for remote-sensor and data-acqui-
sition applications or for other circuits with demanding
power consumption and space requirements. The
MAX1284/MAX1285 are available in 8-pin SO packages.
These devices are pin-compatible, higher-speed ver-
sions of the MAX1240/MAX1241. Refer to the respec-
tive data sheets for more information.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
____________________________FeaturesSingle-Supply Operation
+4.5V to +5.5V (MAX1284)
+2.7V to +3.6V (MAX1285)±1LSB (max) DNL, ±1LSB (max) INL400ksps Sampling Rate (MAX1284)Internal Track/Hold+2.5V Internal ReferenceLow Power: 2.5mA (400ksps)SPI/QSPI/MICROWIRE 3-Wire Serial-InterfacePin-Compatible, High-Speed Upgrades to
MAX1240/MAX12418-Pin SO Package
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
19-1687; Rev 2; 12/10
TOP VIEW
SCLK
DOUT
GNDREF
SHDN
AIN
VDD
MAX1284
MAX1285
Pin Configuration
Ordering Information
Functional Diagram
AINT/H
DOUT6
OUTPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
12-BIT
SAR
REF4
SHDN
+2.5V REFERENCE
GND
SCLK
MAX1284
MAX1285
VDD
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIREis a trademark of National Semiconductor Corp.
MAX1284/MAX1285
+Denotes a lead(Pb)-free/RoHS-compliant package.
PARTTEMP RANGEPIN-
PACKAGE
SUPPLY
VOLTAGE (V)
MAX1284BCSA+0°C to +70°C8 SO5
MAX1284BESA+-40°C to +85°C8 SO5
MAX1285BCSA+0°C to +70°C8 SO2.7 to 3.6
MAX1285BESA+-40°C to +85°C8 SO2.7 to 3.6
EVALUATION KIT
AVAILABLE
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1284
(VDD= +4.5V to +5.5V; fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA= TMINto
TMAX,unless otherwise noted. Typical values are at TA= +25°C.)
VDDto GND.............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C)..............471mW
Operating Temperature Ranges
MAX1284BCSA/MAX1285BCSA.......................0°C to +70°C
MAX1284BESA/MAX1285BESA.....................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
Soldering Temperature (reflow)......................................+260°C
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)
Resolution12Bits
Relative Accuracy (Note 2)INL±1.0LSB
Differential NonlinearityDNLNo missing codes over temperature±1.0LSB
Offset Error±6.0LSB
Gain Error (Note 3)±6.0LSB
Gain-Error Temperature
Coefficient±0.8ppm/°C
DYNAMIC SPECIFICATIONS (100kHz sine wave, 2.5VP-P, clock = 6.4MHz)
Signal-to-Noise Plus Distortion
RatioSINAD70dB
Total Harmonic DistortionTHDUp to the 5th harmonic-80dB
Spurious-Free Dynamic RangeSFDR80dB
Intermodulation DistortionIMDfIN1 = 99Hz, fIN2 = 102Hz76dB
Full-Power Bandwidth-3dB point6MHz
Full-Linear BandwidthSINAD > 68dB350kHz
CONVERSION RATE
Conversion Time (Note 4)tCONV2.5µs
Track/Hold Acquisition TimetACQ468ns
Aperture Delay10ns
Aperture Jitter< 50ps
Serial Clock FrequencytSCLK0.56.4MHz
Duty Cycle4060%
ANALOG INPUT (AIN)
Input Voltage RangeVAIN02.5V
Input Capacitance18pF
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1284 (continued)
(VDD= +4.5V to +5.5V; fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA= TMINto
TMAX,unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS—MAX1285
(VDD= +2.7V to +3.6V; fSCLK= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA= TMINto
TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL REFERENCE
REF Output VoltageVREF2.482.502.52V
REF Short-Circuit CurrentTA = +25°C30mA
REF Output TempcoTC VREF±15ppm/°C
Load Regulation (Note 5)0 to 1mA output load0.12.0mV/mA
Capacitive Bypass at REF4.710µF
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High VoltageVINH3.0V
Input Low VoltageVINL0.8V
Input HysteresisVHYST0.2V
Input LeakageIINVIN = 0V or VDD±1µA
Input CapacitanceCIN15pF
DIGITAL OUTPUT (DOUT)
Output Voltage LowVOLISINK = 5mA0.4V
Output Voltage HighVOHISOURCE = 1mA4V
Three-State Leakage CurrentILVCS = +5V±10µA
Three-State Output CapacitanceCOUTVCS = +5V15pF
POWER SUPPLY
Positive Supply Voltage (Note 6)VDD4.55.5V
Positive Supply Current (Note 7)IDDVDD = +5.5V2.54.0mA
Shutdown Supply CurrentISHDNSCLK = VDD, SHDN = GND210µA
Power-Supply RejectionPSRVDD = +5V ±10%, midscale input±0.5±2.0mV
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)
Resolution12Bits
Relative Accuracy (Note 2)INL±1.0LSB
Differential NonlinearityDNLNo missing codes over temperature±1.0LSB
Offset Error±6.0LSB
Gain Error (Note 3)±6.0LSB
Gain-Error Temperature
Coefficient±1.6ppm/°C
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1285 (continued)
(VDD= +2.7V to +3.6V; fSCLK= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA= TMINto
TMAX,unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DYNAMIC SPECIFICATIONS (75kHz sine wave, 2.5VP-P, fSAMPLE = 300ksps, fSCLK = 4.8MHz)
Signal-to-Noise Plus Distortion
RatioSINAD70dB
Total Harmonic DistortionTHDUp to the 5th harmonic-80dB
Spurious-Free Dynamic RangeSFDR80dB
Intermodulation DistortionIMDfIN1 = 73kHz, fIN2 = 77kHz76dB
Full-Power Bandwidth-3dB point3MHz
Full-Linear BandwidthSINAD > 68dB250kHz
CONVERSION RATE
Conversion Time (Note 4)tCONV3.3µs
Track/Hold Acquisition TimetACQ625ns
Aperture Delay10ns
Aperture Jitter< 50ps
Serial Clock FrequencytSCLK0.54.8MHz
Duty Cycle4060%
ANALOG INPUT (AIN)
Input Voltage RangeVAIN02.5V
Input Capacitance18pF
INTERNAL REFERENCE
REF Output VoltageVREF2.482.502.52V
REF Short-Circuit CurrentTA = +25°C15mA
REF Output TempcoTC VREF±15ppm/°C
Load Regulation (Note 5)0 to 0.75mA output load0.12.0mV/mA
Capacitive Bypass at REF4.710µF
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High VoltageVINH2.0V
Input Low VoltageVINL0.8V
Input HysteresisVHYST0.2V
Input LeakageIINVIN = 0V or VDD±1µA
Input CapacitanceCIN15pF
DIGITAL OUTPUT (DOUT)
Output Voltage LowVOLISINK = 5mA0.4V
Output Voltage HighVOHISOURCE = 0.5mAVDD - 0.5V
Three-State Leakage CurrentILVCS = +3V±10µA
Three-State Output CapacitanceCOUTVCS = +3V15pF
POWER SUPPLY
Positive Supply Voltage (Note 6)VDD2.73.6V
Positive Supply Current (Note 7)IDDVDD = +3.6V2.53.5mA
Shutdown Supply CurrentISHDNSCLK = VDD, SHDN = GND210µA
Power-Supply RejectionPSRVDD = +2.7V to 3.6V, midscale input±0.5±2.0mV
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
SCLK Rise to CSFall IgnoretCSO35ns
SCLK Rise to CSRise HoldtCSH0nsFall to SCLK Rise SetuptCSS35ns
SCLK Pulse-Width LowtCL62nsRise to SCLK Rise IgnoretCS135ns
SCLK Rise to DOUT HoldtDOH10ns
SCLK Rise to DOUT ValidtDOV80ns
CLOAD= 20pF
CLOAD= 20pF
SCLK Pulse-Width HightCH62ns
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONS
SCLK PeriodtCP156ns
TIMING CHARACTERISTICS—MAX1284 (Figures 1, 2, 8, 9)
(VDD= +4.5V to +5.5V, TA= TMIN to TMAX,unless otherwise noted.)
TIMING CHARACTERISTICS—MAX1285 (Figures 1, 2, 8, 9)
(VDD= +2.7V to +3.6V, TA= TMIN to TMAX,unless otherwise noted.)
Note 1:Tested at VDD= VDD(MIN).
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Internal reference, offset, and reference errors nulled.
Note 4:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5:External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitations.
Note 6:Electrical characteristics are guaranteed from VDD(MIN)to VDD(MAX). For operations beyond this range, see Typical
Operating Characteristics.
Note 7:MAX1284 tested with 20pF on DOUTand fSCLK= 6.4MHz, 0 to 5V. MAX1285 tested with same loads, fSCLK= 4.8MHz,
0 to 3V. DOUT= full scale.Rise to DOUT DisabletDOD10 65nsFall to DOUT EnabletDOE65nsPulse-Width HightCSW100ns
CLOAD= 20pF
CLOAD= 20pF
SCLK Rise to CSFall IgnoretCSO45ns
SCLK Rise to CSRise HoldtCSH0nsFall to SCLK Rise SetuptCSS45ns
SCLK Pulse-Width LowtCL83nsRise to SCLK Rise IgnoretCS145ns
SCLK Rise to DOUT HoldtDOH13ns
SCLK Rise to DOUT ValidtDOV100nsRise to DOUT DisabletDOD13 85ns
CLOAD= 20pF
CLOAD= 20pFFall to DOUT EnabletDOE85ns
CS Pulse-Width HightCSW100ns
CLOAD= 20pF
CLOAD= 20pF
SCLK PeriodtCP208
SCLK Pulse-Width HightCH83ns
PARAMETERSYMBOLMINTYPMAXUNITSCONDITIONS
ns
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
__________________________________________Typical Operating Characteristics
(MAX1284: VDD= +5.0V, fSCLK= 6.4MHz, MAX1285: VDD= +3.0V, fSCLK= 4.8MHz; CLOAD= 20pF, 4.7µF capacitor at REF, = +25°C, unless otherwise noted.)
01k2k3k5k
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1284/5 toc01
DIGITAL OUTPUT CODE
INL (LSB)
02k1k3k4k5k
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1284/5 toc02
DIGITAL OUTPUT CODE
DNL (LSB)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1284/5 toc03
VDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
MAX1284/5 toc04
TEMPERATURE (°C)
OFFSET ERROR (LSB)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1284/5 toc07
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1284/5 toc05
VDD (V)
GAIN ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1284/5 toc06
TEMPERATURE (°C)
GAIN ERROR (LSB)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1284/5 toc08
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)
(MAX1284: VDD= +5.0V, fSCLK= 6.4MHz, MAX1285: VDD= +3.0V, fSCLK= 4.8MHz; CLOAD= 20pF, 4.7µF capacitor at REF, = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX1284/5 toc10
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
VDD = 5V, CONVERTING
VDD = 3V, CONVERTING
VDD = 5V, STATICVDD = 3V, STATIC
Serial-Clock Input. SCLK drives the conversion process and clocks data out at rates up to 6.4MHz
(MAX1284) or 4.8MHz (MAX1285).
PIN
Positive Supply VoltageVDD1
FUNCTIONNAME
Sampling Analog Input, 0 to VREFrangeAIN2
Analog and Digital GroundGND5
Active-Low Chip Select. Initiates conversions on the falling edge. When CSis high, DOUT is high
impedance.CS7
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with 4.7µF
capacitor.REF4
Active-Low Shutdown Input. Pulling SHDNlow shuts down the device and reduces the supply current
to 2µA (typ).SHDN3
SCLK8
Pin Description
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1284/5 toc09
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
CONVERTING
SCLK = 6.4MHz
CONVERTING
SCLK = 4.8MHz
STATIC
CODE = 1111 1111 1111
RL = ∞
CL = 10pF
Serial-Data Output. DOUT changes state at SCLK’s rising edge High impedance when CS is high.DOUT6
Detailed Description
Converter Operation
The MAX1284/MAX1285 use an input T/H and succes-
sive-approximation register (SAR) circuitry to convert
an analog input signal to a digital 12-bit output. Figure
3 shows the MAX1284/MAX1285 in its simplest configu-
ration. The internal reference is trimmed to +2.5V.The
serial interface requires only three digital lines (SCLK,
CS,and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1284/MAX1285 have two modes: normal and
shutdown. Pulling SHDNlow shuts the device down and
reduces supply current to below 2µA (typ), while pulling
SHDNhigh puts the device into operational mode. Pullinglow initiates a conversion that is driven by SCLK. The
conversion result is available at DOUT in unipolar serial
format. The serial data stream consists of three zeros,
followed by the data bits (MSB first). All transitions on
DOUT occur 20ns after the rising edge of SCLK. Figures
8 and 9 show the interface timing information.
Analog Input
Figure 4 illustrates the sampling architecture of the
ADC’s comparator. The full-scale input voltage is set by
the internal reference (VREF= +2.5V).
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input (AIN) charges
capacitor CHOLD. Bringing CSlow, ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLDto GND. The retained charge on CHOLDrep-
resents a sample of the input, unbalancing node ZERO
at the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 12-
bit resolution. This action is equivalent to transferring a
charge from CHOLDto the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
DOUTDOUT
6kΩ
DGND
CLOAD = 20pFCLOAD = 20pF
6kΩ
DGND
VDD
b) High-Z to VOL and VOH to VOLa) High-Z to VOH and VOL to VOH
Figure 1. Load Circuits for DOUT Enable Time
DOUTDOUT
6kΩ
DGND
CLOAD = 20pFCLOAD = 20pF
6kΩ
DGND
VDD
b) VOL to High-Za) VOH to High-Z
Figure 2. Load Circuits for DOUT Disable Time

Partno	Mfg	Dc	Qty	Available	Descript
MAX1284BESA+ \|MAX1284BESA	MAX	N/a	38	avai	400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference
MAX1284BESA+T	MAXIM	N/a	8350	avai	400ksps/300ksps, Single-Supply, Low-Power, Serial 12-Bit ADCs with Internal Reference