MAX1280BCUP+ ,400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal ReferenceApplicationsTOP VIEW+Portable Data Logging CH0 1 20 VDD1Data AcquisitionCH1 2 19 VDD2Medical Instru ..
MAX1280BEUP ,400ksps/300ksps / Single-Supply / Low-Power / 8-Channel / Serial 12-Bit ADCs with Internal ReferenceMAX1280/MAX128119-1684; Rev 0; 5/00400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12- ..
MAX1281BEUP ,400ksps/300ksps / Single-Supply / Low-Power / 8-Channel / Serial 12-Bit ADCs with Internal ReferenceELECTRICAL CHARACTERISTICS—MAX1280(V (V = V = V = +4.5V to +5.5V, COM = GND, f = +4.5V to +5.5V, CO ..
MAX1281BEUP ,400ksps/300ksps / Single-Supply / Low-Power / 8-Channel / Serial 12-Bit ADCs with Internal ReferenceApplicationsTOP VIEWPortable Data Logging CH01 20 VDD1Data Acquisition2CH1 19 VDD2Medical Instrumen ..
MAX1281BEUP+ ,400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal ReferenceELECTRICAL CHARACTERISTICS—MAX1280(V (V = V = V = +4.5V to +5.5V, COM = GND, f = +4.5V to +5.5V, CO ..
MAX1281BEUP+ ,400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal ReferenceFeaturesThe MAX1280/MAX1281 12-bit ADCs combine an 8-chan-♦ 8-Channel Single-Ended or 4-Channelnel ..
MAX3783UCM , 2.7Gbps Dual Mux/Buffer with Loopback
MAX3784AUGE ,+3.3 V, 5 Gbps, PC board equalizerApplicationsChassis Life ExtensionTOP VIEW4.25Gbps Fibre Channel16 15 14 134x Multiplexed 1.25Gbps ..
MAX3784AUTE+ ,5Gbps PCB EqualizerELECTRICAL CHARACTERISTICS(V = +3V to +3.6V, T = 0°C to +85°C. Typical values are at V = +3.3V and ..
MAX3784AUTE+T ,5Gbps PCB EqualizerFeaturesThe MAX3784/MAX3784A 5Gbps equalizers provide♦ Spans 40in (1m) of FR-4 PCBcompensation for ..
MAX3784UGE-T ,5Gbps PCB EqualizerApplicationsChassis Life ExtensionTOP VIEW4.25Gbps Fibre Channel12 11 9104x Multiplexed 1.25Gbps Et ..
MAX3785UTT+ ,6.25Gbps, 1.8V PC Board EqualizerApplicationsPin ConfigurationsHSBI for ≤ 6.4GbpsTOP VIEW (BUMPS ON BOTTOM OF DIE)Double IEEE 802.3a ..
MAX1280BCUP+-MAX1281BEUP+
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
General DescriptionThe MAX1280/MAX1281 12-bit ADCs combine an 8-chan-
nel analog-input multiplexer, high-bandwidth track/hold,
and serial interface with high conversion speed and low
power consumption. The MAX1280 operates from a single
+4.5V to +5.5V supply; the MAX1281 operates from a sin-
gle +2.7V to +3.6V supply. Both devices’ analog inputs
are software configurable for unipolar/bipolar and single-
ended/pseudo-differential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1280/
MAX1281 use an external serial-interface clock to per-
form successive-approximation analog-to-digital con-
versions. Both parts feature an internal +2.5V reference
and a reference-buffer amplifier with a ±1.5% voltage-
adjustment range. An external reference with a 1V to
VDD1range may also be used.
The MAX1280/MAX1281 provide a hard-wired SHDN
pin and four software-selectable power modes (normal
operation, reduced power, fast power-down, and full
power-down). These devices can be programmed to
automatically shut down at the end of a conversion or to
operate with reduced power. When using the power-
down modes, accessing the serial interface automatical-
ly powers up the devices, and the quick turn-on time
allows them to be powered down between all conver-
sions. This technique can cut supply current to under
100µA at reduced sampling rates.
The MAX1280/MAX1281 are available in 20-pin TSSOP
packages. These devices are higher-speed versions of
the MAX146/MAX147 (for more information, see the
respective data sheet).
ApplicationsPortable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
Features8-Channel Single-Ended or 4-Channel
Pseudo-Differential InputsInternal Multiplexer and Track/HoldSingle-Supply Operation
+4.5V to +5.5V (MAX1280)
+2.7V to +3.6V (MAX1281)Internal +2.5V Reference400ksps Sampling Rate (MAX1280)Low Power 2.5mA (400ksps)
1.3mA (Reduced-Power Mode)
0.9mA (Fast Power-Down Mode)
2µA (Full Power-Down)SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin TSSOP Package
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference19-1684; Rev 2; 10/10
Pin Configuration
Ordering InformationSPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
TOP VIEW
TSSOPVDD1
VDD2
DIN
SSTRB
DOUT
GND
REFADJ
REF
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX1280
MAX1281
SHDN
SCLK
EVALUATION KIT
AVAILABLE
PARTTEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
MAX1280BCUP+ 0°C to +70°C20 TSSOP±1
MAX1280BEUP+-40°C to +85°C20 TSSOP±1
MAX1281BCUP+ 0°C to +70°C20 TSSOP±1
MAX1281BEUP+-40°C to +85°C20 TSSOP±1
+Denotes a lead(Pb)-free/RoHS-compliant package.
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX1280(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD_ to GND............................................................-0.3V to +6V
VDD1to VDD2........................................................-0.3V to +0.3V
CH0–CH7, COM to GND..........................-0.3V to (VDD1+ 0.3V)
REF, REFADJ to GND..............................-0.3V to (VDD1+ 0.3V)
Digital Inputs to GND..............................................-0.3V to +6V
Digital Outputs to GND............................-0.3V to (VDD2+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 7.0mW/°C above +70°C).........559mW
Operating Temperature Ranges
MAX128_BCUP..................................................0°C to +70°C
MAX128_BEUP...............................................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
Soldering Temperature (reflow)......................................+260°C
SINAD > 68dB
-3dB point
fIN= 200kHz, VIN= 2.5Vp-p
fIN1= 99kHz, fIN2= 102kHz
No missing codes over temperature
Up to the 5th harmonic
CONDITIONSMHz0.56.4fSCLKSerial Clock Frequency<50Aperture Jitter10Aperture Delay468tACQTrack/Hold Acquisition Time2.5tCONVConversion Time (Note 5)
kHz350Full-Linear Bandwidth
MHz6Full-Power Bandwidth-78Channel-to-Channel Crosstalk
(Note 4)76IMDIntermodulation Distortion80SFDRSpurious-Free Dynamic Range-81THDTotal Harmonic Distortion
Bits12Resolution70SINADSignal-to-Noise plus Distortion
Ratio
LSB±0.1Channel-to-Channel Offset-Error
Matching
ppm/°C ±0.8Gain-Error Temperature
Coefficient
±1.0
LSB±1.0DNLDifferential Nonlinearity
LSB±6.0Offset Error
LSB±7.0Gain Error (Note 3)
UNITSMINTYPMAXSYMBOLPARAMETER4060Duty Cycle
DYNAMIC SPECIFICATIONS(100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)
DC ACCURACY(Note 1)
CONVERSION RATELSBINLRelative Accuracy (Note 2)
ELECTRICAL CHARACTERISTICS—MAX1280(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1280 (continued)(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETERTo power down the internal reference
For small adjustments, from 1.22V
0 to 1mA output load
On/off leakage current, VCH_= 0 or VDD1= +25°C
Bipolar, VCOMor VCH_ = VREF/2,
referenced to COM or CH_
Unipolar, VCOM= 0
V/V2.05Buffer Voltage Gain1.33VDD1REFADJ Buffer Disable
Threshold±50REFADJ Input Range1.22REFADJ Output Voltage0.0110Capacitive Bypass at REFADJ4.710Capacitive Bypass at REF
mV/mA0.12.0Load Regulation (Note 7)
ppm/°C±15TC VREFREF Output Temperature
Coefficient30REF Short-Circuit Current2.4802.5002.520VREFREF Output Voltage18Input Capacitance±0.001±1Multiplexer Leakage Current
±VREF/2V
VREF
VCH_Input Voltage Range, Single-
Ended and Differential (Note 6)
VIN= 0 or VDD2
In power-down, fSCLK= 0
VREF= 2.500V, fSCLK= 0
VREF= 2.500V, fSCLK= 6.4MHz
(Note 8)CINInput Capacitance±1IINInput Leakage0.2VHYSTInput Hysteresis0.8VINLInput Low Voltage3.0VINHInput High Voltage
320µA
REF Input Current1.0VDD1+
50mVREF Input Voltage Range
ISINK= 5mAV0.4VOLOutput Voltage Low
ISOURCE= 1mAV4VOHOutput Voltage High= 5VµA±10ILThree-State Leakage Current= 5VpF15COUTThree-State Output Capacitance
ANALOG INPUTS(CH7–CH0, COM)
EXTERNAL REFERENCE(Reference buffer disabled, reference applied to REF)
INTERNAL REFERENCE
DIGITAL INPUTS(DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS(DOUT, SSTRB)
Supply Current
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
CONDITIONSIVDD1 +
IVDD2Supply Current4.55.5VDD1,
VDD2
Positive Supply Voltage
(Note 9)
UNITSMINTYPMAXSYMBOLPARAMETER
VDD1=
VDD2= 5.5V
ELECTRICAL CHARACTERISTICS—MAX1281(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fSCLK= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
SINAD > 68dB
-3dB point
fIN= 150kHz, VIN= 2.5Vp-p
fIN1= 73kHz, fIN2= 77kHz
No missing codes over temperature
Up to the 5th harmonic
CONDITIONSkHz250Full-Linear Bandwidth
MHz3Full-Power Bandwidth-78Channel-to-Channel Crosstalk
(Note 4)76IMDIntermodulation Distortion80SFDRSpurious-Free Dynamic
Range-81THDTotal Harmonic Distortion
LSB±1.0INLRelative Accuracy (Note 2)
Bits12Resolution70SINADSignal-to-Noise plus
Distortion Ratio
LSB±0.2Channel-to-Channel Offset-
Error Matching
ppm/°C ±1.6Gain-Error Temperature
Coefficient
LSB±1.0DNLDifferential Nonlinearity
LSB±6.0Offset Error
LSB±7.0Gain Error (Note 3)
UNITSMINTYPMAXSYMBOLPARAMETEROperating mode (Note 10)
Reduced-power mode (Note 11)
Fast power-down (Note 11)
Full power-down (Note 11)
VDD1= VDD2= 5V ±10%, midscale inputmV±0.5±2.0PSRPower-Supply Rejection
POWER SUPPLY
DC ACCURACY(Note 1)
DYNAMIC SPECIFICATIONS(75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode)
ELECTRICAL CHARACTERISTICS—MAX1280 (continued)(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1281(continued)(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fSCLK= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Normal operating mode
Normal operating mode
Normal operating mode
CONDITIONSMHz0.54.8fSCLKSerial Clock Frequency< 50Aperture Jitter10Aperture Delay625tACQTrack/Hold Acquisition Time3.3tCONVConversion Time (Note 5)
UNITSMINTYPMAXSYMBOLPARAMETERTo power down the internal reference
For small adjustments, from 1.22V
0 to 0.75mA output load
On/off leakage current, VCH_= 0 or VDD1= +25°C
Bipolar, VCOMor VCH_ = VREF/2,
referenced to COM or CH_
Unipolar, VCOM= 0
V/V2.05Buffer Voltage Gain1.33VDD1- 1REFADJ Buffer Disable
Threshold±50REFADJ Input Range1.22REFADJ Output Voltage0.0110Capacitive Bypass at REFADJ4.710Capacitive Bypass at REF
mV/mA0.12.0Load Regulation (Note 7)
ppm/°C±15TC VREFREF Output Temperature
Coefficient15REF Short-Circuit Current2.4802.5002.520VREFREF Output Voltage18Input Capacitance±0.001±1Multiplexer Leakage Current
±VREF/24060Duty Cycle
VREF
VCH_Input Voltage Range, Single-
Ended and Differential (Note 6)
VIN= 0 or VDD2
In power-down, fSCLK= 0
VREF= 2.500V, fSCLK= 0
VREF= 2.500V, fSCLK= 4.8MHz
(Note 8)15CINInput Capacitance±1IINInput Leakage0.2VHYSTInput Hysteresis0.8VINLInput Low Voltage2.0VINHInput High Voltage
REF Input Current320µA
2003501.0VDD1+
50mVREF Input Voltage Range
CONVERSION RATE
ANALOG INPUTS(CH7–CH0, COM)
INTERNAL REFERENCE
EXTERNAL REFERENCE(Reference buffer disabled, reference applied to REF)
DIGITAL INPUTS(DIN, SCLK, CS, SHDN)
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal ReferenceVDD1=
VDD2= 3.6V
ISOURCE= 0.5mA
CONDITIONSIVDD1+
IVDD2Supply Current (Note 10)2.73.6VDD1,
VDD2VDD2 - 0.5VVOHOutput Voltage High
Positive Supply Voltage
(Note 9)
UNITSMINTYPMAXSYMBOLPARAMETER
ISINK= 5mAV0.4VOLOutput Voltage Low= 3VµA±10ILThree-State Leakage Current= 3VpF15COUTThree-State Output
Capacitance
ELECTRICAL CHARACTERISTICS—MAX1281(continued)(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fSCLK= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS—MAX1280(Figures 1, 2, 6, 7; VDD1= VDD2= +4.5V to +5.5V; TA= TMINto TMAX; unless otherwise noted.)
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CONDITIONS100tCSWCSPulse Width High65tSTECSFall to SSTRB Enable65tDOECSFall to DOUT Enable1065tSTDCSRise to SSTRB Disable1065tDODCSRise to DOUT Disable80tSTVSCLK Rise to SSTRB Valid80tDOVSCLK Rise to DOUT Valid62tCLSCLK Pulse Width Low62tCH156tCPSCLK Period
SCLK Pulse Width High1020tSTHSCLK Rise to SSTRB Hold1020tDOHSCLK Rise to DOUT Hold35tCS1CSRise to SCLK Rise Ignore35tCSOSCLK Rise to CSFall Ignore35tDSDIN to SCLK Setup0tDHDIN to SCLK Hold35tCSSCSFall to SCLK Rise Setup0tCSHSCLK Rise to CSRise Hold
UNITSMINTYPMAXSYMBOLPARAMETEROperating mode
Reduced-power mode (Note 11)
Fast power-down (Note 11)
Full power-down (Note 11)
VDD1= VDD2= 2.7V to 3.6V, midscale inputmV±0.5±2.0PSRPower-Supply Rejection
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER SUPPLY
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1281(Figures 1, 2, 6, 7; VDD1= VDD2= +2.7V to +3.6V; TA= TMINto TMAX; unless otherwise noted.)
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CONDITIONS100tCSWCSPulse Width High85tSTECSFall to SSTRB Enable85tDOECSFall to DOUT Enable1385tSTDCSRise to SSTRB Disable1385tDODCSRise to DOUT Disable100tSTVSCLK Rise to SSTRB Valid100tDOVSCLK Rise to DOUT Valid83tCLSCLK Pulse Width Low83 tCH208tCPSCLK Period
SCLK Pulse Width High120tSTHSCLK Rise to SSTRB Hold1320tDOHSCLK Rise to DOUT Hold45tCS1CSRise to SCLK Rise Ignore45tCSOSCLK Rise to CSFall ignore45tDSDIN to SCLK Setup0tDHDIN to SCLK Hold45tCSSCSFall to SCLK Rise Setup0tCSHSCLK Rise to CSRise Hold
UNITSMINTYPMAXSYMBOLPARAMETER
Note 1:MAX1280 tested at VDD1= VDD2= +5V, MAX1281 tested at VDD1= VDD2= +3V; COM = GND; unipolar single-ended
input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nulled.
Note 3:Offset nulled.
Note 4:Ground “on” channel; sine wave applied to all “off” channels.
Note 5:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:The absolute voltage range for the analog inputs (CH7–CH0, and COM) is from GND to VDD1.
Note 7:External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is a result
of production test limitations.
Note 8:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9:Electrical characteristics are guaranteed from VDD1(MIN)= VDD2(MIN)to VDD1(MAX)= VDD2(MAX). For operations beyond
this range, see theTypical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 10:AIN = midscale. Unipolar mode.MAX1280 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK= 6.4MHz, 0 to 5V.
MAX1281 tested with same loads, fSCLK= 4.8MHz, 0 to 3V. DOUT = FFF hex.
Note 11:
PD1PD0MODE0Full power-down.1Fast power-down.0Reduced power mode.1Normal operation (operating mode).
Typical Operating Characteristics(MAX1280: VDD1= VDD2= 5.0V, fSCLK= 6.4MHz; MAX1281: VDD1= VDD2= 3.0V, fSCLK= 4.8MHz; CLOAD= 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference15002000500100025003000350040004500
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODEMAX1280/1-01
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1280/1-02
DNL (LSB)
DIGITAL OUTPUT CODE
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (CONVERTING)
MAX1280/1-03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs. TEMPERATURE
MAX1280/1-04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1281
MAX1280
NORMAL OPERATION (PD1 = PD0 = 1)
REDP (PD1 = 1, PD0 = 0)
FASTDP (PD1 = 0, PD0 = 1)
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (STATIC)
MAX1280/1-05
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs. TEMPERATURE
(STATIC)
MAX1280/1-06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1280 (PD1 = 1, PD0 = 1)
MAX1280 (PD1 = 1, PD0 = 0)
MAX1280 (PD1 = 0, PD0 = 1)
MAX1281 (PD1 = 1, PD0 = 1)
MAX1281 (PD1 = 1, PD0 = 0)
MAX1281 (PD1 = 0, PD0 = 1)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1280/1-07
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (
(PD1 = PD0 = 0)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1280/1-08
SHUTDOWN CURRENT (
MAX1281
MAX1280
(PD1 = PD0 = 0)
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1280/1-09
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal ReferenceGAIN ERROR vs. SUPPLY VOLTAGE
MAX1280/1-13
VDD (V)
GAIN ERROR (LSB)
Typical Operating Characteristics (continued)(MAX1280:VDD1= VDD2= 5.0V, fSCLK= 6.4MHz; MAX1281:VDD1= VDD2= 3.0V, fSCLK= 4.8MHz; CLOAD= 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1280/1-10
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX1281
MAX1280
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1280/1-11
VDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
MAX1280/1-12
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1280/1-14
TEMPERATURE (°C)
GAIN ERROR (LSB)
MAX1281
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Pin DescriptionPositive Supply VoltageVDD219
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD1.REFADJ12
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CSis high.SSTRB15
Serial Data Input. Data is clocked in at SCLK’s rising edge.DIN16
Active-Low Chip Select. Data will not be clocked into DIN unless CSis low. When CSis high, DOUT
and SSTRB are high impedance.CS17
Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)SCLK18
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a +2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
VDD1.
REF11
Analog and Digital GroundGND13
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CSis high.DOUT14
Active-Low Shutdown Input. Pulling SHDNlow shuts down the device, reducing supply current to 2µA
(typ).SHDN10
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.COM9
PINSampling Analog InputsCH0–CH71–8
FUNCTIONNAMEVDD2
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOLVDD2
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
DOUT
a) VOH to High-Zb) VOL to High-ZFigure 1. Load Circuits for Enable TimeFigure 2. Load Circuits for Disable Time
Positive Supply VoltageVDD120
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Detailed DescriptionThe MAX1280/MAX1281 analog-to-digital converters
(ADCs) use a successive-approximation conversion tech-
nique and input track/hold (T/H) circuitry to convert an
analog signal to a 12-bit digital output. A flexible serial
interface provides easy interface to microprocessors
(µPs). Figure 3 shows a functional diagram of the
MAX1280/MAX1281.
Pseudo-Differential InputThe equivalent input circuit of Figure 4 shows the
MAX1280/MAX1281’s input architecture, which is com-
posed of a T/H, input multiplexer, input comparator,
switched-capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 2 and 3.
The MAX1280/MAX1281 input configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) is connected to the sampling capacitor
while converting and must remain stable within ±0.5LSB
(±0.1LSB for best results) with respect to GND during a
conversion.
If a varying signal is applied to the selected IN-, its ampli-
tude and frequency must be limited to maintain accuracy.
The following equations determine the relationship
between the maximum signal amplitude and its frequency
in order to maintain ±0.5LSB accuracy. Assuming a sinu-
soidal signal at IN-, the input voltage is determined by:
The maximum voltage variation is determined by:
A 650mVp-p 60Hz signal at IN- will generate ±0.5LSB
of error when using a +2.5V reference voltage and a
2.5µs conversion time (15/fSCLK). When a DC reference
voltage is used at IN-, connect a 0.1µF capacitor to
GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLDas a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLDfrom IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1/2 within the limits of 12-bit
resolution. This action is equivalent to transferring a
12pF x (VIN+ - VIN-) charge from CHOLDto the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
max d- - 2f 1LSB VINCONV
REFCONVπ=()≤=VπININ-- sin(2ft)=()V
INPUT
SHIFT
REGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUTSHIFT
REGISTER
+1.22V
REFERENCE
T/HANALOG
INPUT
MUX
12-BITSAR
ADC
DOUT
SSTRB
VDD1
VDD2
GND
SCLK
DIN
COM
REFADJ
REF
OUT
REF
CLOCK
+2.500V
17kΩ
CH67
CH78
CH45
CH56
CH12
CH23
CH34
CH01
MAX1280
MAX1281
SHDN
≈ 2.05*A
CHOLD
RIN
800Ω
12pF
HOLD
INPUT
MUX
CSWITCH*
*INCLUDES ALL INPUT PARASITICS
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
CH0
REF
GND
CH1
CH2
CH3
CH4
CH5
CH6
CH7
ZERO
VDD1/2
COMPARATOR
CAPACITATIVE
DAC
6pF
TRACK
MAX1280/MAX1281
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference10µF0.1µF
2.5V
VDD1
VDD2
GND
COM
SCLK
DIN
DOUT
SSTRB
SHDN
TO VDD2
TO VDD2
0.01µF
CH7
REFADJ
REF
4.7µF
0V TO
2.500V
ANALOG
INPUT
OSCILLOSCOPE
CH1CH2CH3CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
MAX1280
MAX1281
+3V or +5V
EXTERNAL CLOCK
SCLK
SSTRB
DOUT*
0.01µF
Figure 5. Quick-Look Circuit
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter con-
verts the “+” input. If the converter is set up for differen-
tial inputs, the difference of [(IN+) - (IN-)] is converted.
At the end of the conversion, the positive input con-
nects back to IN+ and CHOLDcharges to the input sig-
nal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
tACQ= 9 ✕(RS+ RIN) ✕12pF
where RIN= 800Ω, RS= the source impedance of the
input signal; tACQis never less than 468ns (MAX1280)
or 625ns (MAX1281). Note that source impedances
below 2kΩdo not significantly affect the ADC’s AC per-
formance.
Input BandwidthThe ADC’s input tracking circuitry has a 6MHz
(MAX1280) or 3MHz (MAX1281) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti-
alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDD1and GND, allow the channel input pins to
swing from GND - 0.3V to VDD1+ 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDD1by more than 50mV or
be lower than GND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not allow the input current to exceed 2mA.
Quick LookTo quickly evaluate the MAX1280/MAX1281’s analog
performance, use the circuit of Figure 5. The MAX1280/
MAX1281 require a control byte to be written to DIN
before each conversion. Connecting DIN to VDD2feeds
in control bytes of $FF (HEX), which trigger single-
ended unipolar conversions on CH7 without powering
down between conversions. The SSTRB output pulses
