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MAX125CCAX+D |MAX125CCAXDMAXIMN/a78avai2x4-Channel, Simultaneous-Sampling, 14-Bit DAS
MAX125CCAX+D |MAX125CCAXDMAXIM/DALLASN/a40avai2x4-Channel, Simultaneous-Sampling, 14-Bit DAS
MAX125CEAX+ |MAX125CEAXMAXIMN/a150avai2x4-Channel, Simultaneous-Sampling, 14-Bit DAS
MAX125CEAX+D |MAX125CEAXDMAXIMN/a3592avai2x4-Channel, Simultaneous-Sampling, 14-Bit DAS
MAX126CCAX+D |MAX126CCAXDMAXIMN/a34avai2x4-Channel, Simultaneous-Sampling, 14-Bit DAS
MAX126CCAX+D |MAX126CCAXDMAXIM/DALLASN/a30avai2x4-Channel, Simultaneous-Sampling, 14-Bit DAS
MAX126CEAX+D |MAX126CEAXDMAXIMN/a1avai2x4-Channel, Simultaneous-Sampling, 14-Bit DAS


MAX125CEAX+D ,2x4-Channel, Simultaneous-Sampling, 14-Bit DASMAX125/MAX12619-1319; Rev 3; 7/082x4-Channel, Simultaneous-Sampling14-Bit DAS
MAX1261ACEI+ ,250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel InterfaceApplicationsD4 5 24 GNDMAX1261Industrial Control Systems Data LoggingD3/D11 6 23 COMEnergy Manageme ..
MAX1265ACEI ,265ksps / +3V / 6-/2-Channel / 12-Bit ADCs with +2.5V Reference and Parallel Interface
MAX1266BEEI ,420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
MAX126CCAX ,2x4-Channel, Simultaneous-Sampling 14-Bit DASELECTRICAL CHARACTERISTICS(V = +2.7V to +5.25V; COM = 0V; f = 2.0MHz; external clock (50% duty cycl ..
MAX126CCAX+D ,2x4-Channel, Simultaneous-Sampling, 14-Bit DASApplicationsMultiphase Motor ControlPower-Grid SynchronizationPower-Factor MonitoringTypical Operat ..
MAX3735AETG ,2.7Gbps, Low-Power SFP Laser DriversApplications*Dice are designed to operate from -40°C to +85°C, but areGigabit Ethernet SFP/SFF Tran ..
MAX3735AETG+ ,2.7Gbps, Low-Power SFP Laser DriversELECTRICAL CHARACTERISTICS(V = +2.97V to +3.63V, T = -40°C to +85°C. Typical values at V = +3.3V, I ..
MAX3735AETG+T ,2.7Gbps, Low-Power SFP Laser DriversApplicationsMAX3735AETG+ -40°C to +85°C 24 Thin QFN-EP**Gigabit Ethernet SFP/SFF Transceiver Module ..
MAX3735EGG ,2.7Gbps, Low-Power SFP Laser DriversELECTRICAL CHARACTERISTICS(V = +2.97V to +3.63V, T = -40°C to +85°C. Typical values at V = +3.3V, I ..
MAX3736ETE+ ,3.2Gbps, Low-Power, Compact, SFP Laser DriverApplicationsMAX3736ETE -40°C to +85°C 16 Thin QFN-EP* MAX3736ETE+ -40°C to +85°C 16 Thin QFN-EP* Gi ..
MAX3736ETE+T ,3.2Gbps, Low-Power, Compact, SFP Laser DriverELECTRICAL CHARACTERISTICS(V = +2.97V to +3.63V, T = -40°C to +85°C. Typical values are at V = +3.3 ..


MAX125CCAX+D-MAX125CEAX+-MAX125CEAX+D-MAX126CCAX+D-MAX126CEAX+D
2x4-Channel, Simultaneous-Sampling, 14-Bit DAS
General Description
The MAX125/MAX126 are high-speed, multichannel,
14-bit data-acquisition systems (DAS) with simultaneous
track/holds (T/Hs). These devices contain a 14-bit, 3µs,
successive-approximation analog-to-digital converter
(ADC), a +2.5V reference, a buffered reference input,
and a bank of four simultaneous-sampling T/H ampli-
fiers that preserve the relative phase information of the
sampled inputs. The MAX125/MAX126 have two multi-
plexed inputs for each T/H, allowing a total of eight
inputs. In addition, the converter is overvoltage tolerant
to ±17V; a fault condition on any channel will not harm
the IC. Available input ranges are ±5V (MAX125) and
±2.5V (MAX126).
An on-board sequencer converts one to four channels
per CONVSTpulse. In the default mode, one T/H output
(CH1A) is converted. An interrupt signal (INT) is provided
after the last conversion is complete. Convert two,
three, or four channels by reprogramming the
MAX125/MAX126 through the bidirectional parallel
interface. Once programmed, the MAX125/MAX126
continue to convert the specified number of channels
per CONVSTpulse until they are reprogrammed. The
channels are converted sequentially, beginning with
CH1. The INTsignal always follows the end of the last
conversion in a conversion sequence. The ADC con-
verts each assigned channel in 3µs and stores the
result in an internal 14x4 RAM. Upon completion of the
conversions, data can be accessed by applying suc-
cessive pulses to the RDpin. Four successive reads
access four data words sequentially.
The parallel interface’s data-access and bus-release
timing specifications are compatible with most popular
digital signal processors and 16-bit/32-bit microproces-
sors, so the MAX125/MAX126 conversion results can
be accessed without resorting to wait states.
Applications

Multiphase Motor Control
Power-Grid Synchronization
Power-Factor Monitoring
Digital Signal Processing
Vibration and Waveform Analysis
Features
Four Simultaneous-Sampling T/H Amplifiers with
Two Multiplexed Inputs (eight single-ended inputs
total)
3µs Conversion Time per Channel Throughput: 250ksps (1 channel)
142ksps (2 channels)
100ksps (3 channels)
76ksps (4 channels)
Input Range: ±5V (MAX125)
±2.5V (MAX126)
Fault-Protected Input Multiplexer (±17V)±5V SuppliesInternal +2.5V or External Reference OperationProgrammable On-Board SequencerHigh-Speed Parallel DSP Interface
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
Ordering Information

19-1319; Rev 3; 7/08
Typical Operating Circuit appears at end of data sheet.
Pin Configuration appears at end of data sheet.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE INL
(LSB)
MAX125CCAX
0°C to +70°C 36 SSOP ±4
MAX125CEAX -40°C to +85°C 36 SSOP ±4
MAX126CCAX
0°C to +70°C 36 SSOP ±4
MAX126CEAX -40°C to +85°C 36 SSOP ±4
MAX125/MAX126
2x4-Channel, Simultaneous-Sampling
14-Bit DAS
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(AVDD= +5V ±5%, AVSS= -5V ±5%, DVDD= +5V ±5%, VREFIN= 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
AGND, 0.1µF capacitor from REFIN to AGND, fCLK= 16MHz, external clock, 50% duty cycle, TA= TMINto TMAX, unless otherwise
noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND...........................................................-0.3V to 6V
AVSSto AGND............................................................0.3V to -6V
DVDDto DGND...........................................................-0.3V to 6V
AGND to DGND.......................................................-0.3V to 0.3V
CH_ _ to AGND....................................................................±17V
REFIN, REFOUT to AGND..........................................-0.3V to 6V
Digital Inputs/Outputs to DGND..............-0.3V to (DVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
SSOP (derate 11.8mW/°C above +70°C)....................941mW
Operating Temperature Ranges
MAX125CCAX/MAX126CCAX............................0°C to +70°C
MAX125CEAX/MAX126CEAX..........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec)................................300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)

Resolution N All channels 14 Bits
Integral Nonlinearity INL (Note 2) ±2 ±4 LSB
No Missing Codes 13 Bits
TA = +25°C ±5 ±15 Bipolar Zero Error TA = TMIN to TMAX ±25 mV
Bipolar Zero-Error Match Between all channels 1.2 5 mV
Zero-Code Tempco ±5 ppm/°C
TA = +25°C ±5 ±10 Gain Error TA = TMIN to TMAX ±15 mV
Gain-Error Match Between all channels 1.2 5 mV
Gain-Error Tempco ±5 ppm/°C
DYNAMIC PERFORMANCE (fCLK = 16MHz, fIN = 10.06kHz (Notes 1, 3)

MAX125 72 75 Signal-to-Noise Plus Distortion SINAD
Single-channel mode,
channel 1A, 250ksps (Note MAX126 70 72 dB
Total Harmonic Distortion THD Single-channel mode, channel 1A,
250ksps (Notes 4, 5) -89 -80 dB
Spurious-Free Dynamic Range SFDR Single-channel mode, channel 1A,
250ksps (Note 4) 80 90 dB
Channel-to-Channel Isolation Single-channel mode, channel 1A,
250ksps (Note 6) 80 dB
x4-Channel, Simultaneous-Sampling4-Bit DASELECTRICAL CHARACTERISTICS (continued)
(AVDD= +5V ±5%, AVSS= -5V ±5%, DVDD= +5V ±5%, VREFIN= 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
AGND, 0.1µF capacitor from REFIN to AGND, fCLK= 16MHz, external clock, 50% duty cycle, TA= TMINto TMAX, unless otherwise
noted.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER

MAX125V±5VINInput Voltage Range
MAX125, VIN= ±5VµA±667IINInput Current
(Note 7)pF16CINInput Capacitance1tACQAcquisition Time
MHz8Small-Signal Bandwidth
MHz0.5Full-Power Bandwidth
mV/ms2Droop Rate5Aperture Delay
psRMS30Aperture Jitter500Aperture-Delay Matching= +25°CV2.4752.5002.525VREFOUTOutput Voltage
0mA < ILOAD< 1mA%±1External Load Regulation
(Note 9)ppm/°C30REFOUT Tempco0.1External Capacitive
Bypass at REFIN2.50 ±10%Input Voltage Range4.722External Capacitive
Bypass at REFOUT
REFIN = 2.5VµA±10Input Current
(Note 10)kΩ10Input Resistance
(Note 7)pF10Input Capacitance
MHz0.116External Clock Frequency2.4VIHInput High Voltage0.8VILInput Low Voltage
CONVST, RD, WR, CS, CLK±1
(Note 7)pF15CINInput Capacitance
A0–A3µA±10IINInput Current
MAX126±2.5
MAX126, VIN= ±2.5V
ANALOG INPUT
TRACK/HOLD
REFERENCE OUTPUT (Note 8)
REFERENCE INPUT
EXTERNAL CLOCK
DIGITAL INPUTS (CONVST, RD,
WR, CS, CLK, A0–A3) (Note 1)
x4-Channel, Simultaneous-Sampling4-Bit DASCONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER
IOUT= 1mAV4VOHOutput High Voltage
IOUT= -1.6mAV0.4VOLOutput Low Voltage
D0–D13µA±10Three-State Leakage Current
(Note 7)pF10Three-State Output
Capacitance4.7555.25AVDDPositive Supply Voltage-5.25-5-4.75AVSSNegative Supply Voltage4.7555.25DVDDDigital Supply Voltage1725I(AVDD)Positive Supply Current-17-13I(AVSS)Negative Supply Current35I(DVDD)Digital Supply Current3Shutdown Positive Current-1Shutdown Negative Current3Shutdown Digital Current
(Note 11)LSB±1±2PSRR+Positive Supply Rejection
(Note 11)LSB±2PSRR-Negative Supply Rejection
(Note 12)mW165250Power Dissipation
DIGITAL OUTPUTS
(D0–D13, INT) (Note 1)
POWER REQUIREMENTS
ELECTRICAL CHARACTERISTICS (continued)

(AVDD= +5V ±5%, AVSS= -5V ±5%, DVDD= +5V ±5%, VREFIN= 2.5V, AGND = DGND = 0V, 4.7µF capacitor from REFOUT to
AGND, 0.1µF capacitor from REFIN to AGND, fCLK= 16MHz, external clock, 50% duty cycle, TA= TMINto TMAX, unless otherwise
noted.)
x4-Channel, Simultaneous-Sampling4-Bit DASCONDITIONS30tCWCONVSTPulse Width
UNITSMINTYPMAXSYMBOLPARAMETER
TIMING CHARACTERISTICS (Figure 4)

(AVDD= +5V, AVSS= -5V, DVDD= +5V, AGND = DGND = 0V, TA= TMINto TMAX, unless otherwise noted.)0tCWSCSto WRSetup Time0tCWHCSto WRHold Time30tWRWRLow Pulse Width125tCSDCSto CONVSTDelay30tASAddress Setup Time0tAHAddress Hold Time
25pF loadns30tIDRDto INTDelay40tRDDelay Time Between Reads0tCRSCSto RDSetup Time0tCRHCSto RDHold Time30tRDRDLow Pulse Width
25pF load (Note 13)ns30tDAData-Access Time
25pF load (Note 14)ns545tDHBus-Relinquish Time
Mode 1, 1 channel
Mode 2, 2 channel6
Mode 3, 3 channel9
Mode 4, 4 channel12
tCONV
Exiting shutdownµs5Start-Up Time
Note 1:
AVDD= +5V, AVSS= -5V, DVDD= +5V, VREFIN= 2.500V (external), VIN= ±5V (MAX125) or ±2.5V (MAX126).
Note 2:
Relative accuracy is the analog value’s deviation at any code from its theoretical value after the full-scale range has been
calibrated.
Note 3:
CLK synchronized with CONVST.
Note 4:
fIN= 10.06kHz, VIN= ±5V (MAX125) or ±2.5V (MAX126).
Note 5:
First five harmonics.
Note 6:
All inputs except CH1A driven with ±5V (MAX125) or ±2.5V (MAX126) 10kHz signal; CH1A connected to AGND and digitized.
Note 7:
Guaranteed by design. Not production tested.
Note 8:
AVDD= +5V, AVSS= -5V, DVDD= +5V, VIN= 0V (all channels).
Note 9:
Temperature drift is defined as the change in output voltage from +25°C to TMINor TMAX. It is calculated as
TC = [ΔREFOUT/REFOUT] / ΔT.
Note 10:
See Figure 2.
Note 11:
Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input
at full scale and all others at AGND. VREFIN= 2.5V (internal).
Note 12:
Tested with VIN= AGND on all channels, VREFIN= 2.5V (internal).
Note 13:
The data-access time is defined as the time required for an output to cross 0.8V or 2.0V. It is measured using the circuit of
Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.
Note 14:
The bus-relinquish time is derived from the measured time taken for the data outputs to change 0.5V when loaded with the
circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging/discharging the 120pF
capacitor. Thus, the time given is the part’s true bus-relinquish time, independent of the external bus loading capacitance.
Conversion Time
Mode 1, 1 channel
ksps
Conversion Rate/ChannelMode 2, 2 channel142
Mode 3, 3 channel100
Mode 4, 4 channel76
_______________Detailed Description
The MAX125/MAX126 use a successive-approximation
conversion technique and four simultaneous-sampling
track/hold (T/H) amplifiers to convert analog signals into
14-bit digital outputs. Each T/H has two multiplexed
inputs, allowing a total of eight inputs. Each T/H output
is converted and stored in memory to be accessed
sequentially by the parallel interface with successive
read cycles. The MAX125/MAX126 internal micro-
sequencer can be programmed to digitize one, two,
three, or four inputs sampled simultaneously from either
of the two banks of four inputs (see Figure 2).
The conversion timing and control sequences are
derived from a 16MHz external clock, the CONVSTx4-Channel, Simultaneous-Sampling4-Bit DAS
NAMEFUNCTION

1, 2CH2B, CH2AChannel 2 Multiplexed Inputs, single-ended
3, 4CH1B, CH1AChannel 1 Multiplexed Inputs, single-ended
PIN
AVDD+5V ±5% Analog Supply VoltageREFINExternal Reference Input/Internal Reference Output. Bypass with a 0.1µF capacitor to AGND.DVDD+5V ±5% Digital Supply Voltage
9–16D13–D6Data Bits. D13 = MSB.
8, 36AGNDAnalog Ground. Both pins must be tied to ground.REFOUTReference-Buffer Output. Bypass with a 4.7µF capacitor to AGND.CSChip-Select Input (active-low)CLKClock Input (duty cycle must be 30% to 70%).
21–24D3/A3–D0/A0Bidirectional Data Bits/Address Bits. D0/A0 = LSB.
19, 20D5, D4Data BitsDGNDDigital Ground
______________________________________________________________Pin Description
WRWrite Input (active-low)RDRead Input (active-low)CONVSTConversion-Start Input. Rising edge initiates sampling and conversion sequence.INTInterrupt Output. Falling edge indicates the end of a conversion sequence.AVSS-5V ±5% Analog Supply Voltage
32, 33CH4A, CH4BChannel 4 Multiplexed Inputs, single-ended
34, 35CH3A, CH3BChannel 3 Multiplexed Inputs, single-ended
Figure 1.Load Circuit for Access Time and Bus Relinquish Time
TO OUTPUT
PIN
120pF
1.0mA
1.6mA
1.6V
x4-Channel, Simultaneous-Sampling4-Bit DASMUX
2.50V
BANDGAP REFERENCE
REFIN
10k
AGNDREFOUT
MUX
T/H
T/H
T/H
T/H
MUX
MUX
MUX
CH1A
CH1B
CH2A
CH2B
CH3A
CH3B
CH4A
CH4B
14-BIT
DAC
CONTROL LOGIC
BUS INTERFACE
CLKCONVSTINTCSRDWRDVDDDGND
SAR
14x4
RAM
VREF
THREE-STATE
OUTPUT
DRIVERS
AVDD
AGND
AVSS
D0/A0 (LSB)
D1/A1
D2/A2
D3/A3
D13 (MSB)
MAX125
MAX126
VREF
COMP
Figure 2.Functional Diagram
x4-Channel, Simultaneous-Sampling4-Bit DASsignal, and the programmed mode. The T/H amplifiers
hold the input voltages at the CONVSTrising edge.
Additional CONVSTpulses are ignored until the last
conversion for the sample is complete. The ADC con-
verts each assigned channel in 3µs and stores the
result in an internal 4x14-bit memory.
At the end of the last conversion, INTgoes low and the
T/H amplifiers begin to track the inputs again. The data
can be accessed by applying successive pulses to thepin. Successive reads access data words sequen-
tially. The memory is notrandom-access; data from
CH1 is always read first. After accessing all pro-
grammed channels, the address pointer selects CH1
again. Additional read pulses cycle through the data
words. CScan be held low during successive reads.
Input Bandwidth

The T/H’s input tracking circuitry has an 8MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Range and Input Protection

The MAX125’s input range is ±5V, and the MAX126’s
input range is ±2.5V. The input resistance for both parts
is 10kΩ. An input protection structure allows input volt-
ages to ±17V without harming the IC. This protection is
also active in shutdown mode.
Track/Holds

The MAX125/MAX126 feature four simultaneous T/Hs.
Each T/H has two multiplexed inputs. A T-switch input
configuration provides excellent hold-mode isolation.
Allow 1µs acquisition time for 14-bit accuracy.
The T/H aperture delay is typically 10ns. The 500ps
aperture-delay mismatch between the T/Hs allows the
relative phase information of up to four different inputs
to be preserved. Figure 3 shows the equivalent input
circuit, illustrating the ADC’s sampling architecture.
Only one of four T/H stages with its two multiplexed
inputs (CH_A and CH_B) is shown. All switches are in
track configuration for channel A. An internal buffer
charges the hold capacitor to minimize the required
acquisition time between conversions. The analog input
appears as a 10kΩresistor in parallel with a 16pF
capacitor.
CIN5k
CIN5k
S1AS2A
HOLDBUFFER
TRACK
CHOLD
7pF
HOLD
FROM MICROSEQUENCER
REFOUT
TRACK
MUX
DAC
SAR
S1BS2B
S3B
S3A
CH_A
CH_B
MAX125
MAX126
Figure 3.Equivalent Input Circuit
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