MAX1258BETM+ ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsApplicationsGPIOs• Controls for Optical Components• Lower Processor Requirements and Minimize Power ..
MAX1258BETM+ ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsApplicationsGPIOs• Controls for Optical Components• Lower Processor Requirements and Minimize Power ..
MAX1258BETM+T ,12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsEVALUATION KIT AVAILABLE12-Bit, Multichannel ADCs/DACsMAX1220/MAX1257/MAX1258with FIFO, Temperature ..
MAX1259CWE ,MAX1259 Battery ManagerGeneral Description
The MAX1259 battery manager provides backup-battery
switching for CMOS RAM, ..
MAX125CCAX ,2x4-Channel, Simultaneous-Sampling 14-Bit DASApplications __________Typical Operating CircuitPortable Data Logging Data Acquisition+3VMedical In ..
MAX125CCAX+D ,2x4-Channel, Simultaneous-Sampling, 14-Bit DASApplicationsMultiphase Motor ControlPower-Grid SynchronizationPower-Factor MonitoringTypical Operat ..
MAX368EJN ,Fault-Protected Analog Multiplexer with Latch19-0982; Rev 1; T/96
Analog Multiplexer with Latch,
MAX368EWN ,Fault-Protected Analog Multiplexer with LatchELECTRICAL CHARACTERISTICS
(V' - +15V, V - -leN, GND = o, WR = (j, RS = 2 4V Ljrnless Otherw1ser10 ..
MAX368MJN ,Fault-Protected Analog Multiplexer with LatchFeatures
. All Switches Off with Power Supplies Off
. Overvoltage Protection up to :35V
. On ..
MAX3690ECJ ,+3.3V / 622Mbps / SDH/SONET 8:1 Serializer with Clock Synthesis and TTL InputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (V - 2V), T = -40°C to +85°C ..
MAX3690ECJ ,+3.3V / 622Mbps / SDH/SONET 8:1 Serializer with Clock Synthesis and TTL InputsApplicationsOrdering Information622Mbps SDH/SONET Transmission SystemsPART TEMP. RANGE PIN-PACKAGE6 ..
MAX3690ECJ+ ,+3.3V, 622Mbps SDH/SONET 8:1 Serializer with Clock Synthesis and TTL InputsELECTRICAL CHARACTERISTICS(V = +3.0V to +3.6V, PECL loads = 50Ω ±1% to (V - 2V), T = -40°C to +85°C ..
MAX1220BETX+-MAX1257BETM+-MAX1258BETM+-MAX1258BETM+T
12-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO PortsEVALUATION KIT AVAILABLE
General DescriptionThe MAX1220/MAX1257/MAX1258 is a highly integrat-
ed system monitoring and control solution which
includes a 16-channel (MAX1257/MAX1258) or 8-ch
(MAX1220) 12-bit Analog to Digital Converter (ADC),
twelve 12-bit Digital to Analog Converters (DACs), an
internal reference, an internal temp sensor, a 4-bit
(MAX1220) or 12-bit (MAX1257/MAX1258) GPIO port,
and a 25MHz SPI-/QSPI™-/MICROWIRE®- compatible
serial interface.
The MAX1220 is available in a 36-pin TQFN package.
The MAX1257/MAX1258 are available in 48-pin TQFN
package. All devices are specified over the -40°C to
+85°C temperature range.
ApplicationsControls for Optical Components
Base-Station Control Loops
System Supervision and Control
Data-Acquisition Systems
Benefits and FeaturesReduce Parts Count and Board Space with Fully
Integrated System Monitor and Controller
Monitors 8 (MAX1220) or 16 Voltages
(MAX1257/MAX1258) Using 12-Bit, 225ksps ADC
Controls 8 Output Voltage Level with 12-Bit, Octal,
2µs Settling DAC with Ultra-Low Glitch Energy
(4n x VS)
Measures Temperature with Internal ±1°C
Accurate Temperature Sensor
Options for Using Either Internal 2.5V (MAX1257)
Reference, 4.096V (MAX1220/MAX1258)
Reference or External Reference
Includes 4 (MAX1220) or 12 (MAX1257/1258)
GPIOs
Lower Processor Requirements and Minimize Power
Consumption and Heat Dissipation
On-Chip FIFO, Channel-Scan Mode and Data
Averaging
Autoshutdown Between Conversions
Low-Power ADC
2.5mA at 225ksps
22µA at 1ksps
Low-Power DAC: 1.5mA
TQFN Package with Exposed Pad
Enable Maximum Dynamic Range with Availability of
2 Analog Power Supply Options: +2.7V to +3.6V
(MAX1257) or +4.75V to +5.25V
(MAX1220/MAX1258)
Note:All devices are specified over the -40°C to +85°C
operating range.
*EP = Exposed pad.
**Number of resolution bits refers to both DAC and ADC.
Pin Configurations appear at end of data sheet.QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Ordering Information/Selector Guide
PARTPIN-PACKAGE
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS**
ADC
CHANNELS
DAC
CHANNELSGPIOs
MAX1220BETX+ 36 Thin QFN-EP* 4.096 4.75 to 5.25 12 8 8 4
MAX1257BETM+ 48 Thin QFN-EP* 2.5 2.7 to 3.6 12 16 8 12
MAX1258BETM+ 48 Thin QFN-EP* 4.096 4.75 to 5.25 12 16 8 12
DOUT
EOC
AIN0
AIN13
REF2/
AIN14
CNVST/
AIN15
REF1
DIN
SCLK
GPIOA0–
GPIOA3
GPIOB0–
GPIOB3
GPIOC0–
GPIOC3
AVDD
SPI
PORT
AND
LOGIC
CNTRL
OUTPUT
CONDITIONING
12-BIT
DACUSER-PROGRAMMABLE
I/O
OSCILLATOR
OUT0
OUT1
OUT2
OUT4
OUT5
OUT6
MAX1257
MAX1258
12-BIT
SAR
ADC
TEMPERATURE
SENSOR
FIFO AND
ALU
LDACRES_SELAGND
T/H
REFERENCE
OUTPUT
CONDITIONING
12-BIT
DAC
OUT3
OUT7
DGND
DVDD
Functional Diagram
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Absolute Maximum Ratings
Electrical Characteristics
(VAVDD= VDVDD= 2.7V to 3.6V (MAX1257), external reference VREF= 2.5V (MAX1257), VAVDD= 4.75V to 5.25V, VDVDD= 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF= 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
DVDD to AVDD......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND........................-0.3V to (VDVDD + 0.3V)
Analog Inputs, Analog Outputs and REF_
to AGND.............................................-0.3V to (VAVDD + 0.3V)
Maximum Current into Any Pin (except AGND, DGND, AVDD,
DVDD, and OUT_)...........................................................50mA
Maximum Current into OUT_.............................................100mA
Continuous Power Dissipation (multilayer board, TA= +70°C)
36-Pin TQFN (6mm x 6mm)
(derate 35.7mW/°C above +70°C)......................2857.1mW
48-Pin TQFN (7mm x 7mm)
(derate 40mW/°C above +70°C)............................3200mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature ...................................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ADC
DC ACCURACY (Note 1)
Resolution12Bits
Integral NonlinearityINL±0.5±1.0LSB
Differential NonlinearityDNL±0.5±1.0LSB
Offset Error±1±4.0LSB
Gain Error(Note 2)±0.1±4.0LSB
Gain Temperature Coefficient±0.8ppm/°C
Channel-to-Channel Offset±0.1LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, VIN = 2.5VP-P (MAX1257), VIN = 4.096VP-P (MAX1220/MAX1258),
225ksps, fCLK = 3.6MHz)
Signal-to-Noise Plus DistortionSINAD70dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)THD-76dBc
Spurious-Free Dynamic RangeSFDR72dBc
Intermodulation DistortionIMDfIN1 = 9.9kHz, fIN2 = 10.2kHz76dBc
Full-Linear BandwidthSINAD > 70dB100kHz
Full-Power Bandwidth-3dB point1MHz
CONVERSION RATE (Note 3)
External reference0.8µs
Power-Up TimetPUInternal reference (Note 4)218onver si on
cl ock
cycl es
Note:If the package power dissipation is not exceeded, one output at a time may be shorted to AVDD, DVDD, AGND, or DGND
indefinitely.
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Electrical Characteristics (continued)
(VAVDD= VDVDD= 2.7V to 3.6V (MAX1257), external reference VREF= 2.5V (MAX1257), VAVDD= 4.75V to 5.25V, VDVDD= 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF= 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Acquisition Time tACQ (Note 5) 0.6 μs
Internally clocked 5.5 Conversion Time tCONVExternally clocked 3.6 μs
External Clock Frequency fCLK Externally clocked conversion (Note 5) 0.1 3.6 MHz
Duty Cycle 40 60 %
Aperture Delay 30 ns
Aperture Jitter < 50 ps
ANALOG INPUTS
Unipolar 0 VREFInput Voltage Range (Note 6) Bipolar -VREF/2 +VREF/2V
Input Leakage Current ±0.01 ±1 μA
Input Capacitance 24 pF
INTERNAL TEMPERATURE SENSOR
TA = +25°C ±0.7 Measurement Error (Notes 5, 7) TA = TMIN to TMAX ±1.0 ±3.0 °C
Temperature Resolution 1/8 °C/LSB
INTERNAL REFERENCE
MAX1257 2.482 2.50 2.518 REF1 Output Voltage (Note 8) MAX1220/MAX1258 4.066 4.096 4.126 V
REF1 Voltage Temperature
Coefficient TCREF ±30 ppm/°C
REF1 Output Impedance 6.5 k
VREF = 2.5V 0.39 REF1 Short-Circuit Current VREF = 4.096V 0.63 mA
EXTERNAL REFERENCE
REF1 Input Voltage Range VREF1 REF mode 11 (Note 4) 1 VAVDD
+ 0.05 V
REF mode 01 1 VAVDD
+ 0.05 REF2 Input Voltage Range
(Note 4) VREF2
REF mode 11 0 1
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Electrical Characteristics (continued)
(VAVDD= VDVDD= 2.7V to 3.6V (MAX1257), external reference VREF= 2.5V (MAX1257), VAVDD= 4.75V to 5.25V, VDVDD= 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF= 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
VREF = 2.5V (MAX1257), fSAMPLE = 25 80
VREF = 4.096V (MAX1220/MAX1258),
fSAMPLE = 225ksps 40 80 REF1 Input Current (Note 9) IREF1
Acquisition between conversions ±0.01 ±1
μA
VREF = 2.5V (MAX1257), fSAMPLE = 25 80
VREF = 4.096V (MAX1220/MAX1258),
fSAMPLE = 225ksps 40 80REF2 Input Current IREF2
Acquisition between conversions ±0.01 ±1
μA
DAC
DC ACCURACY (Note 10)
Resolution 12 Bits
Integral Nonlinearity INL ±0.5 ±4 LSB
Differential Nonlinearity DNL Guaranteed monotonic ±1.0 LSB
Offset Error VOS (Note 8) ±3 ±10 mV
Offset-Error Drift ±10 ppm of
FS/°C
Gain Error GE (Note 8) ±5 ±10 LSB
Gain Temperature Coefficient ±8 ppm of
FS/°C
DAC OUTPUT
No load 0.02 VAVDD -
0.02 Output-Voltage Range
10k load to either rail 0.1 VAVDD -
0.1
DC Output Impedance 0.5
Capacitive Load (Note 11) 1 nF
VAVDD = 2.7V, VREF = 2.5V (MAX1257),
gain error < 1% 2000
Resistive Load to AGND RL
VAVDD = 4.75V, VREF = 4.096V
(MAX1220/MAX1258), gain error < 2% 500
From power-down mode, VAVDD = 5V 25 Wake-Up Time (Note 12) From power-down mode, VAVDD = 2.7V 21 μs Output Termination Programmed in from power-down mode 1 k
100k Output Termination At wake-up or programmed in
power-down mode 100 k
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Electrical Characteristics (continued)
(VAVDD= VDVDD= 2.7V to 3.6V (MAX1257), external reference VREF= 2.5V (MAX1257), VAVDD= 4.75V to 5.25V, VDVDD= 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF= 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DYNAMIC PERFORMANCE (Notes 5, 13)
Output-Voltage Slew Rate SR Positive and negative 3 V/μs
Output-Voltage Settling Time tS To 1 LSB, 400 - C00 hex (Note 7) 2 5 μs
Digital Feedthrough Code 0, all digital inputs from 0 to
VDVDD 0.5 nV•s
Major Code Transition Glitch
Impulse Between codes 2047 and 2048 4 nV•s
From VREF 660 Output Noise (0.1Hz to 50MHz) Using internal reference 720 μVP-P
From VREF 260 Output Noise (0.1Hz to
500kHz) Using internal reference 320 μVP-P
DAC-to-DAC Transition
Crosstalk 0.5 nV•s
INTERNAL REFERENCE
MAX1257 2.482 2.5 2.518 REF1 Output Voltage (Note 8) MAX1220/MAX1258 4.066 4.096 4.126 V
REF1 Temperature Coefficient TCREF ±30 ppm/°C
VREF = 2.5V 0.39 REF1 Short-Circuit Current VREF = 4.096V 0.63 mA
EXTERNAL-REFERENCE INPUT
REF1 Input Voltage Range VREF1 REF modes 01, 10, and 11 (Note 4)0.7 VAVDD V
REF1 Input Impedance RREF1 70 100 130 k
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS,CNVST,LDAC)
Input-Voltage High VIH VDVDD = 2.7V to 5.25V 2.4 V
VDVDD = 3.6V to 5.25V 0.8 Input-Voltage Low VIL
VDVDD = 2.7V to 3.6V 0.6
Input Leakage Current IL ±0.01 ±10 μA
Input Capacitance CIN 15 pF
DIGITAL OUTPUT (DOUT) (Note 14)
Output-Voltage Low VOL ISINK = 2mA 0.4 V
Output-Voltage High VOH ISOURCE = 2mA VDVDD -
0.5 V
Three-State Leakage Current ±10 μA
Three-State Output
Capacitance COUT 15 pF
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Electrical Characteristics (continued)
(VAVDD= VDVDD= 2.7V to 3.6V (MAX1257), external reference VREF= 2.5V (MAX1257), VAVDD= 4.75V to 5.25V, VDVDD= 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF= 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL OUTPUT (EOC) (Note 14)
Output-Voltage Low VOL ISINK = 2mA 0.4 V
Output-Voltage High VOH ISOURCE = 2mA VDVDD -
0.5 V
Three-State Leakage Current ±10 μA
Three-State Output
Capacitance COUT 15 pF
DIGITAL OUTPUTS (GPIO_) (Note 14)
ISINK = 2mA 0.4 GPIOB_, GPIOC_ Output-
Voltage Low ISINK = 4mA 0.8 V
GPIOB_, GPIOC_ Output-
Voltage High ISOURCE = 2mA VDVDD -
0.5 V
GPIOA_ Output-Voltage Low ISINK = 15mA 0.8 V
GPIOA_ Output-Voltage High ISOURCE = 15mAVDVDD -
0.8 V
Three-State Leakage Current ±10 μA
Three-State Output
Capacitance COUT 15 pF
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage DVDD 2.7 VAVDD V
Idle, all blocks shut down 0.2 4 μA Digital Positive-Supply Current DIDDOnly ADC on, external reference 1 mA
MAX1257 2.7 3.6 Analog Positive-Supply Voltage AVDD
MAX1220/MAX1258 4.75 5.25
Idle, all blocks shut down 0.2 2 μA
fSAMPLE = 225ksps 2.8 4.2 Only ADC on,
external reference fSAMPLE = 100ksps 2.6 Analog Positive-Supply Current AIDD
All DACs on, no load, internal reference 1.5 4
mA
MAX1257, VAVDD = 2.7V -77 REF1 Positive-Supply
Rejection PSRR MAX1220/MAX1258, VAVDD = 4.75V -80 dB
MAX1257, VAVDD = 2.7V to ±0.1 ±0.5
DAC Positive-Supply Rejection PSRD
Output
code =
FFFhex
MAX1220/MAX1258,
VAVDD = 4.75V to 5.25V ±0.1 ±0.5 mV
MAX1257, VAVDD = 2.7V to ±0.06 ±0.5
ADC Positive-Supply Rejection PSRA
Full-
scale
input
MAX1220/MAX1258,
VAVDD = 4.75V to 5.25V ±0.06 ±0.5 mV
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Electrical Characteristics (continued)
(VAVDD= VDVDD= 2.7V to 3.6V (MAX1257), external reference VREF= 2.5V (MAX1257), VAVDD= 4.75V to 5.25V, VDVDD= 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF= 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period tCP 40 ns
SCLK Pulse-Width High tCH 40/60 duty cycle 16 ns
SCLK Pulse-Width Low tCL 60/40 duty cycle 16 ns
GPIO Output Rise/Fall After
CS Rise tGOD CLOAD = 20pF 100 ns
GPIO Input Setup Before CS
Fall tGSU 0 ns
LDAC Pulse Width tLDACPWL 20 ns
CLOAD = 20pF, SLOW = 0 1.8 12.0 SCLK Fall to DOUT Transition
(Note 16) tDOTCLOAD = 20pF, SLOW = 1 10 40 ns
CLOAD = 20pF, SLOW = 0 1.8 12.0 SCLK Rise to DOUT Transition
(Notes 16, 17) tDOTCLOAD = 20pF, SLOW = 1 10 40 ns
CS Fall to SCLK Fall Setup Time tCSS 10 ns
SCLK Fall to CS Rise Hold Time tCSH 0 2000 ns
DIN to SCLK Fall Setup Time tDS 10 ns
DIN to SCLK Fall Hold Time tDH 0 ns
CS Pulse-Width High tCSPWH 50 ns
CS Rise to DOUT Disable tDOD CLOAD = 20pF 25 ns
CS Fall to DOUT Enable tDOE CLOAD = 20pF 1.5 25.0 ns
EOC Fall to CS Fall tRDS 30 ns
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
(Note 18) 65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off 140
CKSEL = 01 (voltage conversion) 9
CKSEL = 10 (voltage conversion),
internal reference on (Note 18) 9
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
tDOV
CKSEL = 10 (voltage conversion),
internal reference initially off 80
μs
CKSEL = 00, CKSEL = 01 (temp sense) 40 ns CNVST Pulse Width tCSWCKSEL = 01 (voltage conversion) 1.4 μs
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Electrical Characteristics (continued)
(VAVDD= VDVDD= 2.7V to 3.6V (MAX1257), external reference VREF= 2.5V (MAX1257), VAVDD= 4.75V to 5.25V, VDVDD= 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF= 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), TA= +25°C.
Outputs are unloaded, unless otherwise noted.)
Note 1:Tested at VDVDD= VAVDD= +2.7V (MAX1257), VDVDD= +2.7V, VAVDD= +5.25V (MAX1220/MAX1258).
Note 2:Offset nulled.
Note 3:No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Note 4:See Table 5 for reference-mode details.
Note 5:Not production tested. Guaranteed by design.
Note 6:See the ADC/DAC Referencessection.
Note 7:Fast automated test, excludes self-heating effects.
Note 8:Specified over the -40°C to +85°C temperature range.
Note 9:REFSEL[1:0] = 00 and when DACs are not powered up.
Note 10:DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11:The DAC buffers are guaranteed by design to be stable with a 1nF load.
Note 12:Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13:All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Note 14:Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15:All digital inputs at either VDVDDor DGND. VDVDDshould not exceed VAVDD.
Note 16:See the Reset Registersection and Table 9 for details on programming the SLOW bit.
Note 17:Clock mode 11 only.
Note 18:First conversion after reference power-up is always timed as if the internal reference was initially off to ensure the internal
reference has settled. Subsequent conversions are timed as shown.
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Typical Operating Characteristics
(VAVDD= VDVDD= 3V (MAX1257), external VREF= 2.5V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), external VREF=
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor at REF, = +25°C, unless otherwise noted.)
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGEMAX1220 toc01
SUPPLY VOLTAGE (V)
ANALOG SHUTDOWN CURRENT (
MAX1220/MAX1258
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc02
SUPPLY VOLTAGE (V)
MAX1257
ANALOG SHUTDOWN CURRENT (
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
MAX1220 toc03
TEMPERATURE (°C)
ANALOG SHUTDOWN CURRENT (
MAX1220/MAX1258
MAX1257
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1220 toc04
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
MAX1220/MAX1258
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1220 toc05
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
MAX1257
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODEMAX1220 toc06
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
MAX1220/MAX1258
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODEMAX1220 toc07
DIFFERENTIAL NONLINEARITY (LSB)
MAX1257
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc08
OFFSET ERROR (LSB)
MAX1220/MAX1258
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLATGE
MAX1220 toc09
MAX1257
OFFSET ERROR (LSB)
2.73.33.03.6
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
ADC GAIN ERROR
vs. TEMPERATURE
MAX1220 toc13
TEMPERATURE (°C)
GAIN ERROR (LSB)
MAX1257
MAX1220/MAX1258
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATEMAX1220 toc14
SAMPLING RATE (ksps)
ADC EXTERNAL REFERENCE INPUT CURRENT (
MAX1220/MAX1258
MAX1257
ANALOG SUPPLY CURRENT
vs. SAMPLING RATEMAX1220 toc15
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT (mA)
MAX1220/MAX1258
MAX1257
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc16
SUPPLY CURRENT (mA)
MAX1220/MAX1258
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc17
MAX1257
SUPPLY CURRENT (mA)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1220 toc18
ANALOG SUPPLY CURRENT (mA)MAX1257
MAX1220/MAX1258
ADC OFFSET ERROR
vs. TEMPERATURE
MAX1220 toc10
TEMPERATURE (°C)
OFFSET ERROR (LSB)
MAX1257
MAX1220/MAX1258
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc11
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
MAX1220/MAX1258
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc12
SUPPLY VOLTAGE (V)
MAX1257
GAIN ERROR (LSB)
Typical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1257), external VREF= 2.5V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), external VREF=
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor at REF, = +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Typical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1257), external VREF= 2.5V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), external VREF=
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor at REF, = +25°C, unless otherwise noted.)
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1220 toc19
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
MAX1220/MAX1258
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1220 toc20
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
MAX1257
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODEMAX1220 toc21
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
MAX1220/MAX1258
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODEMAX1220 toc22
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
MAX1257
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc23
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
MAX1220/MAX1258
EXTERNAL REFERENCE = 4.096V
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc24
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
MAX1257
EXTERNAL REFERENCE = 2.5V
DAC FULL-SCALE ERROR
vs. TEMPERATURE
MAX1220 toc25
DAC FULL-SCALE ERROR (LSB)
MAX1220/MAX1258
EXTERNAL
REFERENCE = 4.096V
INTERNAL
REFERENCE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
MAX1220 toc26
DAC FULL-SCALE ERROR (LSB)
MAX1257
EXTERNAL
REFERENCE = 2.5V
INTERNAL
REFERENCE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGEMAX1220 toc27
DAC FULL-SCALE ERROR (LSB)312
MAX1220/MAX1258
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGEMAX1220 toc28
REFERENCE VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
MAX1257
DAC FULL-SCALE ERROR
vs. LOAD CURRENTMAX1220 toc29
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR (LSB)2015105
MAX1220/MAX1258
DAC FULL-SCALE ERROR
vs. LOAD CURRENTMAX1220 toc30
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR (LSB)
MAX1257
Typical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1257), external VREF= 2.5V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), external VREF=
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor at REF, = +25°C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1220 toc31
TEMPERATURE (°C)
INETRNAL REFERENCE VOLTAGE (V)
MAX1220/MAX1258
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1220 toc32
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
MAX1257
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1220 toc33
SUPPLY VOLTAGE (V)
ADC REFERENCE SUPPLY CURRENT (
MAX1220/MAX1258
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLATAGE
MAX1220 toc34
MAX1257
ADC REFERENCE SUPPLY CURRENT (
MAX1220 toc35
ADC REFERENCE SUPPLY CURRENT (
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATUREMAX1220/MAX1258
EXTERNAL REFERENCE = 4.096V
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
MAX1220 toc36
ADC REFERENCE SUPPLY CURRENT (
MAX1257, EXTERNAL REFERENCE = 2.5V
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
ADC FFT PLOTMAX1220 toc37
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fSAMPLE = 32.768kHz
fANALOG_N = 10.080kHz
fCLK = 5.24288MHz
SINAD = 71.27dBc
SNR = 71.45dBc
THD = 85.32dBc
SFDR = 87.25dBc
ADC IMD PLOTMAX1220 toc38
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fCLK = 5.24288MHz
fIN1 = 9.0kHz
fIN2 = 11.0kHz
AIN = -6dBFS
IMD = 82.99dBc
ADC CROSSTALK PLOTMAX1220 toc39
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fCLK = 5.24288MHz
fIN1 = 10.080kHz
fIN2 = 8.0801kHz
SNR = 72.00dBc
THD = 85.24dBc
ENOB = 11.65 BITS
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENTMAX1220 toc40
OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)300
DAC OUTPUT = MIDSCALE
MAX1220/MAX1258
SINKING
SOURCING
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENTMAX1220 toc41
OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)100-20-10
DAC OUTPUT = MIDSCALE
MAX1257
SINKING
SOURCING
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENTMAX1220 toc42
SOURCE CURRENT (mA)
GPIO OUTPUT VOLTAGE (V)604020
MAX1220/MAX1258
GPIOA0–A3 OUTPUTS
GPIOB0–B3,
C0–C3 OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENTMAX1220 toc43
GPIO OUTPUT VOLTAGE (V)604020
MAX1257
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SINK CURRENTMAX1220 toc44
GPIO OUTPUT VOLTAGE (mV)604020
MAX1220/MAX1258
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SINK CURRENTMAX1220 toc45
GPIO OUTPUT VOLTAGE (mV)50302010
MAX1257
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
Typical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1257), external VREF= 2.5V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), external VREF=
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor at REF, = +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
TEMPERATURE SENSOR ERROR
vs. TEMPERATUREMAX1220 toc46
TEMPERATURE (°C)
TEMPERATURE SENSOR ERROR (35-1510
DAC-TO-DAC CROSSTALK
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc47
100μs/div
VOUTA
1V/div
VOUTB
10mV/div
AC-COUPLED
MAX1257
DAC-TO-DAC CROSSTALK
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc48
100μs/div
VOUTA
2V/div
VOUTB
10mV/div
AC-COUPLED
MAX1220/MAX1258
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc49
1μs/div
VOUT_
1V/div
1V/div
MAX1257
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc50
1μs/div
VOUT_
2V/div
2V/div
MAX1220/MAX1258
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc51
1μs/div
VOUT_
1V/div
1V/div
MAX1257
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc52
VOUT_
2V/div
2V/div
MAX1220/MAX1258
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc53
VOUT_
10mV/div
AC-COUPLED
1V/div
MAX1257
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc54
VOUT_
20mV/div
AC-COUPLED
2V/div
MAX1220/MAX1258
Typical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1257), external VREF= 2.5V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), external VREF=
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor at REF, = +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
DAC DIGITAL FEEDTHROUGH RLOAD = 10kΩ,
CLOAD = 100pF, CS = HIGH, DIN = LOWMAX1220 toc55
200ns/div
VOUT_
100mV/div
AC-COUPLED
SCLK
1V/div
MAX1257
DAC DIGITAL FEEDTHROUGH RLOAD = 10kΩ,
CLOAD = 100pF, CS = HIGH, DIN = LOWMAX1220 toc56
200ns/div
VOUT_
100mV/div
AC-COUPLED
SCLK
2V/div
MAX1220/MAX1258
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc57
1μs/div
VOUT_
1V/div
MAX1257
VLDAC
1V/div
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc58
2μs/div
VOUT_
2V/div
MAX1220/MAX1258
VLDAC
2V/div
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc59
1μs/div
VOUT_
1V/div
MAX1257
VLDAC
1V/div
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc60
1μs/div
VOUT_
2V/div
MAX1220/MAX1258
VLDAC
2V/div
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc61
VDAC-OUT
10mV/div
AC-COUPLED
MAX1257
VREF2
1V/div
ADC REFERENCE SWITCHING
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pFMAX1220 toc62
VDAC-OUT
2mV/div
AC-COUPLEDMAX1220/MAX1258
VREF2
2V/div
ADC REFERENCE SWITCHING
Typical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1257), external VREF= 2.5V (MAX1257), VAVDD= VDVDD= 5V (MAX1220/MAX1258), external VREF=
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capacitor at REF, = +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Pin Description
PIN
MAX1220MAX1257
MAX1258
NAME FUNCTION 1, 2 — GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
3 4 EOCActive-Low End-of-Conversion Output. Data is valid after the falling edge EOC.
4 7 DVDD Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1μF
capacitor. 8 DGND Digital Ground. Connect DGND to AGND.
6 9 DOUT
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
7 10 SCLK
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%.) See Table 5 for details on programming the
clock mode.
8 11 DIN Serial-Data Input. DIN data is latched into the serial interface on the
falling edge of SCLK.
9–12, 16–19 12–15,
22–25 OUT0–OUT7 DAC Outputs
13 18 AVDD Positive Analog Power Input. Bypass AVDD to AGND with a 0.1μF
capacitor.
14 19 AGND Analog Ground
15, 23, 32, 33 — N.C. No Connection. Not internally connected.
20 26 LDAC
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
21 27 CSActive-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
22 28 RES_SEL
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100k resistor to AGND or set RES_SEL high to
wake up the DAC outputs with a 100k resistor to VREF. Set RES_SEL
high to power up the DAC input register to FFFh. Set RES_SEL low to
power up the DAC input register to 000h.
24, 25 — GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Pin Description (continued)
PIN
MAX1220MAX1257
MAX1258
NAME FUNCTION 26 35 REF1
Reference 1 Input. Reference voltage;leave unconnected to use the
internal reference (2.5V for the MAX1257 or 4.096V for the
MAX1220/MAX1258). REF1 is the positive reference in ADC external
differential reference mode. Bypass REF1 to AGND with a 0.1μF
capacitor in external reference mode only. See the ADC/DAC
References section.
27–31, 34 — AIN0–AIN5 Analog Inputs
35 — REF2/AIN6
Reference 2 Input/Analog Input 6. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
36 — CNVST/AIN7 Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details
on programming the setup register.
— 1 CNVST/AIN15 Active-Low Conversion-Start Input/Analog Input 15. See Table 5 for
details on programming the setup register. 2, 3, 5, 6 GPIOA0–GPIOA3 General-Purpose I/O A0–A3. GPIOA0–GPIOA3 can sink and source 15mA. 16, 17,
20, 21 GPIOB0–GPIOB3 General-Purpose I/O B0–B3. GPIOB0–GPIOB3 can sink 4mA and
source 2mA.
— 29–32 GPIOC0–GPIOC3 General-Purpose I/O C0–C3. GPIOC0–GPIOC3 can sink 4mA and
source 2mA. 33, 34, 36–47 AIN0–AIN13 Analog Inputs
— 48 REF2/AIN14
Reference 2 Input/Analog Input 14. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
— — EP Exposed Pad. Must be externally connected to AGND. Do not use as a
ground connect.
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Detailed DescriptionThe MAX1220/MAX1257/MAX1258 integrate a 12-bit,
multichannel, analog-to-digital converter (ADC), and a
12-bit, octal, digital-to-analog converter (DAC) in a sin-
gle IC. These devices also include a temperature sen-
sor and configurable GPIOs with a 25MHz
SPI-/QSPI-/MICROWIRE-compatible serial interface.
The ADC is available in 8 and 16 input-channel
versions. The octal DAC outputs settle within 2.0µs, and
the ADC has a 225ksps conversion rate.
All devices include an internal reference (2.5V or
4.096V) providing a well-regulated, low-noise reference
for both the ADC and DAC. Programmable reference
modes for the ADC and DAC allow the use of an inter-
nal reference, an external reference, or a combination
of both. Features such as an internal ±1°C accurate
temperature sensor, FIFO, scan modes, programmable
internal or external clock modes, data averaging, and
AutoShutdown allow users to minimize both power con-
sumption and processor requirements. The low glitch
energy (4nV•s) and low digital feedthrough (0.5nV•s) of
the integrated octal DACs make these devices ideal for
digital control of fast-response closed-loop systems.
These devices are guaranteed to operate with a supply
voltage from +2.7V to +3.6V (MAX1257) and from
+4.75V to +5.25V (MAX1220/MAX1258). These devices
consume 2.5mA at 225ksps throughput, only 22µA at
1ksps throughput, and under 0.2µA in the shutdown
mode. The MAX1257/MAX1258 feature 12 GPIOs while
the MAX1220 offers four GPIOs that can be configured
as inputs or outputs.
Figure 1 shows the MAX1257/MAX1258 functional dia-
gram. The MAX1220 only includes the GPIOA0,
GPIOA1 and GPIOC0, GPIOC1 block. The output-con-
ditioning circuitry takes the internal parallel data bus
and converts it to a serial data format at DOUT, with the
appropriate wake-up timing. The arithmetic logic unit
(ALU) performs the averaging function.
SPI-Compatible Serial InterfaceThe MAX1220/MAX1257/MAX1258 feature a serial inter-
face that is compatible with SPI and MICROWIRE
devices. For SPI, ensure the SPI bus master (typically a
microcontroller (µC)) runs in master mode so that it
generates the serial clock signal. Select the SCLK fre-
quency of 25MHz or less, and set the clock polarity
(CPOL) and phase (CPHA) in the µC control registers to
the same value. The MAX1220/MAX1257/MAX1258
operate with SCLK idling high or low, and thus operate
with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS
low to latch any input data at DIN on the falling edge of
SCLK. Output data at DOUT is updated on the falling
edge of SCLK in clock modes 00, 01, and 10. Output
data at DOUT is updated on the rising edge of SCLK in
clock mode 11. See Figures 6–11. Bipolar true-differen-
tial results and temperature-sensor results are available
in two’s complement format, while all other results are in
binary.
A high-to-low transition on CSinitiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CSlow between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interfacesection
and Tables 10, 20, and 21.
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
DOUT
EOC
ADDRESS
AIN0
AIN13
REF2/
AIN14
CNVST/AIN15
REF1
DIN
SCLK
GPIOA0–
GPIOA3
GPIOB0–
GPIOB3
GPIOC0–
GPIOC3
AVDD
SPI
PORT
GPIO
CONTROL
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
USER-PROGRAMMABLE
I/O
OSCILLATOROUT0
OUT1
OUT2
OUT4
OUT5
OUT6
MAX1257
MAX1258
12-BIT
SAR
ADC
LOGIC
CONTROL
TEMPERATURE
SENSOR
FIFO AND
ALU
LDACRES_SELAGND
T/H
REF2
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INPUT
REGISTER
INTERNAL
REFERENCE
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
12-BIT
DACBUFFER
OUT3
OUT7
DGND
DVDD
CNVST
Figure 1. MAX1257/MAX1258 Functional Diagram
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
Table 1. Command Byte (MSB First)
REGISTER
NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADDITIONAL
NO. OF
BYTES Conversion 1 CHSEL3 CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 TEMP 0
Setup 0 1 CKSEL1 CKSEL0 REFSEL1 REFSEL0 DIFFSEL1 DIFFSEL0 1
ADC 0 0 1 AVGON NAVG1 NAVG0 NSCAN1 NSCAN0 0
DAC Select 0 0 0 1 X X X X 2
Reset 0 0 0 0 1 RESET SLOW FBGON 0
GPIO Configure 0 0 0 0 0 0 1 1 1 or 2
GPIO Write 0 0 0 0 0 0 1 0 1 or 2
GPIO Read 0 0 0 0 0 0 0 1 1 or 2
No Operation 0 0 0 0 0 0 0 0 0
X = Don’t care.
Write to the GPIOs by issuing a command byte to the
appropriate register. Writing to the MAX1220 GPIOs
requires 1 additional byte following the command byte.
Writing to the MAX1257/MAX1258 requires 2 additional
bytes following the command byte. See Tables 12–19
for details on GPIO configuration, writes, and reads.
See the GPIO Commandsection. Command bytes writ-
ten to the GPIOs on devices without GPIOs are ignored.
Power-Up Default StateThe MAX1220/MAX1257/MAX1258 power up with all
blocks in shutdown (including the reference). All regis-
ters power up in state 00000000, except for the setup
register and the DAC input register. The setup register
powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high and powers up to 000h
when RES_SEL is low.
12-Bit ADCThe MAX1220/MAX1257/MAX1258 ADCs use a fully
differential successive-approximation register (SAR)
conversion technique and on-chip track-and-hold (T/H)
circuitry to convert temperature and voltage signals into
12-bit digital results. The analog inputs accept both sin-
gle-ended and differential input signals. Single-ended
signals are converted using a unipolar transfer function,
and differential signals are converted using a selec-
table bipolar or unipolar transfer function. See the ADC
Transfer Functionssection for more data.
ADC Clock ModesWhen addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVSTto request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOCgoes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOCgoes high when CSor CNVSTgo low.
EOCis always high in clock mode 11.
Single-Ended or Differential ConversionsThe MAX1220/MAX1257/MAX1258 use a fully differen-
tial ADC for all conversions. When a pair of inputs are
connected as a differential pair, each input is connect-
ed to the ADC. When configured in single-ended mode,
the positive input is the single-ended channel and the
negative input is referred to AGND. See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
AIN14/AIN15. AIN0–AIN7 are available on all devices.
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
Unipolar or Bipolar ConversionsAddress the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to VREF1.A nega-
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to ±VREF1 / 2. The digital
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
In single-ended mode, the MAX1220/MAX1257/
MAX1258 always operate in unipolar mode. The analog
inputs are internally referenced to AGND with a full-scale
input range from 0 to the selected reference voltage.
Analog Input (T/H)The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1220/MAX1257/MAX1258. In
track mode, a positive input capacitor is connected to
AIN0–AIN15 in single-ended mode and AIN0, AIN2,
and AIN4–AIN14 (only positive inputs) in differential
mode. A negative input capacitor is connected to
AGND in single-ended mode or AIN1, AIN3, and
AIN5–AIN15 (only negative inputs) in differential mode.
For external T/H timing, use clock mode 01. After the
T/H enters hold mode, the difference between the sam-
pled positive and negative input voltages is converted.
The input capacitance charging rate determines the
time required for the T/H to acquire an input signal. If
the input signal’s source impedance is high, the
required acquisition time lengthens.
Any source impedance below 300Ωdoes not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening tACQ (only in clock mode 01) or by placing
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
Input BandwidthThe ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band
of interest.
Analog Input ProtectionInternal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDD and AGND, allowing
the inputs to swing from (AGND - 0.3V) to (AVDD +
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
Internal FIFOThe MAX1220/MAX1257/MAX1258 contain a first-
in/first-out (FIFO) buffer that holds up to 16 ADC results
plus one temperature result. The internal FIFO allows
the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
AIN0–AIN15
(SINGLE-ENDED),
AIN0, AIN2,
AIN4–AIN14
(DIFFERENTIAL)
COMPARATOR
HOLDACQ
ACQ
HOLD
ACQ
HOLD
AVDD / 2
REF1
AGND
CIN+
CIN-
DAC
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5–AIN15
(DIFFERENTIAL)
Figure 2. Equivalent Input Circuit
MAX1220/MAX1257/MAX125812-Bit, Multichannel ADCs/DACs
with FIFO, Temperature Sensing,
and GPIO Ports
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measure-
ment is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the Temperature
Measurementssection for details on converting the dig-
ital code to a temperature.
12-Bit DACIn addition to the 12-bit ADC, the MAX1220/
MAX1257/MAX1258 also include eight voltage-output,
12-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential nonlin-
earity error. Each DAC has a 2µs settling time and ultra-
low glitch energy (4nV•s). The 12-bit DAC code is
unipolar binary with 1 LSB = VREF/4096.
DAC Digital InterfaceFigure 1 shows the functional diagram of the MAX1257/
MAX1258. The shift register converts a serial 16-bit word
to parallel data for each input register operating with a
clock rate up to 25MHz. The SPI-compatible digital inter-
face to the shift register consists of CS, SCLK, DIN, and
DOUT. Serial data at DIN is loaded on the falling edge
of SCLK. Pull CSlow to begin a write sequence. Begin a
write to the DAC by writing 0001XXXX as a command
byte. The last 4 bits of the DAC select register are don’t-
care bits. See Table 10. Write another 2 bytes to the
DAC interface register following the command byte to
select the appropriate DAC and the data to be written to
it. See Tables 20 and 21.
The eight double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The eight 12-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAClow or by writing the
appropriate DAC command sequence at DIN. See
Table 20. The outputs of the DACs are buffered through
eight rail-to-rail op amps.
The MAX1220/MAX1257/MAX1258 DAC output voltage
range is based on the internal reference or an external
reference. Write to the setup register (see Table 5) to
program the reference. If using an external voltage ref-
erence, bypass REF1 with a 0.1µF capacitor to AGND.
The MAX1257 internal reference is 2.5V. The
MAX1220/MAX1258 internal reference is 4.096V. When
using an external reference on any of these devices,
the voltage range is 0.7V to VAVDD.
DAC Transfer FunctionSee Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up ModesThe state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AVDD
or AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩinternal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AVDD to wake up all DAC outputs
at FFFh. While RES_SEL is high, the 100kΩpullup
resistor pulls the DAC outputs to VREF1and the output
buffers are powered down.
DAC Power-Up ModesSee Table 21 for a description of the DAC power-up
and power-down modes.
GPIOsIn addition to the internal ADC and DAC, the
MAX1257/MAX1258 also provide 12 general-purpose
input/output channels, GPIOA0–GPIOA3, GPIOB0–
DAC CONTENTS
MSBLSBANALOG OUTPUT0000000000000⎛⎜⎞⎟VREF4095
4096⎛⎜⎞⎟=+⎛⎜⎞⎟VVREFREF2048
40962⎛⎜⎞⎟VREF2047
4096⎛⎜⎞⎟VREF1
4096⎛⎜⎞⎟VREF2049
Table 2. DAC Output Code Table
