MAX1247ACEE+ ,+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16ELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f ..
MAX1247ACPE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16FeaturesThe MAX1246/MAX1247 12-bit data-acquisition systems' 4-Channel Single-Ended or 2-Channel co ..
MAX1247ACPE+ ,+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16FeaturesThe MAX1246/MAX1247 12-bit data-acquisition systems♦ 4-Channel Single-Ended or 2-Channel co ..
MAX1247AEEE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16Applications+3VPortable Data Logging Data AcquisitionVCH0 V DDDD 0.1μFMedical Instruments Battery- ..
MAX1247BCEE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16ELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f ..
MAX1247BCEE+ ,+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16MAX1246/MAX124719-1071; Rev 2; 10/01+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16
MAX3669EHJ ,+3.3V / 622Mbps SDH/SONET Laser Driver with Current Monitors and APCELECTRICAL CHARACTERISTICS(V = +3.14V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3669EHJ ,+3.3V / 622Mbps SDH/SONET Laser Driver with Current Monitors and APCApplicationsNote A: Dice are designed to operate over a -40°C to +140°C622Mbps SDH/SONET Access Nod ..
MAX3669EHJ+ ,+3.3V, 622Mbps SDH/SONET Laser Driver with Current Monitors and APCFeaturesThe MAX3669 is a complete, +3.3V laser driver with auto-♦♦ +3.3V or +5.0V Single-Supply Ope ..
MAX3669EHJ+T ,+3.3V, 622Mbps SDH/SONET Laser Driver with Current Monitors and APCApplicationsMAX3669EHJ -40°C to +85°C 32 TQFP 622Mbps SDH/SONET Access NodesMAX3669EHJ+ -40°C to +8 ..
MAX3669ETG , 3.3V, 622Mbps SDH/SONET Laser Driver with Current Monitors and APC
MAX3669ETG , 3.3V, 622Mbps SDH/SONET Laser Driver with Current Monitors and APC
MAX1246ACPE+-MAX1246BCEE+-MAX1247ACEE+-MAX1247ACPE+-MAX1247BCEE+-MAX1247BCEE+T-MAX1247BCPE+-MAX1247BEEE+
+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16
General DescriptionThe MAX1246/MAX1247 12-bit data-acquisition systems
combine a 4-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. The MAX1246 oper-
ates from a single +2.7V to +3.6V supply; the MAX1247
operates from a single +2.7V to +5.25V supply. Both
devices’ analog inputs are software configurable for
unipolar/bipolar and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1246/
MAX1247 use either the internal clock or an external seri-
al-interface clock to perform successive-approximation
analog-to-digital conversions.
The MAX1246 has an internal 2.5V reference, while the
MAX1247 requires an external reference. Both parts have
a reference-buffer amplifier with a ±1.5% voltage-
adjustment range. These devices provide a hard-wired
SHDNpin and a software-selectable power-down, and
can be programmed to automatically shut down at the
end of a conversion. Accessing the serial interface auto-
matically powers up the MAX1246/MAX1247, and the
quick turn-on time allows them to be shut down between
all conversions. This technique can cut supply current to
under 60µA at reduced sampling rates. The MAX1246/
MAX1247 are available in a 16-pin DIP and a small QSOP
that occupies the same board area as an 8-pin SO.
For 8-channel versions of these devices, see the
MAX146/MAX147 data sheet.
________________________ApplicationsPortable Data Logging
Medical Instruments
Pen Digitizers
Data Acquisition
Battery-Powered Instruments
Process Control
Features4-Channel Single-Ended or 2-Channel
Differential InputsSingle-Supply Operation:
+2.7V to +3.6V (MAX1246)
+2.7V to +5.25V (MAX1247)Internal 2.5V Reference (MAX1246)Low Power:1.2mA (133ksps, 3V supply)
54µA (1ksps, 3V supply)
1µA (power-down mode)SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs16-Pin QSOP Package (same area as 8-pin SO)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16VDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSSSHDN
SSTRB
DOUT
DIN
SCLK
COM
AGND
DGND
VDD
CH3
4.7μF
0.1μF
CH0
0V TO
+2.5V
ANALOG
INPUTSMAX1246
CPU
+3V
VREF
0.047μF
REFADJ
__________Typical Operating Circuit19-1071; Rev 2; 10/01
PART
MAX1246ACPEMAX1246BCPE
MAX1246ACEE0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP RANGEPIN-PACKAGE16 Plastic DIP
16 Plastic DIP
16 QSOP
EVALUATION KIT AVAILABLE
Ordering Information
Ordering Information continued at end of data sheet.MAX1246BCEE0°C to +70°C16 QSOP
INL
(LSB)±1/2
±1/2
SPI and QSPI are registered trademarks of Motorola, Inc.
MICROWIREis a registered trademark of National
Semiconductor Corp.
Pin Configuration appears at end of data sheet.
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.5V applied
to VREF pin; TA= TMINto TMAX;unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND.................................................-0.3V to 6V
AGND to DGND......................................................-0.3V to 0.3V
CH0–CH3, COM to AGND, DGND............-0.3V to (VDD+ 0.3V)
VREF to AGND...........................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND..............................................-0.3V to 6V
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C).........842mW
QSOP (derate 8.36mW/°C above +70°C)...................667mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
MAX1246_C_E/MAX1247_C_E..........................0°C to +70°C
MAX1246_E_E/MAX1247_E_E........................-40°C to +85°C
MAX1246_MJE/MAX1247_MJE....................-55°C to +125°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)Resolution12Bits
MAX124_A±0.5
MAX124_B±1.0Relative Accuracy (Note 2)INL
MAX1247C±2.0
LSB
No Missing CodesNMC12Bits
MAX124_A/MAX124_B±1Differential NonlinearityDNLMAX124_C±0.8LSB
MAX124_A±0.5±3Offset ErrorMAX124_B±0.5±4LSB
Gain Error (Note 3)±0.5±4LSB
Gain Temperature Coefficient±0.25ppm/°C
Channel-to-Channel Offset
Matching±0.25LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)MAX124_A/MAX124_B7073Signal-to-Noise + Distortion
RatioSINADMAX1247C73dB
MAX124_A/MAX124_B-88-80Total Harmonic DistortionTHDUp to the 5th
harmonicMAX1247C-88dB
MAX124_A/MAX124_B8090Spurious-Free Dynamic RangeSFDRMAX1247C90dB
Channel-to-Channel Crosstalk65kHz, 2.500VP-P (Note 4)-85dB
Small-Signal Bandwidth-3dB rolloff2.25MHz
Full-Power Bandwidth1.0MHz
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.5V applied
to VREF pin; TA= TMINto TMAX;unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CONVERSION RATEInternal clock, SHDN = FLOAT5.57.5
Internal clock, SHDN = VDD3565Conversion Time (Note 5)tCONVExternal clock = 2MHz, 12 clocks/
conversion6
Track/Hold Acquisition TimetACQ1.5µs
Aperture Delay30ns
Aperture Jitter<50ps
SHDN = FLOAT1.8Internal Clock FrequencySHDN = VDD0.225MHz
0.12.0External Clock FrequencyData transfer only02.0MHz
ANALOG/COM INPUTSUnipolar, COM = 0V0 to VREFInput Voltage Range, Single-
Ended and Differential (Note 6)Bi p ol ar , C OM = V RE F / 2±VREF / 2V
Multiplexer Leakage CurrentOn/off leakage current, VCH_ = 0V or VDD±0.01±1µA
Input Capacitance16pF
INTERNAL REFERENCE (MAX1246 only, reference buffer enabled)VREF Output VoltageTA = +25°C2.4802.5002.520V
VREF Short-Circuit Current30mA
MAX1246_C±30±50
MAX1246_E±30±60VREF Temperature Coefficient
MAX1246_M±30±80
ppm/°C
Load Regulation (Note 8)0mA to 0.2mA output load±0.35mV
Internal compensation mode0Capacitive Bypass at VREFExternal compensation mode4.7µF
Capacitive Bypass at REFADJ0.047µF
REFADJ Adjustment RangeVBST = VLX = VIN = 28V, VFB = 1.5V±1.5%
EXTERNAL REFERENCE AT VREF (Buffer disabled)VREF Input Voltage Range
(Note 9)1.0VDD +
50mVV
VREF Input CurrentVREF = 2.5V100150V
VREF Input Resistance1825kΩ
Shutdown VREF Input Current0.01100µA
REFADJ Buffer Disable
Threshold
VDD -
0.5V
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.5V applied
to VREF pin; TA= TMINto TMAX;unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EXTERNAL REFERENCE AT REFADJInternal compensation mode0Capacitive Bypass at VREFExternal compensation mode4.7µF
MAX12462.06Reference Buffer GainMAX12472.00V/V
MAX1246±50REFADJ Input CurrentMAX1247±10µA
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); COM = 0V; fSCLK= 2.0MHz; external clock (50% duty cycle);
15 clocks/conversion cycle (133ksps); MAX1246—4.7µF capacitor at VREF pin; MAX1247—external reference, VREF = 2.5V applied
to VREF pin; TA= TMINto TMAX;unless otherwise noted.)3.0VIH
VDD= 3.6V
DIN, SCLK, CSInput High VoltageVDD> 3.6V, MAX1247 only±0.3PSRSupply Rejection (Note 10)VDD= 2.7V to VDD(MAX), full-scale input,
external reference = 2.500V15CINDIN, SCLK, CSInput Capacitance±0.01±1IINDIN, SCLK, CSInput Leakage0.2VHYSTDIN, SCLK, CSInput Hysteresis0.8VILDIN, SCLK, CSInput Low Voltage
2.0±4.0ISSHDNInput Current0.4VSLSHDNInput Low VoltageVDD- 0.4VSHSHDNInput High Voltage
SHDN= 0VorVDD±100SHDNMaximum Allowed
Leakage, Mid InputVDD / 2VFLTSHDNVoltage, Floating
SHDN= FLOAT
SHDN= FLOAT
UNITSMINTYPMAXSYMBOLPARAMETER(Note 7)
VIN= 0V or VDD
VDD ≤3.6V
IDD
CONDITIONSPositive Supply Current, MAX1246µA
1.22.0±0.01±10ILThree-State Leakage CurrentVDD- 0.5VOHOutput Voltage High0.8VOLOutput Voltage Low0.4
2.703.6015COUTThree-State Output Capacitance
MAX1246= VDD(Note 7)= VDD
ISOURCE= 0.5mA
ISINK= 16mA
ISINK= 5mA2.705.25VDDPositive Supply VoltageMAX1247
Operating mode,
full-scale input70
VDD= 5.25V
VDD= 3.6V
3.515VDD= 5.25V
VDD= 3.6V1.210Full power-down1.82.570
Operating mode, full-scale input
Fast power-down
Full power-down1.1VDD- 1.1VSMSHDNInput Mid Voltage
Fast power-downIDD
Positive Supply Current, MAX1247
DIGITAL INPUTS(DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS(DOUT, SSTRB)
POWERREQUIREMENTS
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
__________________________________________Typical Operating Characteristics(VDD= 3V, VREF = 2.5V, fSCLK= 2MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. CODE
MAX1247-01
CODE
INL (LSB)
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
VDD (V)
INL (LSB)
MAX1247-02
MAX1246
MAX1247
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (°C)
INL (LSB)
MAX1247-03
MAX1247
MAX1246
VDD = 2.7V
TIMING CHARACTERISTICS(VDD= +2.7V to +3.6V (MAX1246); VDD= +2.7V to +5.25V (MAX1247); TA= TMINto TMAX; unless otherwise noted.)
Note 1:Tested at VDD= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:MAX1246—internal reference, offset nulled; MAX1247—external reference (VREF= +2.500V), offset nulled.
Note 4:Ground “on” channel; sine wave applied to all “off” channels.
Note 5:Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7:Guaranteed by design. Not subject to production testing.
Note 8:External load should not change during conversion for specified accuracy.
Note 9:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note10:Measured as |VFS(2.7V) - VFS(VDD.MAX)|.
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
Figure 1
Figure 2
Figure 1
MAX124_ _C/E
CONDITIONSMAX124_ _Mns20240Figure 1
tCSH240tSTRCSRise to SSTRBOutput Disable240tSDVCSFall to SSTRBOutput Enable
240tSSTRBSCLKFall to SSTRBns
200tCLSCLK Pulse Width Low200SCLK Pulse Width High0CSto SCLK Rise Hold100tCSSCSto SCLK Rise Setup240tTRCSRise to Output Disable240tDVCSFall to Output Enable
tCH200tDOSCLK Fall to Output Data Valid0tDHDIN to SCLK Hold1.5tACQAcquisition TimetSCKSSTRB Rise to SCLK Rise100tDS
UNITSMINTYPMAXSYMBOLPARAMETER
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
____________________________Typical Operating Characteristics (continued)(VDD= 3V, VREF = 2.5V, fSCLK= 2MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
MAX1247-04
RL = ∞
CODE = 101010100000CLOAD = 50pF
MAX1247
MAX1246
CLOAD = 20pF
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VDD (V)
SHUTDOWN SUPPLY CURRENT (
MAX1247-05
FULL POWER-DOWN
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
VDD (V)
VREF (V)
MAX1247-06
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1247-07
MAX1247
MAX1246
RLOAD = ∞
CODE = 10101010000010203040506070
FFT PLOTFREQUENCY (kHz)
AMPLITUDE (dB)
MAX1247-10VDD = 2.7V
fIN = 10k
fSAMPLE = 133k
SHUTDOWN CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
SHUTDOWN CURRENT (
MAX1247-08
MAX1246
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
VREF (V)
MAX1247-09
VDD = 2.7V
VDD = 3.6V
EFFECTIVE NUMBER OF BITS
vs. FREQUENCY
MAX1247-11
EFFECTIVE NUMBER OF BITS
VDD = 2.7V
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
____________________________Typical Operating Characteristics (continued)(VDD= 3V, VREF = 2.5V, fSCLK= 2MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
OFFSET vs. SUPPLY VOLTAGE
VDD (V)
OFFSET (LSB)
MAX1247-12
GAIN ERROR
vs. SUPPLY VOLTAGE
VDD (V)
GAIN ERROR (LSB)
MAX1247-13
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE
VDD (V)
GAIN MATCHING (LSB)
MAX1247-14
OFFSET vs. TEMPERATURE
TEMPERATURE (˚C)
OFFSET (LSB)-57014512095
MAX1247-15
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE
VDD (V)
OFFSET MATCHING (LSB)
MAX1247-18
GAIN ERROR
vs. TEMPERATURE
TEMPERATURE (˚C)
GAIN ERROR (LSB)451201459570
MAX1247-16
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
TEMPERATURE (˚C)
GAIN MATCHING (LSB)451451209570
MAX1247-17
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
TEMPERATURE (˚C)
OFFSET MATCHING (LSB)-57014512095
MAX1247-19
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
NAMEFUNCTIONVDDPositive Supply Voltage
2–5CH0–CH3Sampling Analog Inputs
PINCOMGround reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.SHDN
Three-Level Shutdown Input. Pulling SHDNlow shuts the MAX1246/MAX1247 down; otherwise, they
are fully operational. Pulling SHDNhigh puts the reference-buffer amplifier in internal compensation
mode. Letting SHDNfloat puts the reference-buffer amplifier in external compensation mode.DOUTSerial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CSis high.DGNDDigital GroundAGNDAnalog GroundVREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX1246 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.SCLKSerial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)CSActive-Low Chip Select. Data will not be clocked into DIN unless CSis low. When CSis high, DOUT is
high impedance.DINSerial Data Input. Data is clocked in at SCLK’s rising edge.SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1246/MAX1247 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CSis high (external clock
mode).
______________________________________________________________Pin DescriptionVDD
6kΩ
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6kΩ
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOL
VDD
6kΩ
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6kΩ
DOUT
a) VOH to High-Zb) VOL to High-Z
Figure 1.Load Circuits for Enable TimeFigure 2.Load Circuits for Disable TimeREFADJInput to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
_______________Detailed DescriptionThe MAX1246/MAX1247 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX1246/
MAX1247.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH3, and IN-is switched to COM. In
differential mode, IN+ and IN-are selected from two
pairs: CH0/CH1 and CH2/CH3. Configure the channels
with Tables 2 and 3. Please note that the codes for
CH0–CH3 in the MAX1246/MAX1247 correspond to the
codes for CH2–CH5 in the eight-channel (MAX146/
MAX147) versions.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at IN+
is sampled. The return side (IN-) must remain stable within
±0.5LSB (±0.1LSB for best results) with respect to AGND
during a conversion. To accomplish this, connect a 0.1µF
capacitor from IN-(the selected analog input) to AGND.
During the acquisition interval, the channel selected
as the positive input (IN+) charges capacitor CHOLD.
The acquisition interval spans three SCLK cycles and
ends on the falling SCLK edge after the last bit of the
input control word has been entered. At the end of the
acquisition interval, the T/H switch opens, retaining
charge on CHOLDas a sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLDfrom the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN-is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0V
within the limits of 12-bit resolution. This action is equiv-
alent to transferring a 16pF x [(VIN+) -(VIN-)] charge
from CHOLDto the binary-weighted capacitive DAC,
which in turn forms a digital representation of the analog
input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN-is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN-connects to the “-” input, and the
difference of |IN+ -IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
INPUT
SHIFT
REGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+1.21V
REFERENCE
(MAX1246)
T/HANALOG
INPUT
MUX
12-BIT
SAR
ADC
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
COM
REFADJ
VREF
OUT
REF
CLOCK
+2.500V
20kΩ
*A ≈ 2.00 (MAX1247)
CH35
CH24
CH13
CH02
MAX1246
MAX1247
SHDN
≈ 2.06*A
Figure 3.Block Diagram
CH0
CH1
CH2
CH3
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
9kΩ
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR+
16pF
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4.Equivalent Input Circuit
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
BITNAMEDESCRIPTION7(MSB)STARTThe first logic “1” bit after CSgoes low defines the beginning of the control byte.SEL2These three bits select which of the four channels are used for the conversion (Tables 2 and 3).
5 SEL1SEL0UNI/BIP1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.SGL/DIF1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).PD1Selects clock and power-down modes.
0(LSB)PD0PD1PD0Mode0Full power-down1Fast power-down0Internal clock mode1 External clock mode
Table 1.Control-Byte Formatallowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
tACQ= 9 x (RS+ RIN) x 16pF
where RIN= 9kΩ, RS= the source impedance of the
input signal, and tACQis never less than 1.5µs. Note
that source impedances below 1kΩdo not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog input
to VDDand AGND, allow the channel input pins to swing
from AGND -0.3V to VDD+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDDby more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 4mA.
How to Start a ConversionStart a conversion by clocking a control byte into DIN.
With CSlow, each rising edge on SCLK clocks a bit from
DIN into the MAX1246/MAX1247’s internal shift register.
After CSfalls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
The MAX1246/MAX1247 are compatible with SPI™/
QSPI™ and Microwire™ devices. For SPI, select the
correct clock polarity and sampling edge in the SPI
control registers: set CPOL = 0 and CPHA = 0. Micro-
wire, SPI, and QSPI all transmit a byte and receive a
byte at the same time.Using the Typical Operating
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(MSB)(LSB)STARTSEL2SEL1SEL0UNI/BIPSGL/DIFPD1PD0
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16Circuit,the simplest software interface requires only
three 8-bit transfers to perform a conversion (one 8-bit
transfer to configure the ADC, and two more 8-bit trans-
fers to clock out the 12-bit conversion result). See Figure
19 for MAX1246/MAX1247 QSPI connections.
Simple Software InterfaceMake sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.Use a general-purpose I/O line on the CPU to pull low.Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.Pull CShigh.
Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero and three trailing zeros. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Digital OutputIn unipolar input mode, the output is straight binary
(Figure 16). For bipolar inputs, the output is two’s com-
plement (Figure 17). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Clock ModesThe MAX1246/MAX1247 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX1246/MAX1247. The T/H acquires the input signal
as the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 6–9 show the timing characteristics
common to both modes.
External ClockIn external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 5). SSTRB and DOUT go into a high-impedance
state when CSgoes high; after the next CSfalling edge,
SSTRB outputs a logic low. Figure 7 shows the SSTRB
timing in external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial clock interruptions could cause the conversion
interval to exceed 120µs.
SEL2SEL1SEL0CH0CH1CH2CH3COM1+–
1+–
0+–
0+–
Table 2.Channel Selection in Single-Ended Mode (SGL/DDIIFF
= 1)
SEL2SEL1SEL0CH0CH1CH2CH31+–
0+–
1–+
0–+
Table 3.Channel Selection in Differential Mode (SGL/DDIIFF
= 0)
MAX1246/MAX1247
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
Internal Clock
In internal clock mode, the MAX1246/MAX1247 generate
their own conversion clocks internally. This frees the µP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN= FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 8). CSdoes
not need to be held low once a conversion is started.
Pulling CShigh prevents data from being clocked into
the MAX1246/MAX1247 and three-states DOUT, but it
does not adversely affect an internal clock mode
• • •
• • •
• • •
• • •
SCLK
DIN
DOUT
tCSHtCSStCL
tDS
tDH
tDV
tCH
tDOtTR
tCSH
Figure 6.Detailed Serial-Interface Timing
SSTRB
SCLK
DIN
DOUT812162024
START
SEL2SEL1SEL0UNI/
BIPSGL/
DIFPD1PD0
B11
MSBB10B9B8B7B6B5B4B3B2B1B0
LSB
ACQUISITION
(fSCLK = 2MHz)
IDLE
FILLED WITH ZEROS
IDLECONVERSION
tACQ
A/D STATE
RB1RB2RB3
1.5μs
Figure 5.24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with fSCLK ≤2MHz)
