MAX1245BCPP+ ,+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADCFeaturesThe MAX1245 12-bit data-acquisition system combines♦ Single +2.375V to +3.3V Operationan 8- ..
MAX1246ACPE+ ,+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16ELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V (MAX1246); V = +2.7V to +5.25V (MAX1247); COM = 0V; f ..
MAX1246BCEE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16General Description ________
MAX1246BCEE+ ,+2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16Applications__________Typical Operating CircuitPortable Data LoggingMedical Instruments+3VPen Digit ..
MAX1246BCPE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16Applications+3VPortable Data Logging Data AcquisitionVCH0 V DDDD 0.1μFMedical Instruments Battery- ..
MAX1247ACEE ,+2.7V / Low-Power / 4-Channel / Serial 12-Bit ADCs in QSOP-16FeaturesThe MAX1246/MAX1247 12-bit data-acquisition systems' 4-Channel Single-Ended or 2-Channel co ..
MAX3664EUA ,622Mbps, ultra-low-power, 3.3V transimpedance preamplifier for SDH/SONET.applications consumes only' 55nA Input-Referred NoiseRMS85mW. Operating from a single +3.3V supply, ..
MAX3667E/D ,+3.3V, 622Mbps SDH/SONET Laser Driver with Automatic Power ControlApplications622Mbps SDH/SONET Access NodesPin Configuration appears at end of data sheet.Laser Driv ..
MAX3667ECJ ,+3.3V / 622Mbps SDH/SONET Laser Driver with Automatic Power ControlApplications622Mbps SDH/SONET Access NodesPin Configuration appears at end of data sheet.Laser Driv ..
MAX3668EHJ+ ,+3.3V, 622Mbps SDH/SONET Laser Driver with Automatic Power ControlELECTRICAL CHARACTERISTICS(V = +3.14V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical ..
MAX3668EHJ+T ,+3.3V, 622Mbps SDH/SONET Laser Driver with Automatic Power Controlapplications up to 622Mbps. It accepts differentialPECL inputs, provides bias and modulation curren ..
MAX3668EHJ+T ,+3.3V, 622Mbps SDH/SONET Laser Driver with Automatic Power ControlApplicationsMAX3668EHJ+ -40°C to +85°C 32 TQFP (5mm x 5mm)622Mbps SDH/SONET Access NodesMAX3668E/D ..
MAX1245BCPP+
+2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC
________________General DescriptionThe MAX1245 12-bit data-acquisition system combines
an 8-channel multiplexer, high-bandwidth track/hold, and
serial interface with high conversion speed and ultra-low
power consumption. It operates from a single +2.375V to
+3.3V supply, and its analog inputs are software config-
urable for unipolar/bipolar and single-ended/differential
operation.
The 4-wire serial interface directly connects to SPI™,
QSPI™, and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1245
works with an external reference, and uses either the
internal clock or an external serial-interface clock to
perform successive-approximation analog-to-digital
conversions.
This device provides a hard-wired SHDNpin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface powers up
the MAX1245, and the quick turn-on time allows it to be
shut down between conversions. This technique can
cut supply current to under 10µA at reduced sampling
rates.
The MAX1245 is available in a 20-pin DIP package and
an SSOP that occupies 30% less area than an 8-pin DIP.
For supply voltages from +2.7V to +5.25V, use the pin-
compatible MAX147.
________________________ApplicationsPortable Data LoggingMedical Instruments
Battery-Powered InstrumentsData Acquisition
____________________________FeaturesSingle +2.375V to +3.3V Operation8-Channel Single-Ended or 4-Channel
Differential Analog InputsLow Power:0.8mA (100ksps)
10µA (1ksps)
1µA (power-down mode)Internal Track/Hold, 100kHz Sampling RateSPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin DIP/SSOP Packages
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADCTOP VIEW
DIP/SSOPVDD
SCLK
DIN
SSTRB
DOUT
DGND
AGND
VDD
VREFSHDN
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX1245
___________________Pin ConfigurationVDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSSSHDN
SSTRB
DOUT
DIN
SCLK
COM
AGND
DGND
VDD
CH7
0.1μF
0.1μF
CH00V to+2.048V
ANALOGINPUTS
MAX1245
CPU
+2.5V
VREF+2.048V
___________Typical Operating Circuit19-1066; Rev 1; 11/09
________________Ordering Information*Contact factory for availability of alternate surface-mount packages.
PART*TEMP RANGEPIN-PACKAGEINL
(LSB) MAX1245ACPP 0°C to +70°C 20 Plastic DIP ±1/2
MAX1245BCPP 0°C to +70°C 20 Plastic DIP ±1
MAX1245ACAP 0°C to +70°C 20 SSOP ±1/2
MAX1245BCAP 0°C to +70°C 20 SSOP ±1
MAX1245AEPP -40°C to +85°C 20 Plastic DIP ±1/2
MAX1245BEPP -40°C to +85°C 20 Plastic DIP ±1
MAX1245AEAP -40°C to +85°C 20 SSOP ±1/2
MAX1245BEAP -40°C to +85°C 20 SSOP ±1
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +2.375V to +3.3V, VCOM= 0V, fCLK= 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),
VREF = 2.048V applied to VREF pin, TA= TMINto TMAX,unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND..............................................-0.3V to +6V
AGND to DGND....................................................-0.3V to +0.3V
CH0–CH7, COM to AGND, DGND............-0.3V to (VDD+ 0.3V)
VREF to AGND...........................................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND............................................-0.3V to +6V
Digital Outputs to DGND...........................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C).........889mW
SSOP (derate 8.00mW/°C above +70°C)...................640mW
CERDIP (derate 11.11mW/°C above +70°C)..............889mW
Operating Temperature Ranges
MAX1245_C_P...................................................0°C to +70°C
MAX1245_E_P................................................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10sec)............................+300°C3565tCONVConversion Time (Note 5)
MHz1.0Full-Power Bandwidth
MHz2.25Small-Signal Bandwidth-85Channel-to-Channel Crosstalk76SFDRSpurious-Free Dynamic Range-76THDTotal Harmonic Distortion68SINADSignal-to-Noise + Distortion Ratio
LSB±0.2Channel-to-Channel Offset
Matching
ppm/°C±0.25Gain Temperature Coefficient
±0.5
Bits12Resolution
LSBGain Error (Note 3)±0.5±4
LSB±1.0INLRelative Accuracy (Note 2)
LSB±1DNL
LSB±0.5±4
UNITSMINTYPMAXSYMBOLPARAMETERExternal clock = 1.5MHz, 12 clocks/conversion
Internal clock, SHDN= VDD
Internal clock, SHDN= open
MAX1245A
-3dB rolloff
50kHz, 2Vp-p(Note 4)
Up to the 5th harmonic
MAX1245B
No missing codes over temperature
CONDITIONSDifferential Nonlinearity40Aperture Delay
MHz1.5SHDN= open<50Aperture Jitter
MHz0.11.52.0tACQTrack/Hold Acquisition TimeExternal clock = 1.5MHz
0.225Internal Clock FrequencySHDN= VDD1.5External Clock Frequency Data transfer only
DC ACCURACY(Note 1)
DYNAMICSPECIFICATIONS (10kHz sine-wave input, 0Vp-p to 2.048Vp-p, 100ksps, 1.5MHz external clock, bipolar input mode)
CONVERSION RATEOffset Error
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADCMultiplexer Leakage Current15CINDIN, SCLK, CSInput Capacitance±0.01±1IINDIN, SCLK, CSInput Leakage0.2VHYSTDIN, SCLK, CSInput Hysteresis0.8VINLDIN, SCLK, CSInput Low Voltage0.0110Shutdown VREF Input Current1825VREF Input Resistance82120VREF Input Current1.0VDD+
50mV
VREF Input Voltage Range
(Note 8)16Input Capacitance
0 to VREFV±VREF/2
Input Voltage Range, Single-
Ended and Differential (Note 6)±0.01±1
UNITSMINTYPMAXSYMBOLPARAMETER(Note 7)
VIN= 0V or VDD
Unipolar, VCOM= 0V
VREF = 2.048V
Bipolar, VCOM= VREF/2
On/off leakage current, VIN= 0V or VDD
(Note 7)
CONDITIONSVDD/2VDD/2
- 0.3+ 0.3VIMSHDNInput Mid Voltage±4.0IINSHDNInput Current0.4VINLSHDNInput Low VoltageVDD- 0.4VINHSHDNInput High Voltage
SHDN= 0VorVDD±80SHDNMaximum Allowed Leakage,
Mid InputVDD/2VFLTSHDNVoltage, Open
SHDN= open
SHDN= open
ELECTRICAL CHARACTERISTICS (continued)(VDD= +2.375V to +3.3V, VCOM= 0V, fCLK= 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),
VREF = 2.048V applied to VREF pin, TA= TMINto TMAX,unless otherwise noted.)±0.3PSRSupply Rejection (Note 9)0.81.3IDDPositive Supply Current±0.01±10ILThree-State Leakage CurrentVDD- 0.375VOHOutput Voltage High0.5VOLOutput Voltage Low0.42.3753.3VDDPositive Supply Voltage15COUTThree-State Output Capacitance
VDD= 2.375V to 3.3V, full-scale input,
external reference = 2.048V
Operating mode, full-scale input= VDD(Note 7)= VDD
ISOURCE=0.5mA
ISINK= 16mA
ISINK= 5mA
1.210Power-down2.0VINHDIN, SCLK, CSInput High Voltage
ANALOG/COM INPUTS
EXTERNALREFERENCE
DIGITAL INPUTS(DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS(DOUT, SSTRB)
POWERREQUIREMENTSMAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
TIMING CHARACTERISTICS(VDD= +2.375V to +3.3V, VCOM= 0V, TA= TMINto TMAX, unless otherwise noted.)
Note 1:Tested at VDD= +2.375V; VCOM= 0V; unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:External reference (VREF = +2.048V), offset nulled.
Note 4:Ground “on” channel; sine wave applied to all “off” channels.
Note 5:Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7:Guaranteed by design. Not subject to production testing.
Note 8:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9:Measured as |VFS(2.375V) - VFS(3.3V)|.
DIN to SCLK Setup400tSTRCSRise to SSTRBOutput Disable240tSDVCSFall to SSTRBOutput Enable
260tSSTRBSCLKFall to SSTRBns
300tCLSCLK Pulse Width Low300SCLK Pulse Width High0CSto SCLK Rise Hold200tCSSCSto SCLK Rise Setup400tTRCSRise to Output Disable240tDVCSFall to Output Enable
tDOSCLK Fall to Output Data Valid0tDHDIN to SCLK Hold2.0tACQAcquisition TimetSCKSSTRB Rise to SCLK Rise200tDS
UNITSMINTYPMAXSYMBOLInternal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
Figure 1
Figure 2
Figure 1
CONDITIONSFigure 1ns20260
tCSH
tCH
__________________________________________Typical Operating Characteristics(VDD= 2.5V, VREF = 2.048V, fCLK= 1.5MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VDD (V)
IDD
(mA)
RL = ∞
CODE = 101010100000
MAX1245-01
CLOAD = 50pF
CLOAD = 20pF
SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
IDD
(mA)145120-54595
MAX1245-02
RL = ∞
CODE = 101010100000
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
VDD (V)
INL (LSB)
MAX1245-03
PARAMETER
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADCINTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE (˚C)
INL (LSB)-57095145120
MAX1245-04VDD = 2.375V
OFFSET vs. SUPPLY VOLTAGE
VDD (V)
OFFSET (LSB)
MAX1245-05
OFFSET vs. TEMPERATURE
TEMPERATURE (˚C)
OFFSET (LSB)-57014512095
MAX1245-06
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE
VDD (V)
OFFSET MATCHING (LSB)
MAX1245-07
GAIN ERROR
vs. TEMPERATURE
GAIN ERROR (LSB)451201459570
MAX1245-10
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
TEMPERATURE (˚C)
OFFSET MATCHING (LSB)-57014512095
MAX1245-08
GAIN ERROR
vs. SUPPLY VOLTAGE
VDD (V)
GAIN ERROR (LSB)
MAX1245-09
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE
VDD (V)
GAIN MATCHING (LSB)
MAX1245-11
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
TEMPERATURE (˚C)
GAIN MATCHING (LSB)451451209570
MAX1245-12
____________________________Typical Operating Characteristics (continued)(VDD= 2.5V, VREF = 2.048V, fCLK= 1.5MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
____________________________Typical Operating Characteristics (continued)(VDD= 2.5V, VREF = 2.048V, fCLK= 1.5MHz, CLOAD= 20pF, TA = +25°C, unless otherwise noted.)
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
CONVERSIONS PER CHANNEL PER SECOND (Hz)11k10k100100k
MAX1245-13
VDD = VREF = 2.5V
CODE = 101010100000
RL = ∞
8 CHANNELS
1 CHANNEL
INTEGRAL NONLINEARITY
INL (BITS)
DIGITAL CODE
FFT PLOT
AMPLITUDE (dB)
FREQUENCY (kHz)
fTONE = 10ksps
fSAMPLE = 100ksps
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
MAX1245-14
INPUT FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
11.0
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
NAMEFUNCTION1–8CH0–CH7Sampling Analog InputsCOMGround reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
PINSHDN
Three-Level Shutdown Input. Pulling SHDNlow shuts the MAX1245 down to 10µA (max) supply current; oth-
erwise, the MAX1245 is fully operational. Letting SHDNbe open sets the internal clock frequency to 1.5MHz.
Pulling SHDNhigh sets the internal clock frequency to 225kHz. See Hardware Power-Downsection.VREFExternal Reference Voltage Input for analog-to-digital conversionDOUTSerial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CSis high.DGNDDigital GroundAGNDAnalog Ground
12, 20VDDPositive Supply VoltageSCLKSerial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)CSActive-Low Chip Select. Data will not be clocked into DIN unless CSis low. When CSis high, DOUT is
high impedance.DINSerial Data Input. Data is clocked in at the rising edge of SCLK.SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1245 begins the A/D con-
version and goes high when the conversion is done. In external clock mode, SSTRB pulses high for
one clock period before the MSB decision. High impedance when CSis high (external clock mode).
______________________________________________________________Pin DescriptionVDD
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOLVDD
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
DOUT
a) VOH to High-Zb) VOL to High-ZFigure 1.Load Circuits for Enable TimeFigure 2.Load Circuits for Disable Time
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________Detailed DescriptionThe MAX1245 analog-to-digital converter (ADC) uses a
successive-approximation conversion technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 12-bit digital output. A flexible serial interface
provides easy interface to microprocessors (µPs). No
external hold capacitors are required. Figure 3 is a
block diagram of the MAX1245.
Pseudo-Differential InputThe sampling architecture of the ADC’s analog compara-
tor is illustrated in the equivalent input circuit (Figure 4). In
single-ended mode, IN+ is internally switched to
CH0–CH7, and IN-is switched to COM. In differential
mode, IN+ and IN-are selected from the following pairs:
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels with Tables 2 and 3.
In differential mode, IN-and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN-(the selected
analog input) to AGND.
During the acquisition interval, the channel selected as the
positive input (IN+) charges capacitor CHOLD. The acqui-
sition interval spans three SCLK cycles and ends on the
falling SCLK edge after the last bit of the input control
word has been entered. At the end of the acquisition inter-
val, the T/H switch opens, retaining charge on CHOLDas a
sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLDfrom the positive input, IN+, to the
negative input, IN-(In single-ended mode, IN-is simply
COM). This unbalances node ZERO at the input of the
comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of 12-bit resolution. This action is
equivalent to transferring a charge of 16pF x [(VIN+) -
(VIN-)] from CHOLDto the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal.
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN-is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN-connects to the “-” input, and the
difference of |IN+ -IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLDcharges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
tACQ= 9 x (RS+ RIN) x 16pF
INPUTSHIFT
REGISTERCONTROLLOGIC
INTCLOCK
OUTPUTSHIFTREGISTER
T/HANALOGINPUTMUX12-BIT
SARADC
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
COM
VREF
OUT
REF
CLOCK
MAX1245
SHDN
12, 20
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
12k
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR+
16pF
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
MAX12450.1μF
2.048V
VDD
DGND
AGND
COM
SCLK
DIN
DOUT
SSTRB
SHDN
+2.5V
N.C.
0.01μF
CH7
VREF
0.1μF
0V TO
2.048V
ANALOG
INPUT
OSCILLOSCOPE
CH1CH2CH3CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
MAX1245
+2.5V
1.5MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
Figure 5.Quick-Look Circuit
where RIN= 12kΩ, RS= the source impedance of the
input signal, and tACQis never less than 2.0µs. Note
that source impedances below 1kΩdo not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
Input BandwidthThe ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog
input to VDDand AGND, allow the channel input pins to
swing from AGND -0.3V to VDD+ 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on channel.
Quick LookTo quickly evaluate the MAX1245’s analog perfor-
mance, use the circuit of Figure 5. The MAX1245
requires a control byte to be written to DIN before each
conversion. Tying DIN to VDDfeeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conver-
sions on CH7 in external clock mode without powering
down between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the 12-bit conversion result is
shifted out of DOUT. Varying the analog input to CH7
alters the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
How to Start a ConversionA conversion is started by clocking a control byte into
DIN. With CSlow, each rising edge on SCLK clocks a
bit from DIN into the MAX1245’s internal shift register.
After CSfalls, the first arriving logic “1” bit defines the
MSB of the control byte. Until this first “start” bit arrives,
any number of logic “0” bits can be clocked into DIN
with no effect. Table 1 shows the control-byte format.
The MAX1245 is compatible with MICROWIRE, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI
all transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit,the simplest soft-
ware interface requires only three 8-bit transfers to
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(MSB)(LSB)STARTSEL2SEL1SEL0UNI/BIPSGL/DIFPD1PD0
BITNAMEDESCRIPTION7(MSB)STARTThe first logic “1” bit after CSgoes low defines the beginning of the control byte.SEL2These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
5 SEL1SEL0UNI/BIP1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.SGL/DIF1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).PD1Selects clock and power-down modes.
0(LSB)PD0PD1PD0Mode0Power-down (IQ= 1.2µA)1Unassigned0Internal clock mode1 External clock mode
Table 1.Control-Byte Format
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH7COM0+–0+–1+–1+–0+–0+–1+–1+ –
Table 2.Channel Selection in Single-Ended Mode (SGL/DDIIFF
= 1)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH70+–1+–0+–1+–0–+1–+0–+1–+
Table 3.Channel Selection in Differential Mode (SGL/DDIIFF
= 0)
perform a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the 12-bit
conversion result). See Figure 17 for MAX1245 QSPI
connections.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 1.5MHz.Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.Use a general-purpose I/O line on the CPU to pull low.Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.Transmit a byte of all zeros ($00 HEX) and, simulta-
neously, receive byte RB2.Transmit a byte of all zeros ($00 HEX) and, simulta-
neously, receive byte RB3.Pull CShigh.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of idle time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar inputs, the output is two’s-com-
plement (Figure 15). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Clock Modes
The MAX1245 may use either an external serial clock or
the internal clock to perform the successive-approxima-
tion conversion. In both clock modes, the external clock
shifts data in and out of the MAX1245. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7–10 show the
timing characteristics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version. SSTRB pulses high for one clock period after
the control byte’s last bit. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CSgoes
high; after the next CSfalling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
SSTRB
SCLK
DIN
DOUT812162024
START
SEL2SEL1SEL0UNI/
BIP
SGL/
DIFPD1PD0
B11
MSBB10B9B8B7B6B5B4B3B2B1B0
LSB
ACQUISITION
(SCLK = 1.5MHz)
IDLE
FILLED WITH ZEROS
IDLECONVERSION
tACQ
A/D STATE
RB1RB2RB3
2.0μs
Figure 6.24-Clock External-Clock-Mode Conversion Timing (MICROWIRE and SPI Compatible, QSPI Compatible with fCLK ≤1.5MHz)
