MAX1209ETL+ ,12-Bit, 80Msps, 3.3V IF-Sampling ADCfeatures a 3µW power-down to ±1.15Vmode to conserve power during idle periods.♦ Common-Mode Referen ..
MAX120CAG ,500ksps, 12-Bit ADCs with Track/Hold And RefrenceELECTRICAL CHARACTERISTICS
(VDD = +4 75V to +5 25V, Vss = -10EV to -15.75V, (CLN = 8MHZ for MAX120 ..
MAX120CAG ,500ksps, 12-Bit ADCs with Track/Hold And RefrenceApplications
Digital-Signal Processing
Audio and Telecom Processing
Speech Recognition and S ..
MAX120CAG+ ,500ksps, Sampling, 12-Bit ADC with Track/Hold and Referenceapplications requiring a serial interface, MAX120CWG+ 0°C to +70°C 24 Wide SO ±1refer to the MAX121 ..
MAX120CAG+ ,500ksps, Sampling, 12-Bit ADC with Track/Hold and ReferenceApplicationsMAX120ENG+ -40°C to +85°C 24 PDIP ±1● Digital-Signal ProcessingMAX120EWG+ -40°C to +85° ..
MAX120CNG ,500ksps, 12-Bit ADCs with Track/Hold And RefrenceGeneral Description
The MAX12O and MAX122 complete, BCMOS, sampling
12-bit analog-to-digital co ..
MAX3510EEP+T ,Upstream CATV Amplifier
MAX3510EEP-T ,Upstream CATV Amplifier
MAX3510EEP-T ,Upstream CATV Amplifier
MAX3516EUP ,Upstream CATV Amplifiers
MAX3516EUP+ ,Upstream CATV Amplifiers
MAX351CPE ,Precision, Quad, SPST Analog Switches
MAX1209ETL+
12-Bit, 80Msps, 3.3V IF-Sampling ADC
General DescriptionThe MAX1209 is a 3.3V, 12-bit, 80Msps analog-to-digital
converter (ADC) featuring a fully differential wideband
track-and-hold (T/H) input amplifier, driving a low-noiseinternal quantizer. The analog input stage accepts sin-
gle-ended or differential signals. The MAX1209 is opti-mized for low power, small size, and high dynamic
performance. Excellent dynamic performance is main-
tained from baseband to input frequencies of 175MHzand beyond, making the MAX1209 ideal for intermediate-
frequency (IF) sampling applications.
Powered from a single 3.0V to 3.6V supply, the
MAX1209 consumes only 366mW while delivering atypical signal-to-noise (SNR) performance of 66.5dB at
an input frequency of 175MHz. In addition to low oper-ating power, the MAX1209 features a 3µW power-down
mode to conserve power during idle periods.
A flexible reference structure allows the MAX1209 to use
the internal 2.048V bandgap reference or accept anexternally applied reference. The reference structure
allows the full-scale analog input range to be adjusted
from ±0.35V to ±1.15V. The MAX1209 provides a com-mon-mode reference to simplify design and reduce exter-
nal component count in differential analog input circuits.
The MAX1209 supports both a single-ended and differ-
ential input clock drive. Wide variations in the clockduty cycle are compensated with the ADC’s internal
duty-cycle equalizer (DCE).
ADC conversion results are available through a 12-bit,
parallel, CMOS-compatible output bus. The digital out-put format is pin selectable to be either two’s comple-
ment or Gray code. A data-valid indicator eliminatesexternal components that are normally required for reli-
able digital interfacing. A separate digital power input
accepts a wide 1.7V to 3.6V supply, allowing theMAX1209 to interface with various logic levels.
The MAX1209 is available in a 6mm x 6mm x 0.8mm,
40-pin thin QFN package with exposed paddle (EP),
and is specified for the extended industrial (-40°C to+85°C) temperature range.
See the Pin-Compatible Versions tablefor a complete
family of 14-bit and 12-bit high-speed ADCs.
ApplicationsIF Communication Receivers
Cellular, Point-to-Point Microwave, HFC, WLAN
Ultrasound and Medical Imaging
Portable Instrumentation
Low-Power Data Acquisition
FeaturesDirect IF Sampling Up to 400MHzExcellent Dynamic Performance
68.0dB/66.5dB SNR at fIN= 70MHz/175MHz
85.1dBc/85.5dBc SFDR at fIN= 70MHz/175MHz3.3V Low-Power Operation
366mW (Single-Ended Clock Mode)
393mW (Differential Clock Mode)
3µW (Power-Down Mode)Differential or Single-Ended ClockFully Differential or Single-Ended Analog InputAdjustable Full-Scale Analog Input Range: ±0.35V
to ±1.15VCommon-Mode ReferenceCMOS-Compatible Outputs in Two’s Complement
or Gray CodeData-Valid Indicator Simplifies Digital DesignData Out-of-Range IndicatorMiniature, 40-Pin Thin QFN Package with Exposed
PaddleEvaluation Kit Available (Order MAX1211EVKIT)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
Ordering Information19-1001; Rev 0; 8/04
PARTTEMP
RANGEPIN-PACKAGEPKG
CODEMAX1209ETL-40°C to
+85°C
40 Thin QFN
(6mm x 6mm x 0.8mm) T4066-3
Pin-Compatible Versions
PARTSAMPLING
RATE (Msps)
RESOLUTION
(BITS)
TARGET
APPLICATIONMAX125536514IF/Baseband
MAX12098012IF
MAX12116512IF
MAX12088012Baseband
MAX12076512Baseband
MAX12064012Baseband
Pin Configuration appears at end of data sheet.
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND...........................................................-0.3V to +3.6V
OVDDto GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
INP, INN to GND...-0.3V to the lower of (VDD+ 0.3V) and +3.6V
REFIN, REFOUT, REFP, REFN, COM
to GND................-0.3V to the lower of (VDD+ 0.3V) and +3.6V
CLKP, CLKN, CLKTYP, G/T, DCE,
PD to GND........-0.3V to the lower of (VDD+ 0.3V) and +3.6V
D11 Through D0, I.C. DAV, DOR to GND...-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
40-Pin Thin QFN 6mm x 6mm x 0.8mm
(derated 26.3mW/°C above +70°C)........................2105.3mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering 10s)..................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 2)Resolution12Bits
Integral NonlinearityINLfIN = 3MHz±0.6LSB
Differential NonlinearityDNLfIN = 3MHz, no missing codes over
temperature-0.77±0.35LSB
Offset ErrorVREFIN = 2.048V±0.17±0.91%FS
Gain ErrorVREFIN = 2.048V±0.56±5.3%FS
ANALOG INPUT (INP, INN)Differential Input Voltage RangeVDIFFDifferential or single-ended inputs±1.024V
Common-Mode Input VoltageVDD / 2V
CPARFixed capacitance to ground2Input Capacitance
(Figure 3)CSAMPLESwitched capacitance1.9pF
CONVERSION RATEMaximum Clock FrequencyfCLK80MHz
Minimum Clock Frequency5MHz
Data LatencyFigure 68.5Clock
cycles
DYNAMIC CHARACTERISTICS (differential inputs, Note 2)
Small-Signal Noise FloorSSNFInput at less than -35dBFS-68.8dBFS
fIN = 70MHz at -0.5dBFS68.0
fIN = 100MHz at -0.5dBFS67.7Signal-to-Noise RatioSNR
fIN = 175MHz at -0.5dBFS (Note 6)64.566.5
fIN = 70MHz at -0.5dBFS67.8
fIN = 100MHz at -0.5dBFS67.6Signal-to-Noise and DistortionSINAD
fIN = 175MHz at -0.5dBFS (Note 6)64.366.4
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSfIN = 70MHz at -0.5dBFS85.1
fIN = 100MHz at -0.5dBFS86.2Spurious-Free Dynamic RangeSFDR
fIN = 175MHz at -0.5dBFS (Note 6)74.685.5
dBc
fIN = 70MHz at -0.5dBFS-81.2
fIN = 100MHz at -0.5dBFS-82.3Total Harmonic DistortionTHD
fIN = 175MHz at -0.5dBFS-82.7-73.9
dBc
fIN = 70MHz at -0.5dBFS-86.5
fIN = 100MHz at -0.5dBFS-89.6Second HarmonicHD2
fIN = 175MHz at -0.5dBFS-89
dBc
fIN = 70MHz at -0.5dBFS-85.1
fIN = 100MHz at -0.5dBFS-86.5Third HarmonicHD3
fIN = 175MHz at -0.5dBFS-88.6
dBc
fIN1 = 68.5MHz at -7dBFS,
fIN2 = 71.5MHz at -7dBFS-82.4
Intermodulation DistortionIMD
fIN1 = 172.5MHz at -7dBFS,
fIN2 = 177.5MHz at -7dBFS-74.2
dBc
fIN1 = 68.5MHz at -7dBFS,
fIN2 = 71.5MHz at -7dBFS-86.4
Third-Order IntermodulationIM3
fIN1 = 172.5MHz at -7dBFS,
fIN2 = 177.5MHz at -7dBFS-86.1
dBc
fIN1 = 68.5MHz at -7dBFS,
fIN2 = 71.5MHz at -7dBFS85.1
Two-Tone Spurious-Free
Dynamic RangeSFDRTT
fIN1 = 172.5MHz at -7dBFS,
fIN2 = 177.5MHz at -7dBFS74.2
dBc
Full-Power BandwidthFPBWInput at -0.5dBFS, -3dB roll-off700MHz
Aperture DelaytADFigure 40.9ns
Aperture JittertAJFigure 4<0.2psRMS
Output NoisenOUTINP = INN = COM0.52LSBRMS
Overdrive Recovery Time±10% beyond full scale1Clock
cycles
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally)REFOUT Output VoltageVREFOUT1.9842.0482.070V
COM Output VoltageVCOMVDD / 21.65V
Differential Reference Output
VoltageVREFVREF = VREFP - VREFN1.024V
REFOUT Load Regulation35mV/mA
REFOUT Temperature CoefficientTCREF+50ppm/°C
Short to VDD—sinking0.24REFOUT Short-Circuit CurrentShort to GND—sourcing2.1mA
BUF F ERED EXTERNAL REF ERENCE (REF IN d ri ven extern al ly; VR EF IN = 2.048V, VR EF P, VR EF N , an d VC OM are g en erated in tern ally)REFIN Input VoltageVREFIN2.048V
REFP Output VoltageVREFP(VDD / 2) + (VREFIN / 4)2.162V
REFN Output VoltageVREFN(VDD / 2) - (VREFIN / 4)1.138V
COM Output VoltageVCOMVDD / 21.601.651.70V
Differential Reference Output
VoltageVREFVREF = VREFP - VREFN0.9711.0241.069V
Differential Reference
Temperature Coefficient±25ppm/°C
REFIN Input Resistance>50MΩ
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; VREFP, VREFN, and VCOM are applied externally)COM Input VoltageVCOMVDD / 21.65V
REFP Input VoltageVREFP - VCOM0.512V
REFN Input VoltageVREFN - VCOM-0.512V
Differential Reference Input
VoltageVREFVREF = VREFP - VREFN1.024V
REFP Sink CurrentIREFPVREFP = 2.162V1.1mA
REFN Source CurrentIREFNVREFN = 1.138V1.1mA
COM Sink CurrentICOM0.3mA
REFP, REFN Capacitance13pF
COM Capacitance6pF
CLOCK INPUTS (CLKP, CLKN)Single-Ended Input High
ThresholdVIHCLKTYP = GND, CLKN = GND0.8 x
VDDV
Single-Ended Input Low
ThresholdVILCLKTYP = GND, CLKN = GND0.2 x
VDDV
Differential Input Voltage SwingCLKTYP = high1.4VP-P
Differential Input Common-Mode
VoltageCLKTYP = highVDD / 2V
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput ResistanceRCLKFigure 55kΩ
Input CapacitanceCCLK2pF
DIGITAL INPUTS (CLKTYP, G/T, PD)Input High ThresholdVIH0.8 x
OVDDV
Input Low ThresholdVIL0.2 x
OVDDV
VIH = OVDD±5Input Leakage CurrentVIL = 0±5µA
Input CapacitanceCDIN5pF
DIGITAL OUTPUTS (D11–D0, DAV, DOR)D11–D0, DOR, ISINK = 200µA0.2Output Voltage LowVOLDAV, ISINK = 600µA0.2V
D11–D0, DOR, ISOURCE = 200µAOVDD -
Output Voltage HighVOH
DAV, ISOURCE = 600µAOVDD -
Tri-State Leakage CurrentILEAK(Note 3)±5µA
D11–D0, DOR Tri-State Output
CapacitanceCOUT(Note 3)3pF
DAV Tri-State Output
CapacitanceCDAV(Note 3)6pF
POWER REQUIREMENTSAnalog Supply VoltageVDD3.03.33.6V
Digital Output Supply VoltageOVDD1.72.0VDD +
0.3VV
Normal operating mode,
fIN = 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
Normal operating mode,
fIN = 175MHz at -0.5dBFS,
CLKTYP = OVDD, differential clock
Analog Supply CurrentIVDD
Power-down mode clock idle, PD = OVDD0.001
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
Note 1:Specifications ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2:See definitions in the Parameter Definitions section.
Note 3:During power-down, D11–D0, DOR, and DAV are high impedance.
Note 4:Guaranteed by design and characterization.
Note 5:Digital outputs settle to VIHor VIL.
Note 6:Due to test equipment jitter limitations at 175MHz, 0.15% of the spectrum on each side of the fundamental is excluded from
the spectral analysis.
ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK = 80MHz (50% duty cycle), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSNormal operating mode,
fIN = 175MHz at -0.5dBFS, CLKTYP = GND,
single-ended clock
Normal operating mode,
fIN = 175MHz at -0.5dBFS,
CLKTYP = OVDD, differential clock
Analog Power DissipationPDISS
Power-down mode clock idle, PD = OVDD0.003
Normal operating mode,
fIN = 175MHz at -0.5dBFS, OVDD = 2.0V,
CL ≈ 5pF
9.2mADigital Output Supply CurrentIOVDD
Power-down mode clock idle, PD = OVDD0.9µA
TIMING CHARACTERISTICS (Figure 6)
Clock Pulse Width HightCH6.25ns
Clock Pulse Width LowtCL6.25ns
Data-Valid DelaytDAVCL = 5pF (Note 5)6.4ns
Data Setup Time Before Rising
Edge of DAVtSETUPCL = 5pF (Notes 4, 5)7.7ns
Data Hold Time After Rising Edge
of DAVtHOLDCL = 5pF (Notes 4, 5)4.2ns
Wake-Up Time from Power-DowntWAKEVREFIN = 2.048V10ms
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADCSINGLE-TONE FFT PLOT
(8192-POINT DATA RECORD)
MAX1209 toc01
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80.00352MHzSINAD = 67.872dB
fIN = 69.99331395MHzTHD = -82.119dBc
AIN = -0.506dBFSSFDR = 85.522dBc
SNR = 68.039dB
HD2HD3
HD4
SINGLE-TONE FFT PLOT
(4096-POINT DATA RECORD) MAX1209 toc02
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80.00352MHz SINAD = 66.010dB
fIN = 175.078125MHz THD = -82.976dBc
AIN = -0.500dBFS SFDR = 84.718dBc
SNR = 66.097dB481216202428323640
HD4HD2HD3
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD)
MAX1209 toc03
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80MHzAIN2 = -7.046dBFS
fIN1 = 68.50098MHzSFDRTT = 85.065dBc
AIN1 = -7.049dBFSIMD = -82.255dBc
fIN2 = 71.499MHzIM3 = -86.378dBc481216202428323640
fIN1
fIN2
2 x fIN1 + fIN2
fIN1 + 2 x fIN2
fIN2 + fIN1
TWO-TONE FFT PLOT
(16,384-POINT DATA RECORD) MAX1209 toc04
FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 80MHz AIN2 = -7.017dBFS
fIN1 = 172.4853516MHz SFDRTT = 74.205dBc
AIN1 = -6.976dBFS IMD = -74.108dBc
fIN2 = 177.4853516MHz IM3 = -85.923dBc481216202428323640
fIN1
fIN2
fIN2 - fIN1fIN2 + fIN1
INTEGRAL NONLINEARITY
MAX1209 toc05
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
MAX1209 toc06
DIGITAL OUTPUT CODE
DNL (LSB)
Typical Operating Characteristics(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
SNR, SINAD
vs. SAMPLING RATEMAX1209 toc07
fCLK (MHz)
SNR, SINAD (dB)602040100
fIN ≈ 70MHz
SNR
SINAD
SFDR, -THD
vs. SAMPLING RATEMAX1209 toc08
fCLK (MHz)
SFDR, -THD (dBc)602040
fIN ≈ 70MHz
SFDR
-THD
POWER DISSIPATION
vs. SAMPLING RATEMAX1209 toc09
fCLK (MHz)
POWEER DISSIPATION (mW)602040
DIFFERENTIAL CLOCK
fIN ≈ 70MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
SNR, SINAD vs. SAMPLING RATE
MAX1209 toc10
fCLK (MHz)
SNR, SINAD (dB)
SNR
SINAD
fIN ≈ 175MHz
SFDR, -THD vs. SAMPLING RATE
MAX1209 toc11
fCLK (MHz)
SFDR, -THD (dBc)
SFDR
-THD
fIN ≈ 175MHz
POWER DISSIPATION
vs. SAMPLING RATE
MAX1209 toc12
fCLK (MHz)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fIN ≈ 175MHz
CL ≈ 5pF50100150200
SNR, SINAD
vs. ANALOG INPUT FREQUENCYMAX1209 toc13
ANALOG INPUT FREQUENCY (MHz)
SNR, SINAD (dB)
SNR
SINAD
fCLK ≈ 80MHz50100150200
SFDR, -THD
vs. ANALOG INPUT FREQUENCYMAX1209 toc14
ANALOG INPUT FREQUENCY (MHz)
SFDR, -THD (dBc)
fCLK ≈ 80MHz
SFDR
-THD
POWER DISSIPATION
vs. ANALOG INPUT FREQUENCY
MAX1209 toc15
ANALOG INPUT FREQUENCY (MHz)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK ≈ 80MHz
CL ≈ 5pF
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADCSNR, SINAD
vs. ANALOG INPUT AMPLITUDE
MAX1209 toc16
ANALOG INPUT AMPLITUDE (dBFS)
SNR, SINAD (dB)
SNR
SINAD
fCLK = 79.95392MHz
fIN = 175.00168MHz
SFDR, -THD
vs. ANALOG INPUT AMPLITUDE
MAX1209 toc17
ANALOG INPUT AMPLITUDE (dBFS)
SFDR, -THD (dBc)
SFDR
-THD
fCLK = 79.95392MHz
fIN = 175.00168MHz
POWER DISSIPATION
vs. ANALOG INPUT AMPLITUDE
MAX1209 toc18
ANALOG INPUT AMPLITUDE (dBFS)
POWER DISSIPATION (mW)
ANALOG + DIGITAL POWER
ANALOG POWER
DIFFERENTIAL CLOCK
fCLK = 79.95392MHz
fIN = 175.0016MHz
CL ≈ 5pF
SNR, SINAD
vs. ANALOG POWER-INPUT VOLTAGEMAX1209 toc19
VDD (V)
SNR, SINAD (dB)
fCLK = 80.03584MHz
fIN = 32.11399MHz
SNR
SINAD
SFDR, -THD
vs. ANALOG POWER-INPUT VOLTAGEMAX1209 toc20
VDD (V)
SFDR, -THD (dBc)
fCLK = 80.03584MHz
fIN = 32.11399MHz
SFDR
-THD
POWER DISSIPATION
vs. ANALOG POWER-INPUT VOLTAGEMAX1209 toc21
VDD (V)
POWER DISSIPATION (mW)
DIFFERENTIAL CLOCK
fCLK = 80.03584MHz
fIN = 32.11399MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
SNR, SINAD
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGEMAX1209 toc22
OVDD (V)
SNR, SINAD (dB)
fCLK = 80.03584MHz
fIN = 32.11399MHz
SNR
SINAD
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
SFDR, -THD
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGEMAX1209 toc23
OVDD (V)
SFDR, -THD (dBc)
fCLK = 80.03584MHz
fIN = 32.11399MHz
SFDR
-THD
POWER DISSIPATION
vs. OUTPUT-DRIVER POWER-INPUT VOLTAGEMAX1209 toc24
OVDD (V)
SFDR, -THD (dBc)
DIFFERENTIAL CLOCK
fCLK = 80.03584MHz
fIN = 32.11399MHz
CL ≈ 5pF
ANALOG + DIGITAL POWER
ANALOG POWER
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADCSNR, SINAD vs. TEMPERATURE
MAX1209 toc25
TEMPERATURE (°C)
SNR, SINAD (dB)
fCLK ≈ 80MHz
fIN ≈ 175MHz
SNR
SINAD
SFDR, -THD vs. TEMPERATURE
MAX1209 toc26
TEMPERATURE (°C)
SFDR, -THD (dBc)
fCLK ≈ 80MHz
fIN ≈ 175MHz
SFDR
-THD
ANALOG POWER DISSIPATION
vs. TEMPERATURE
MAX1209 toc27
TEMPERATURE (°C)
ANALOG POWER DISSIPATION (
DIFFERENTIAL CLOCK
fCLK ≈ 80MHz
fIN ≈ 175MHz
CL ≈ 5pF
OFFSET ERROR vs. TEMPERATURE
MAX1209 toc28
TEMPERATURE (°C)
OFFSET ERROR (%FS)
VREFIN = 2.048V
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
GAIN ERROR vs. TEMPERATURE
MAX1209 toc29
TEMPERATURE (°C)
GAIN ERROR (%FS)
VREFIN = 2.048V
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADCREFP, COM, REFN
SHORT-CIRCUIT PERFORMANCE
MAX1209 toc34
SINK CURRENT (mA)
VOLTAGE
(V)
VREFPVCOM
VREFN
INTERNAL REFERENCE MODE
AND BUFFERED EXTERNAL
REFERENCE MODE0
REFP, COM, REFN
LOAD REGULATION
MAX1209 toc33
SINK CURRENT (mA)
VOLTAGE
(V)
VREFP
VCOM
VREFN
INTERNAL REFERENCE MODE AND
BUFFERED EXTERNAL REFERENCE MODE
Typical Operating Characteristics (continued)(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low,
G/T= low, fCLK= 80MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
REFERENCE OUTPUT VOLTAGE
LOAD REGULATION
MAX1209 toc30
IREFOUT SINK CURRENT (mA)
REFOUT
(V)+85°C
+25°C
-40°C
REFERENCE OUTPUT VOLTAGE
SHORT-CIRCUIT PERFORMANCE
MAX1209 toc31
IREFOUT SINK CURRENT (mA)
REFOUT
(V)
+85°C
+25°C
-40°C
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX1209 toc32
TEMPERATURE (°C)
REFOUT
(V)
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
PINNAMEFUNCTIONREFP
Positive Reference I/O. The full-scale analog input range is ±(VREFP - VREFN). Bypass REFP to GND with
a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and REFN.
Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side of the
printed circuit (PC) board.REFN
Negative Reference I/O. The full-scale analog input range is ±(VREFP - VREFN). Bypass REFN to GND
with a 0.1µF capacitor. Connect a 1µF capacitor in parallel with a 10µF capacitor between REFP and
REFN. Place the 1µF REFP to REFN capacitor as close to the device as possible on the same side
of the PC board.COM
Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM to
GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on theopposite side of the PC board and connected to the MAX1209 through a via.
4, 7, 16,GNDGround. Connect all ground pins and EP together.INPPositive Analog InputINNNegative Analog InputDCEDuty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer.
Connect DCE high (OVDD or VDD) to enable the internal duty-cycle equalizer.CLKN
Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.CLKP
Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential
clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-
ended clock signal to CLKP and connect CLKN to GND.CLKTYPClock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect
CLKTYP to OVDD or VDD to define the differential clock input.
12–15, 36VDDAnalog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥2.2µF and 0.1µF. Connect all VDD pins to the same potential.
17, 34OVDDOutput-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
parallel capacitor combination of ≥2.2µF and 0.1µF.DOR
Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of
range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog
input is within its full-scale range (Figure 6).D11CMOS Digital Output, Bit 11 (MSB)D10CMOS Digital Output, Bit 10D9CMOS Digital Output, Bit 9D8CMOS Digital Output, Bit 8D7CMOS Digital Output, Bit 7D6CMOS Digital Output, Bit 6D5CMOS Digital Output, Bit 5D4CMOS Digital Output, Bit 4D3CMOS Digital Output, Bit 3
Pin Description
MAX1209
12-Bit, 80Msps, 3.3V IF-Sampling ADC
PINNAMEFUNCTIOND2CMOS Digital Output, Bit 2D1CMOS Digital Output, Bit 1D0CMOS Digital Output, Bit 0 (LSB)
31, 32I.C.Internally Connected. Leave I.C. unconnected.DAV
Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for
any input clock duty-cycle variations. DAV is typically used to latch the MAX1209 output data into an
external back-end digital circuit.PDPower-Down Input. Force PD high for power-down mode. Force PD low for normal operation.REFOUT
Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN
or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a≥0.1µF capacitor.REFIN
Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to
GND with a ≥0.1µF capacitor. In these modes,VREFP - VREFN = VREFIN/2. For unbuffered external
reference-mode operation, connect REFIN to GND.G/TOutput Format Select Input. Connect G/T to GND for the two’s complement digital output format.
Connect G/T to OVDD or VDD for the Gray code digital output format.
—EP
Exposed Paddle. The MAX1209 relies on the exposed paddle connection for a low-inductance ground
connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the
top-side PC board ground plane to the bottom-side PC board ground plane.
Pin Description (continued)MAX1209Σ+
DIGITAL ERROR CORRECTION
FLASH
ADC
T/H
DAC
STAGE 2
D11–D0
INP
INN
STAGE 1T/HSTAGE 9STAGE 10
END OF PIPE
OUTPUT
DRIVERS
D11–D0
Figure 1. Pipeline Architecture—Stage Blocks
MAX1209
Detailed DescriptionThe MAX1209 uses a 10-stage, fully differential,
pipelined architecture (Figure1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
From input to output, the total clock-cycle latency is 8.5
clock cycles.
Each pipeline converter stage converts its input voltage
into a digital output code. At every stage, except the
last, the error between the input voltage and the digital
output code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure2 shows the
MAX1209 functional diagram.
Input Track-and-Hold (T/H) CircuitFigure3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a common-mode input voltage of VDD / 2
±0.5V.
The MAX1209 sampling clock controls the ADC’s
switched-capacitor T/H architecture (Figure3), allowing
the analog input signal to be stored as charge on the
sampling capacitors. These switches are closed (track)
when the sampling clock is high and open (hold) when
the sampling clock is low (Figure4). The analog input
signal source must be capable of providing the dynam-
ic current necessary to charge and discharge the sam-
pling capacitors. To avoid signal degradation, these
capacitors must be charged to one-half LSB accuracy
within one-half of a clock cycle.
The analog input of the MAX1209 supports differential
or single-ended input drive. For optimum performance
with differential inputs, balance the input impedance of
INP and INN and set the common-mode voltage to mid-
supply (VDD / 2). The MAX1209 provides the optimum
common-mode voltage of VDD / 2 through the COM
output when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures10, 11, and 12.
Reference Output (REFOUT) An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX1209. The power-down logic input (PD) enables
and disables the reference circuit. The reference circuit
requires 10ms to power up and settle when power is
applied to the MAX1209 or when PD transitions from
high to low. REFOUT has approximately 17kΩto GND
when the MAX1209 is in power-down.
The internal bandgap reference and its buffer generate
VREFOUTto be 2.048V. The reference temperature coeffi-
cient is typically +50ppm/°C. Connect an external ≥0.1µF
bypass capacitor from REFOUT to GND for stability.
12-Bit, 80Msps, 3.3V IF-Sampling ADCMAX1209
INP
INN
12-BIT
PIPELINE
ADCDEC
REFERENCE
SYSTEMCOM
REFOUT
REFN
REFP
OVDD
DAVOUTPUT
DRIVERS
D11–D0
DOR
REFIN
T/H
POWER CONTROL
AND
BIAS CIRCUITS
CLKPCLOCK
GENERATOR
AND
DUTY-CYCLE
EQUALIZER
CLKN
CLKTYP
VDD
GND
DCE
G/T
Figure 2. Simplified Functional Diagram
MAX1209
CPAR
2pF
VDDBOND WIRE
INDUCTANCE
1.5nH
INP
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS:
*CSAMPLE
1.9pF
CPAR
2pF
VDDBOND WIRE
INDUCTANCE
1.5nH
INN
*CSAMPLE
1.9pF
RSAMPLE =1
fCLK x CSAMPLE
Figure 3. Simplified Input Track-and-Hold Circuit
