MAX1195ECM ,Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel OutputsApplications DDMAX1195GND N.C.7 30Baseband I/Q Sampling WLAN, WWAN, WLL,INB- 8 29 N.C.MMDS ModemsIN ..
MAX1196ECM+D ,Dual 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Multiplexed Parallel OutputsApplications DDV 6 31 OGNDDDMAX1196Baseband I/Q SamplingGND 7 30 A/BINB- N.C.8 29Multichannel IF Sa ..
MAX1198ECM+D ,Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputsfeatures parallel, CMOS-compatible three-state outputs. The digital output format can be set to two ..
MAX1198ECM-D ,Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel OutputsELECTRICAL CHARACTERISTICS(V = 3.3V, OV = 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM ..
MAX120 ,500ksps, Sampling, 12-Bit ADC with Track/Hold and ReferenceFeaturesThe MAX120/MAX122 complete, BiCMOS, sampling 12-bit ● 12-Bit Resolutionanalog-to-digital co ..
MAX1202ACAP+ ,5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital InterfaceFeaturesThe MAX1202/MAX1203 are 12-bit data-acquisition sys- ● 8-Channel Single-Ended or 4-Channel ..
MAX3491EESD+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491EESD-T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491ESD ,3.3V-Powered, 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3491ESD+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX349CAP+ ,Serially Controlled, Low-Voltage, 8-Channel Dual 4-Channel Multiplexers
MAX349CPN ,Serially Controlled, Low-Voltage, 8-Channel/Dual 4-Channel Multiplexers
MAX1195ECM
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel Outputs
General DescriptionThe MAX1195 is a 3V, dual, 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1195
is optimized for low-power, small size, and high-dynamic
performance for applications in imaging, instrumentation
and digital communications. This ADC operates from a
single 2.7V to 3.6V supply, consuming only 87mW while
delivering a typical signal-to-noise and distortion (SINAD)
of 48.5dB at an input frequency of 20MHz and a sam-
pling rate of 40Msps. The T/H-driven input stages incor-
porate 400MHz (-3dB) input amplifiers. The converters
may also be operated with single-ended inputs. In addi-
tion to low operating power, the MAX1195 features a
3mA sleep mode as well as a 0.1µA power-down mode
to conserve power during idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired, for applications requiring
increased accuracy or a different input voltage range.
The MAX1195 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two’s
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1195 is available in a 7mm x 7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible higher speed versions of the MAX1195
are also available. Refer to the MAX1197 data sheet for
60Msps and the MAX1198 data sheet for 100Msps. In
addition to these speed grades, this family will include a
multiplexed output version (MAX1196, 40Msps), for
which digital data is presented time interleaved and on
a single, parallel 8-bit output port.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1183 data sheet. With the N.C. pins of the MAX1195
internally pulled down to ground, this ADC becomes a
drop-in replacement for the MAX1183.
Applications
FeaturesSingle 2.7V to 3.6V OperationExcellent Dynamic Performance
48.5dB/46.7dB SINAD at fIN= 20MHz/200MHz
68.7dBc/55.7dBc SFDR at fIN= 20MHz/200MHz-72dB Interchannel Crosstalk at fIN= 20MHzLow Power
87mW (Normal Operation)
9mW (Sleep Mode)
0.3µW (Shutdown Mode)0.05dB Gain and ±0.05°Phase MatchingWide ±1VP-PDifferential Analog Input Voltage
Range400MHz -3dB Input BandwidthOn-Chip 2.048V Precision Bandgap ReferenceUser-Selectable Output Format—Two’s
Complement or Offset BinaryPin-Compatible 8-Bit and 10-Bit Upgrades
Available
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Pin Configuration
Ordering Information19-2410; Rev 0; 4/02
Functional Diagram and Pin Compatible Upgrades table
appear at end of data sheet.*EP = Exposed paddle
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical
Imaging
Battery-Powered
Instrumentation
WLAN, WWAN, WLL,
MMDS Modems
Set-Top Boxes
VSAT Terminals
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 40MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at = +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND...............................-0.3V to VDD
REFIN, REFOUT, REFP, REFN,
COM, CLK to GND.................................-0.3V to (VDD+ 0.3V)OE, PD, SLEEP, T/B, D7A–D0A,
D7B–D0B to OGND.............................-0.3V to (OVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C).........1000mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 40MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 40MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at = +25°C.)
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 40MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at = +25°C.)
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Note 1:Guaranteed by design. Not subject to production testing.
Note 2:Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 3:Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two
applied input signals with the same magnitude (peak-to-peak) at fIN1and fIN2.
Note 4:REFIN and REFOUT should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 5:REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) and 2.2µF (typ) capacitor.
Note 6:Typical analog output current at fINA&B= 20MHz. For digital output currents vs. analog input frequency,
see Typical Operating Characteristics.
Note 7:See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock
level to 50% of the data output level.
Note 8:Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level.
Crosstalk is measured by calculating the power ratio of the fundamental of each channel’s FFT.
Note 9:Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT.
Note 10:Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental
of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 11:SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode.
ELECTRICAL CHARACTERISTICS (continued)(VDD= OVDD= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, VIN= 2VP-P(differential with respect to COM), CL= 10pF at digital outputs, fCLK= 40MHz, TA= TMINto TMAX, unless
otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characerization. Typical values are at = +25°C.)
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Typical Operating Characteristics(VDD= 3V, OVDD= 3V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 40MHz, CL≈10pF TA= +25°C, unless otherwise
noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCYMAX1195 toc09
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1195 toc08
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
SIGNAL-TO-NOISE + DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1195 toc07
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
MAX1195 toc06
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1195 toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)131112789106
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1195 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1195 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1195 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
MAX1195 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)161214468102
020
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)(VDD= 3V, OVDD= 3V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 40MHz, CL≈10pF TA= +25°C, unless otherwise
noted.)
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Typical Operating Characteristics (continued)(VDD= 3V, OVDD= 3V, VREFIN= 2.048V, differential input at -1dB FS, fCLK= 40MHz, CL≈10pF TA= +25°C, unless otherwise
noted.)
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Detailed DescriptionThe MAX1195 uses a seven-stage, fully differential,
pipelined architecture (Figure1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by two, and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all seven stages.
Input Track-and-Hold CircuitsFigure2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuits sample the
input signals onto the two capacitors (C2a and C2b)
through switches S4a and S4b. S2a and S2b set the
common mode for the amplifier input, and open simul-
MAX1195
Dual, 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Pin Description (continued)Figure1. Pipelined Architecture—Stage Blocks
