MAX1182ECM+D ,Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel OutputsApplicationsV 6 31 OGNDDDMAX1182GND 7 30 D0BHigh Resolution ImagingINB- 8 29 D1BI/Q Channel Digitiz ..
MAX1182ECM+TD ,Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel OutputsELECTRICAL CHARACTERISTICS(V = +3V, OV = +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM ..
MAX1183ECM+D ,Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel OutputsELECTRICAL CHARACTERISTICS(V = 3V, OV = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM t ..
MAX1183ECM-D ,Dual 10-Bit, 40Msps, 3V, Low-Power ADC with Internal Reference and Parallel OutputsApplicationsINA- 5 32 OVDDV 6 31 OGNDDDMAX1183High-Resolution ImagingGND 7 30 D0BINB- 8 29 D1BI/Q C ..
MAX1185ECM+TD ,Dual 10-Bit, 20Msps, +3V, Low-Power ADC with Internal Reference and Multiplexed Parallel OutputsApplicationsINB- 8 29 N.C.INB+ 9 28 N.C.High Resolution ImagingGND 10 27 N.C.I/Q Channel Digitizati ..
MAX1187AEUI+ ,16-Bit, 135ksps, Single-Supply ADCs with Bipolar Analog Input RangeMAX1179/MAX1187/MAX118919-2675; Rev 1; 1/0316-Bit, 135ksps, Single-Supply ADCs withBipolar Analog I ..
MAX3490ECSA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490ECSA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490ECSA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490ECSA+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490EEPA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3490EESA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX1182ECM+D-MAX1182ECM+TD
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs
General DescriptionThe MAX1182 is a +3V, dual 10-bit analog-to-digital
converter (ADC) featuring fully-differential wideband
track-and-hold (T/H) inputs, driving two pipelined, 9-
stage ADCs. The MAX1182 is optimized for low-power,
high-dynamic performance applications in imaging,
instrumentation and digital communication applications.
This ADC operates from a single +2.7V to +3.6V sup-
ply, consuming only 195mW while delivering a typical
signal-to-noise ratio (SNR) of 59dB at an input frequen-
cy of 20MHz and a sampling rate of 65Msps. The T/H
driven input stages incorporate 400MHz (-3dB) input
amplifiers. The converters may also be operated with
single-ended inputs. In addition to low operating power,
the MAX1182 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
An internal +2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of the internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1182 features parallel, CMOS-compatible
three-state outputs. The digital output format is set to
two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of +1.7V to +3.6V for flexible inter-
facing. The MAX1182 is available in a 7mm x 7mm, 48-
pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible higher and lower speed versions of the
MAX1182 are also available. Please refer to the
MAX1180 datasheet for 105Msps, the MAX1181
datasheet for 80Msps, the MAX1183 datasheet for
40Msps, and the MAX1184 datasheet for 20Msps. In
addition to these speed grades, this family includes a
20Msps multiplexed output version (MAX1185), for
which digital data is presented time-interleaved on a
single, parallel 10-bit output port.
ApplicationsHigh Resolution Imaging
I/Q Channel Digitization
Multchannel IF Undersampling
Instrumentation
Video Application
FeaturesSingle +3V OperationExcellent Dynamic Performance:
59dB SNR at fIN= 20MHz
77dB SFDR at fIN= 20MHz Low Power:
65mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)0.02dB Gain and 0.25°Phase Matching (typ)Wide ±1VP-PDifferential Analog Input Voltage
Range400MHz -3dB Input BandwidthOn-Chip +2.048V Precision Bandgap ReferenceUser-Selectable Output Format—Two’s
Complement or Offset Binary48-Pin TQFP Package with Exposed Pad for
Improved Thermal DissipationEvaluation Kit Available
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Pin Configuration19-2094; Rev 0; 7/01
Ordering Information
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +3V, OVDD= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10kΩresistor, VIN= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 5), fCLK= 65MHz (50% duty cycle),
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDD to GND...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND...............................-0.3V to VDD
REFIN, REFOUT, REFP, REFN, CLK,
COM to GND..........................................-0.3V to (VDD + 0.3V)OE, PD, SLEEP, T/B, D9A–D0A,
D9B–D0B to OGND.............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C).......1000mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead temperature (soldering, 10s)..................................+300°C
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +3V, OVDD= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10kΩresistor, VIN= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 5), fCLK= 65MHz (50% duty cycle),= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +3V, OVDD= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10kΩresistor, VIN= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 5), fCLK= 65MHz (50% duty cycle),
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)(VDD= +3V, OVDD= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10kΩresistor, VIN= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs (Note 5), fCLK= 65MHz (50% duty cycle),
Note 1:SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale
input voltage range.
Note 2:Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 3:Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 4:With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5:Equivalent dynamic performance is obtainable over full OVDDrange with reduced CL.
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Typical Operating Characteristics(VDD= +3V, OVDD= +2.5V, internal reference, differential input at -0.5dB FS, fCLK= 65MHz, CL≈10pF, TA= +25°C, unless otherwise
noted.)
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel OutputsTOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
MAX1182 toc10
ANALOG INPUT FREQUENCY (MHz)
THD (dB)-74
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
MAX1182 toc11
ANALOG INPUT FREQUENCY (MHz)
SFDR (dB)
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, SINGLE-ENDEDMAX1182 toc12
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)100100010
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, SINGLE-ENDEDMAX1182 toc13
ANALOG INPUT FREQUENCY (MHz)
GAIN (dB)100100010
SIGNAL-TO-NOISE RATIO
vs. INPUT POWER (fIN = 20.085279MHz)
MAX1182 toc14
INPUT POWER (dB FS)
SNR (dB)
SIGNAL-TO-NOISE + DISTORTION
vs. INPUT POWER (fIN = 20.085279MHz)
MAX1182 toc15
INPUT POWER (dB FS)
SINAD (dB)
TOTAL HARMONIC DISTORTION
vs. INPUT POWER (fIN = 20.085279MHz)
MAX1182 toc16
INPUT POWER (dB FS)
THD (dB)
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (fIN = 20.085279MHz)
MAX1182 toc17
INPUT POWER (dB FS)
SFDR (dB)
INTEGRAL NONLINEARITY
(BEST-ENDPOINT FIT)
MAX1182 toc18
DIGITAL OUTPUT CODE
INL (LSB)
Typical Operating Characteristics (continued)(VDD= +3V, OVDD= +2.5V, internal reference, differential input at -0.5dB FS, fCLK= 65MHz, CL≈10pF, TA= +25°C, unless otherwise
noted.)
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel OutputsDIFFERENTIAL NONLINEARITY
MAX1182 toc19
DIGITAL OUTPUT CODE
DNL (LSB)
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (VREFIN = +2.048V)
MAX1182 toc20
TEMPERATURE (°C)
GAIN ERROR (% FS)
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE
(VREFIN = +2.048V)
MAX1182 toc21
TEMPERATURE (°C)
OFFSET ERROR (% FS)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1182 toc22
VDD (V)
IVDD
(mA)
ANALOG SUPPLY CURRENT
vs. TEMPERATUREMAX1182 toc23
TEMPERATURE (°C)
IVDD
(mA)
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
MAX1182 toc24
VDD (V)
IVDD4045355055606570
SFDR, SNR, THD, SINAD
vs. CLOCK DUTY CYCLEMAX1182 toc25
CLOCK DUTY CYCLE (%)
SFDR, SNR, THD, SINAD (dB)
INTERNAL REFERENCE VOLTAGE
vs. ANALOG POWER VOLTAGE
MAX1182 toc26
VDD (V)
REFOUT
(V)
Typical Operating Characteristics (continued)(VDD= +3V, OVDD= +2.5V, internal reference, differential input at -0.5dB FS, fCLK= 65MHz, CL≈10pF, TA= +25°C, unless otherwise
noted.)
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel OutputsINTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1182 toc27
TEMPERATURE (°C)
REFOUT
(V)
N-2N-1NN+1N+2
OUTPUT NOISE HISTOGRAM (DC INPUT)MAX1182 toc28
DIGITAL OUTPUT CODE
COUNTS
ypical Operating Characteristics (continued)(VDD= +3V, OVDD= +2.5V, internal reference, differential input at -0.5dB FS, fCLK= 65MHz, CL≈10pF, TA= +25°C, unless otherwise
noted.)
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Detailed DescriptionThe MAX1182 uses a 9-stage, fully-differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
Counting the delay through the output latch, the clock-
cycle latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held-
input voltages into a digital code. The digital-to-analog
converters (DACs) convert the digitized results back
into analog voltages, which are then subtracted from
the original held input signals. The resulting error sig-
nals are then multiplied by two and the residues are
passed along to the next pipeline stages where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
Input Track-and-Hold (T/H) CircuitsFigure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and
hold mode. In track mode, switches S1, S2a, S2b, S4a,
S4b, S5a and S5b are closed. The fully-differential cir-
cuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the amplifier input, and
open simultaneously with S1, sampling the input wave-
form. Switches S4a and S4b are then opened before
switches S3a and S3b, connect capacitors C1a and
C1b to the output of the amplifier, and switch S4c is
closed. The resulting differential voltages are held on
capacitors C2a and C2b. The amplifiers are used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. These values are then
presented to the first-stage quantizers and isolate the
pipelines from the fast-changing inputs. The wide input
bandwidth T/H amplifiers allow the MAX1182 to track-
and-sample/hold analog inputs of high frequencies (>
Nyquist). The ADC inputs (INA+, INB+, INA-, and INB-)
can be driven either differentially or single-ended.
Match the impedance of INA+ and INA- as well as
INB+ and INB- and set the common-mode voltage to
mid-supply (VDD/2) for optimum performance.
MAX1182
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel OutputsFigure 1. Pipelined Architecture—Stage Blocks
