MAX11645EUA+T ,Low-Power, 1-/2-Channel, I²C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm PackageApplications IndicatorsOrdering InformationMedical Instruments System Supervision2PIN- I C SLAVE Ba ..
MAX1165AEUI+ ,Low-Power, 16-Bit Analog-to-Digital Converters with Parallel InterfaceELECTRICAL CHARACTERISTICS(AV = DV = +5V, external reference = +4.096V, C = 4.7µF, C = 0.1µF, T = T ..
MAX1165BCUI ,Low-Power, 16-Bit Analog-to-Digital Converters with Parallel InterfaceApplications*Future product—contact factory for availability.Temperature Sensor/MonitorIndustrial P ..
MAX1166BCUP ,Low-Power, 16-Bit Analog-to-Digital Converters with Parallel InterfaceMAX1165/MAX116619-2551; Rev 2; 8/08Low-Power, 16-Bit Analog-to-Digital Converterswith Parallel Inte ..
MAX1166BCUP+ ,Low-Power, 16-Bit Analog-to-Digital Converters with Parallel InterfaceApplicationsOrdering Information continued at end of data sheet.Temperature Sensor/MonitorIndustria ..
MAX1166BEUP+ ,Low-Power, 16-Bit Analog-to-Digital Converters with Parallel InterfaceFeatures♦ 16-Bit Wide (MAX1165) and Byte Wide (MAX1166)The MAX1165/MAX1166 16-bit, low-power, succe ..
MAX3486ECSA+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486EEPA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486EESA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486EESA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486EESA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ESA ,3.3V-Powered, 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX11645EUA+T
Low-Power, 1-/2-Channel, I²C, 12-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package
General DescriptionThe MAX11644/MAX11645 low-power, 12-bit, 1-/2-
channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, clock, and
an I2C-compatible 2-wire serial interface. These
devices operate from a single supply of 2.7V to 3.6V
(MAX11645) or 4.5V to 5.5V (MAX11644) and require
only 6μA at a 1ksps sample rate. AutoShutdown™ pow-
ers down the devices between conversions, reducing
supply current to less than 1μA at low throughput rates.
The MAX11644/MAX11645 each measure two single-
ended or one differential input. The fully differential ana-
log inputs are software configurable for unipolar or
bipolar, and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11645 fea-
tures a 2.048V internal reference and the MAX11644
features a 4.096V internal reference.
The MAX11644/MAX11645 are available in an ultra-tiny
1.9mm x 2.2mm WLP package and an 8-pin μMAX®
package. The MAX11644/MAX11645 are guaranteed
over the extended temperature range (-40°C to +85°C).
For pin-compatible 10-bit parts, refer to the MAX11646/
MAX11647 data sheet.
Applications
FeaturesUltra-Tiny 1.9mm x 2.2mm Wafer Level PackageHigh-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed ModeSingle-Supply
2.7V to 3.6V (MAX11645)
4.5V to 5.5V (MAX11644)Internal Reference
2.048V (MAX11645)
4.096V (MAX11644)External Reference: 1V to VDDInternal Clock
2-Channel Single-Ended or 1-Channel Fully
DifferentialInternal FIFO with Channel-Scan ModeLow Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down ModeSoftware-Configurable Unipolar/Bipolar
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
Ordering Information19-5225; Rev 1; 9/10
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-
PACKAGE2C SLAVE
ADDRESS
MAX11644EUA+ -40°C to +85°C 8 μMAX 0110110
MAX11645EUA+ -40°C to +85°C 8 μMAX 0110110
MAX11645EWC+ -40°C to +85°C 12 WLP 0110110
Typical Operating Circuit and Selector Guide appear at end
of data sheet.AutoShutdown is a trademark and μMAX is a registered trademark
of Maxim Integrated Products, Inc.
+Denotes a lead(Pb)-free/RoHs-compliant package.
Handheld Portable
Applications
Medical Instruments
Battery-Powered Test
Equipment
Solar-Powered Remote
Systems
Received-Signal-Strength
Indicators
System Supervision
Power-Supply Monitoring
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 2.7V to 3.6V (MAX11645), VDD= 4.5V to 5.5V (MAX11644), VREF= 2.048V (MAX11645), VREF= 4.096V (MAX11644),
fSCL=1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0, AIN1, REF to GND..............................-0.3V to the lower of
(VDD+ 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin μMAX (derate 4.5mW/°C above +70°C)..............362mW
12-Pin WLP (derate 16.1mW/°C above +70°C)..........1288mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s)
μMAX only.....................................................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY (Note 2) Resolution 12 Bits
Relative Accuracy INL (Note 3) ±1 LSB
Differential Nonlinearity DNL No missing codes over temperature ±1 LSB
Offset Error ±4 LSB
Offset-Error Temperature
Coefficient Relative to FSR 0.3 ppm/°C
Gain Error (Note 4) ±4 LSB
Gain-Temperature Coefficient Relative to FSR 0.3 ppm/°C
Channel-to-Channel Offset
Matching ±0.1 LSB
Channel-to-Channel Gain
Matching ±0.1 LSB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps)Signal-to-Noise Plus Distortion SINAD 70 dB
Total Harmonic Distortion THD Up to the 5th harmonic -78 dB
Spurious-Free Dynamic Range SFDR 78 dB
Full-Power Bandwidth SINAD > 68dB 3 MHz
Full-Linear Bandwidth -3dB point 5 MHz
CONVERSION RATE Internal clock 7.5 Conversion Time (Note 5) tCONVExternal clock 10.6 μs
Internal clock, SCAN[1:0] = 01 51 Throughput Rate fSAMPLEExternal clock 94.4 ksps
Track/Hold Acquisition Time 800 ns
Internal Clock Frequency 2.8 MHz
External clock, fast mode 60 Aperture Delay (Note 6) tADExternal clock, high-speed mode 30 ns
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
ELECTRICAL CHARACTERISTICS (continued)(VDD= 2.7V to 3.6V (MAX11645), VDD= 4.5V to 5.5V (MAX11644), VREF= 2.048V (MAX11645), VREF= 4.096V (MAX11644),
fSCL=1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT (AIN0/AIN1) Unipolar 0 VREFInput Voltage Range, Single-
Ended and Differential (Note 7) Bipolar 0 ±VREF/2V
Input Multiplexer Leakage On/off leakage current, VAIN_ = 0 or VDD±0.01 ±1 μA
Input Capacitance CIN 22 pF
INTERNAL REFERENCE (Note 8) MAX11645 1.968 2.048 2.128 Reference Voltage VREF TA = +25°C MAX11644 3.936 4.096 4.256 V
Reference-Voltage Temperature
Coefficient TCVREF 25 ppm/°C
REF Short-Circuit Current 2 mA
REF Source Impedance 1.5 k
EXTERNAL REFERENCE REF Input Voltage Range VREF (Note 9) 1 VDD V
REF Input Current IREF fSAMPLE = 94.4ksps 40 μA
DIGITAL INPUTS/OUTPUTS (SCL, SDA) Input-High Voltage VIH 0.7 x VDD V
Input-Low Voltage VIL 0.3 x VDD V
Input Hysteresis VHYST 0.1 x VDD V
Input Current IIN VIN = 0 to VDD ±10 μA
Input Capacitance CIN 15 pF
Output Low Voltage VOL ISINK = 3mA 0.4 V
POWER REQUIREMENTS MAX11645 2.7 3.6 Supply Voltage VDD
MAX11644 4.5 5.5
Internal reference 900 1150 fSAMPLE = 94.4ksps
external clock External reference 670 900
Internal reference 530 fSAMPLE = 40ksps
internal clock External reference 230
Internal reference 380 fSAMPLE = 10ksps
internal clock External reference 60
Internal reference 330 fSAMPLE =1ksps
internal clock External reference 6
Supply Current IDD
Shutdown (internal REF off) 0.5 10
μA
Power-Supply Rejection Ratio PSRR Full-scale input (Note 10) ±0.5 ±2.0 LSB/V
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
TIMING CHARACTERISTICS (Figure 1)(VDD= 2.7V to 3.6V (MAX11645), VDD= 4.5V to 5.5V (MAX11644), VREF= 2.048V (MAX11645), VREF= 4.096V (MAX11644),
fSCL=1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE Serial-Clock Frequency fSCL 400 kHz
Bus Free Time Between a STOP (P)
and a START (S) Condition tBUF 1.3 μs
Hold Time for START Condition tHD,STA 0.6 μs
Low Period of the SCL Clock tLOW 1.3 μs
High Period of the SCL Clock tHIGH 0.6 μs
Setup Time for a Repeated START
(Sr) Condition tSU,STA 0.6 μs
Data Hold Time tHD,DAT (Note 11) 0 900 ns
Data Setup Time tSU,DAT 100 ns
Rise Time of Both SDA and SCL
Signals, Receiving tR Measured from 0.3VDD - 0.7VDD 20 + 0.1CB 300 ns
Fall Time of SDA Transmitting tF Measured from 0.3VDD - 0.7VDD (Note 12) 20 + 0.1CB 300 ns
Setup Time for STOP Condition tSU,STO 0.6 μs
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP 50 ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 13) Serial-Clock Frequency fSCLH (Note 14) 1.7 MHz
Hold Time, Repeated START
Condition tHD,STA 160 ns
Low Period of the SCL Clock tLOW 320 ns
High Period of the SCL Clock tHIGH 120 ns
Setup Time for a Repeated START
Condition tSU,STA 160 ns
Data Hold Time tHD,DAT (Note 11) 0 150 ns
Data Setup Time tSU,DAT 10 ns
Rise Time of SCL Signal
(Current Source Enabled) tRCL 20 80 ns
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rise Time of SCL Signal After
Acknowledge Bit tRCL1 Measured from 0.3VDD - 0.7VDD 20 160 ns
Fall Time of SCL Signal tFCL Measured from 0.3VDD - 0.7VDD 20 80 ns
Rise Time of SDA Signal tRDA Measured from 0.3VDD - 0.7VDD 20 160 ns
Fall Time of SDA Signal tFDA Measured from 0.3VDD - 0.7VDD (Note 12) 20 160 ns
Setup Time for STOP Condition tSU,STO 160 ns
Capacitive Load for Each Bus Line CB 400 pF
Pulse Width of Spike Suppressed tSP (Notes 11 and 14) 0 10 ns
TIMING CHARACTERISTICS (Figure 1) (continued)(VDD= 2.7V to 3.6V (MAX11645), VDD= 4.5V to 5.5V (MAX11644), VREF= 2.048V (MAX11645), VREF= 4.096V (MAX11644),
fSCL=1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming
notation.) (Note 1)
Note 1:All WLP devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2:For DC accuracy, the MAX11644 is tested at VDD= 5V and the MAX11645 is tested at VDD= 3V with an external
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
Note 3:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4:Offset nulled.
Note 5:Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7:The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to VDD.
Note 8:When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
0.1μF capacitor and a 2kΩseries resistor (see theTypical Operating Circuit).
Note 9:ADC performance is limited by the converter’s noise floor, typically 300μVP-P.
Note 10:Measured for the MAX11645 as:
and for the MAX11644, where N is the number of bits:
Note 11:A master device must provide a data hold time for SDA (referred to VILof SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12:The minimum value is specified at TA= +25°C.
Note 13:CB= total capacitance of one bus line in pF.
Note 14:fSCLmust meet the minimum clock low time plus the rise/fall times.VVVFS
REF(.)(.)452⎡⎣⎤⎦×⎡⎢⎥−45.)VVVVFS
REF(.)(.)272⎡⎣⎤⎦×⎡⎢⎥−27.)V
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
Typical Operating Characteristics(VDD= 3.3V (MAX11645), VDD= 5V (MAX11644), fSCL= 1.7MHz, 50% duty cycle, fSAMPLE= 94.4ksps, single-ended, unipolar,
TA = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX11644 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
AX11644 toc02
DIGITAL OUTPUT CODE
INL (LSB)4000100015005002000250030003500-140
-2010k20k30k40k50k
FFT PLOTMAX11644 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
fSAMPLE = 94.4ksps
fIN = 10kHz
SUPPLY CURRENT
vs. TEMPERATURE
AX11644 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
INTERNAL REFERENCE MAX11644
INTERNAL REFERENCE MAX11645
EXTERNAL REFERENCE MAX11644
EXTERNAL REFERENCE MAX11645
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
AX11644 toc05
SUPPLY VOLTAGE (V)
IDD
SDA = SCL = VDD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
AX11644 toc06
SUPPLY CURRENT (
MAX11644
MAX11645
0
ANALOG SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
AX11644 toc07
CONVERSION RATE (ksps)
AVERAGE I
EXTERNAL REFERENCE
INTERNAL REFERENCE ALWAYS ON
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
OFFSET ERROR vs. TEMPERATUREAX11644 toc11
TEMPERATURE (°C)
OFFSET ERROR (LSB)653550-10520-25
OFFSET ERROR vs. SUPPLY VOLTAGE
AX11644 toc12
VDD (V)
OFFSET ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
AX11644 toc13
GAIN ERROR (LSB)653550-10520-25
GAIN ERROR vs. SUPPLY VOLTAGE
AX11644 toc14
GAIN ERROR (LSB)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
AX11644 toc09
TEMPERATURE (°C)
REF
NOR
ALIZED
NORMALIZED TO VALUE AT TA = +25°C
MAX11644
MAX11645
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
AX11644 toc10
VDD (V)
REF
(V)
MAX11644
NORMALIZED TO
REFERENCE VALUE AT
VDD = 5V
MAX11645
NORMALIZED TO
REFERENCE VALUE AT
VDD = 3.3V
Typical Operating Characteristics (continued)(VDD= 3.3V (MAX11645), VDD= 5V (MAX11644), fSCL= 1.7MHz, 50% duty cycle, fSAMPLE= 94.4ksps, single-ended, unipolar,
TA = +25°C, unless otherwise noted.)
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
Pin Description
PIN
μMAXWLPNAMEFUNCTION1,2 A1, A2 AIN0, AIN1 Analog Inputs — N.C. No connection. Not internally connected. A4 REF Reference Input/Output. Selected in the setup register (see Tables 1 and 6).
5 C4 SCL Clock Input
6 C3 SDA Data Input/Output A3, B1–B4,
C2 GND Ground
8 C1 VDD Positive Supply. Bypass to GND with a 0.1μF capacitor.
SDA
SCLREF
VDD
GNDAIN1
N.C.
AIN0
µMAX
TOP VIEW
MAX11644
MAX11645
TOP VIEW (BUMPS ON BOTTOM)
MAX11645
GND
AIN1GNDREF
GNDGND
SDA
GND
GNDSCL
WLP
VDD
AIN0
Pin Configuration
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package tHD,STA
tSU,DAT
tHIGHtF
tHD,DATtHD,STASrA
SCL
SDA
tSU,STAtLOWtBUF
tSU,STO
tHD,STA
tSU,DAT
tHIGH
tFCL
tHD,DATtHD,STASrA
SCL
SDA
tSU,STAtLOWtBUF
tSU,STO
tRCLtRCL1
HS MODEF/S MODE
A) F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
B) HS-MODE 2-WIRE SERIAL-INTERFACE TIMINGtFDAtRDAtRtF
Figure 1. 2-Wire Serial-Interface Timing
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
Detailed DescriptionThe MAX11644/MAX11645 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX11644/MAX11645
measure either two single-ended or one differential
input(s). These devices feature a high-speed, 2-wire
serial interface supporting data rates up to 1.7MHz.
Figure 2 shows the simplified internal structure for the
MAX11644/MAX11645.
Power SupplyThe MAX11644/MAX11645 operate from a single sup-
ply and consume 670μA (typ) at sampling rates up to
94.4ksps. The MAX11645 feature a 2.048V internal ref-
erence and the MAX11644 feature a 4.096V internal ref-
erence. All devices can be configured for use with an
external reference from 1V to VDD.
Analog Input and Track/HoldThe MAX11644/MAX11645 analog-input architecture
contains an analog-input multiplexer (mux), a fully dif-
ferential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer
connects CT/Hbetween the analog input selected by
CS[0] (see the Configuration/Setup Bytes (Write Cycle)
section) and GND (Table 3). In differential mode, the
analog-input multiplexer connects CT/Hto the + and -
analog inputs selected by CS[0] (Table 4).
ANALOG
INPUT
MUX
AIN1
REF
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX11644)
2.048V (MAX11645)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
AND RAM
REF
T/H12-BIT
ADC
VDD
GND
MAX11644
MAX11645
Figure 2. Simplified Functional Diagram
VDD
IOL
IOH
VOUT
400pF
SDA
Figure 3. Load Circuit
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package During the acquisition interval, the T/H switches are in
the track position and CT/Hcharges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/Has a stable sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of a 12-bit resolution. This action
requires 12 conversion clock cycles and is equivalent
to transferring a charge of 11pF x (VIN+- VIN-) from
CT/Hto the binary weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog input
to GND. This input capacitor forms an RC filter with the
source impedance limiting the analog-input bandwidth.
For larger source impedances, use a buffer amplifier to
maintain analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte. See the Slave Addresssection.
The T/H circuitry enters hold mode on the falling clock
edge of the acknowledge bit of the address byte (the
ninth clock pulse). A conversion or a series of conver-
sions is then internally clocked and the MAX11644/
MAX11645 hold SCL low. With external clock mode, the
T/H circuitry enters track mode after a valid address on
the rising edge of the clock during the read (R/W= 1)
bit. Hold mode is then entered on the rising edge of the
second clock pulse during the shifting out of the first
byte of the result. The conversion is performed during
the next 12 clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ≥95 (RSOURCE+ RIN) x CIN
where RSOURCEis the analog-input source impedance,
RIN= 2.5kΩ, and CIN= 22pF. tACQis 1.5/fSCLfor internal
clock mode and tACQ= 2/fSCLfor external clock mode.
Analog Input BandwidthThe MAX11644/MAX11645 feature input-tracking cir-
cuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
TRACK
TRACK
HOLD
CT/H
CT/H
TRACK
TRACK
HOLD
AIN0
AIN1
GND
ANALOG INPUT MUX
CAPACITIVE
DAC
REF
CAPACITIVE
DAC
REFMAX11644
MAX11645
HOLD
HOLD
TRACK
HOLD
VDD/2
Figure 4. Equivalent Input Circuit
