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MAX11613EUA+MAXIMN/a531avaiLow-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small Packages
MAX11614EEE+MAXIMN/a200avaiLow-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small Packages
MAX11615EEE+MAXIMN/a200avaiLow-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small Packages
MAX11617EEE+ |MAX11617EEEMAXIMN/a146avaiLow-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small Packages


MAX11613EUA+ ,Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small PackagesFeaturesThe MAX11612–MAX11617 low-power, 12-bit, multi- 2♦ High-Speed I C-Compatible Serial Interfa ..
MAX11614EEE+ ,Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small PackagesELECTRICAL CHARACTERISTICS(V = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V = 4.5V to 5.5V (MAX1161 ..
MAX11615EEE+ ,Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small PackagesApplications SystemsMAX11613EWC+ -40°C to +85°C 12 WLP 0110100Medical Instruments Received-Signal-S ..
MAX11617EEE+ ,Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small PackagesApplicationsMAX11612EUA+ -40°C to +85°C 8 µMAX 0110100Handheld Portable Solar-Powered RemoteMAX1161 ..
MAX1162ACUB+ ,16-Bit, +5V, 200ksps ADC with 10µA ShutdownELECTRICAL CHARACTERISTICS(AV = DV = +4.75V to +5.25V, f = 4.8MHz (50% duty cycle), 24 clocks/conve ..
MAX1162BEUB+ ,16-Bit, +5V, 200ksps ADC with 10µA Shutdownfeatures a separate digital supply, allowingdirect interfacing with +2.7V to +5.25V digital logic.♦ ..
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA+T ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486EEPA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers


MAX11613EUA+-MAX11614EEE+-MAX11615EEE+-MAX11617EEE+
Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small Packages
General Description
The MAX11612–MAX11617 low-power, 12-bit, multi-
channel analog-to-digital converters (ADCs) feature
internal track/hold (T/H), voltage reference, clock, and an 2C-compatible 2-wire serial interface. These devices
operate from a single supply of 2.7V to 3.6V
(MAX11613/MAX11615/MAX11617) or 4.5V to 5.5V
(MAX11612/MAX11614/MAX11616) and require only
670µA at the maximum sampling rate of 94.4ksps.
Supply current falls below 230µA for sampling rates
under 46ksps. AutoShutdown™ powers down the
devices between conversions, reducing supply current
to less than 1µA at low throughput rates. The
MAX11612/MAX11613 have 4 analog input channels
each, the MAX11614/MAX11615 have 8 analog input
channels each, while the MAX11616/MAX11617 have
12 analog input channels each. The fully differential
analog inputs are software configurable for unipolar or
bipolar, and single-ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11613/
MAX11615/MAX11617 feature a 2.048V internal refer-
ence and the MAX11612/MAX11614/MAX11616 feature
a 4.096V internal reference.
The MAX11612/MAX11613 are available in an 8-pin
µMAX®package and the MAX11613 is available in an
ultra-small, 1.9mm x 2.2mm, 12-bump wafer-level pack-
age (WLP). The MAX11614–MAX11617 are available in a
16-pin QSOP package and in an ultra-small, 2.14mm x
2.0mm, 16-bump wafer level package (WLP). The
MAX11612–MAX11617 are guaranteed over the extend-
ed temperature range (-40°C to +85°C). For pin-compati-
ble 10-bit parts, refer to the MAX11606–MAX11611 data
sheet. For pin-compatible 8-bit parts, refer to the
MAX11600–MAX11605 data sheet.
Applications
Features
High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
Single-Supply
2.7V to 3.6V (MAX11613/MAX11615/MAX11617)
4.5V to 5.5V (MAX11612/MAX11614/MAX11616)
Ultra-Small Packages
8-Pin µMAX (MAX11612/MAX11613)
1.9mm x 2.2mm, 12-Bump WLP (MAX11613)
16-Pin QSOP (MAX11614–MAX11617)
2.14mm x 2.0mm, 16-Bump WLP (MAX11615/
MAX11617)
Internal Reference
2.048V (MAX11613/MAX11615/MAX11617)
4.096V (MAX11612/MAX11614/MAX11616)
External Reference: 1V to VDDInternal Clock4-Channel Single-Ended or 2-Channel Fully
Differential (MAX11612/MAX11613)
8-Channel Single-Ended or 4-Channel Fully
Differential (MAX11614/MAX11615)
12-Channel Single-Ended or 6-Channel Fully
Differential (MAX11616/MAX11617)
Internal FIFO with Channel-Scan ModeLow Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
Software-Configurable Unipolar/Bipolar
Ordering Information
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
PARTTEMP RANGEPIN-
PACKAGE2C SLAVE
ADDRESS
MAX11612EUA+
-40°C to +85°C8 µMAX0110100
MAX11613EUA+
-40°C to +85°C8 µMAX0110100
MAX11613EWC+-40°C to +85°C12 WLP0110100
MAX11614EEE+
-40°C to +85°C16 QSOP0110011
MAX11615EEE+
-40°C to +85°C16 QSOP0110011
MAX11615EWE+-40°C to +85°C16 WLP0110011
MAX11616EEE+
-40°C to +85°C16 QSOP0110101
MAX11617EEE+
-40°C to +85°C16 QSOP0110101
MAX11617EWE+-40°C to +85°C16 WLP0110101
Pin Configurations, Typical Operating Circuit, and Selector

AutoShutdown is a trademark of Maxim Integrated Products, Inc.
+Denotes a lead(Pb)-free/RoHs-compliant package.
Handheld Portable
Applications
Medical Instruments
Battery-Powered Test
Equipment
Solar-Powered Remote
Systems
Received-Signal-Strength
Indicators
System Supervision
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VDD= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF= 2.048V
(MAX11613/MAX11615/MAX11617), VREF= 4.096V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming notation.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0–AIN11,
REF to GND............-0.3V to the lower of (VDD+ 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 5.9mW/°C above +70°C)..........470.6mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW
12-Pin WLP (derate 16.1mW/°C above +70°C).........1288mW
16-Pin WLP (derate 17.2mW/°C above +70°C..........1376mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 2)

Resolution12Bits
Relative AccuracyINL(Note 3)±1LSB
Differential NonlinearityDNLNo missing codes over temperature±1LSB
Offset Error±4LSB
Offset-Error Temperature
CoefficientRelative to FSR0.3ppm/°C
Gain Error(Note 4)±4LSB
Gain-Temperature CoefficientRelative to FSR0.3ppm/°C
Channel-to-Channel Offset
Matching±0.1LSB
Channel-to-Channel Gain
Matching±0.1LSB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps)

Signal-to-Noise Plus DistortionSINAD70dB
Total Harmonic DistortionTHDUp to the 5th harmonic-78dB
Spurious-Free Dynamic RangeSFDR78dB
Full-Power BandwidthSINAD > 68dB3MHz
Full-Linear Bandwidth-3dB point5MHz
CONVERSION RATE

Internal clock7.5Conversion Time (Note 5)tCONVExternal clock10.6µs
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF= 2.048V
(MAX11613/MAX11615/MAX11617), VREF= 4.096V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Internal clock, SCAN[1:0] = 0151
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX11616/MAX11617)51Throughput RatefSAMPLE
External clock94.4
ksps
Track/Hold Acquisition Time800ns
Internal Clock Frequency2.8MHz
External clock, fast mode60Aperture Delay (Note 6)tADExternal clock, high-speed mode30ns
ANALOG INPUT (AIN0–AIN11)

Unipolar0VREFInput-Voltage Range, Single-
Ended and Differential (Note 7)Bipolar0±VREF/2V
Input Multiplexer Leakage CurrentON/OFF leakage current, VAIN_ = 0 or VDD±0.01±1µA
Input CapacitanceCIN22pF
INTERNAL REFERENCE (Note 8)
AX11613/M AX 11615/MAX 116171.9682.0482.128Reference VoltageVREFTA = +25°CM AX11612/M AX 11614/MAX 116163.9364.0964.256V
Reference-Voltage Temperature
CoefficientTCVREF25ppm/°C
REF Short-Circuit Current2mA
REF Source Impedance1.5kΩ
EXTERNAL REFERENCE

REF Input-Voltage RangeVREF(Note 9)1VDDV
REF Input CurrentIREFfSAMPLE = 94.4ksps40µA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)

Input-High VoltageVIH0.7 x VDDV
Input-Low VoltageVIL0.3 x VDDV
Input HysteresisVHYST0.1 x VDDV
Input CurrentIINVIN = 0 to VDD±10µA
Input CapacitanceCIN15pF
Output Low VoltageVOLISINK = 3mA0.4V
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF= 2.048V
(MAX11613/MAX11615/MAX11617), VREF= 4.096V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS

MAX11613/MAX11615/MAX116172.73.6Supply VoltageVDDMAX11612/MAX11614/MAX116164.55.5V
Internal reference9001150fSAMPLE = 94.4ksps
external clockExternal reference670900
Internal reference530fSAMPLE = 40ksps
internal clockExternal reference230
Internal reference380fSAMPLE = 10ksps
internal clockExternal reference60
Internal reference330fSAMPLE =1ksps
internal clockExternal reference6
Supply CurrentIDD
Shutdown (internal REF off)0.510
Power-Supply Rejection RatioPSRRFull-scale input (Note 10)±0.5±2.0LSB/V
TIMING CHARACTERISTICS (Figure 1)

(VDD= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF= 2.048V
(MAX11613/MAX11615/MAX11617), VREF= 4.096V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming notation.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICS FOR FAST MODE

Serial-Clock FrequencyfSCL400kHz
Bus Free Time Between a STOP (P)
and a START (S) ConditiontBUF1.3µs
Hold Time for START (S) ConditiontHD, STA0.6µs
Low Period of the SCL ClocktLOW1.3µs
High Period of the SCL ClocktHIGH0.6µs
Setup Time for a Repeated START
Condition (Sr)tSU, STA0.6µs
Data Hold Time (Note 11)tHD, DAT0900ns
Data Setup TimetSU, DAT100ns
Rise Time of Both SDA and SCL
Signals, ReceivingtRMeasured from 0.3VDD - 0.7VDD20 + 0.1CB300ns
Fall Time of SDA TransmittingtFMeasured from 0.3VDD - 0.7VDD (Note 12)20 + 0.1CB300ns
Setup Time for STOP (P) ConditiontSU, STO0.6µs
Capacitive Load for Each Bus LineCB400pF
Pulse Width of Spike SuppressedtSP50ns
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 13)

Serial-Clock FrequencyfSCLH(Note 14)1.7MHz
Hold Time, Repeated START
Condition (Sr)tHD, STA160ns
Low Period of the SCL ClocktLOW320ns
High Period of the SCL ClocktHIGH120ns
Setup Time for a Repeated START
Condition (Sr)tSU, STA160ns
Data Hold TimetHD, DAT(Note 11)0150ns
Data Setup TimetSU, DAT10ns
Rise Time of SCL Signal
(Current Source Enabled)tRCL2080ns
Rise Time of SCL Signal After
Acknowledge BittRCL1Measured from 0.3VDD - 0.7VDD20160ns
Fall Time of SCL SignaltFCLMeasured from 0.3VDD - 0.7VDD2080ns
Rise Time of SDA SignaltRDAMeasured from 0.3VDD - 0.7VDD20160ns
Fall Time of SDA SignaltFDAMeasured from 0.3VDD - 0.7VDD (Note 12)20160ns
Setup Time for STOP (P) ConditiontSU, STO160ns
Capacitive Load for Each Bus LineCB400pF
Pulse Width of Spike SuppressedtSP(Notes 11 and 14)010ns
TIMING CHARACTERISTICS (Figure 1) (continued)

(VDD= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF= 2.048V
(MAX11613/MAX11615/MAX11617), VREF= 4.096V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming notation.) (Note 1)
Note 1:
All WLP devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2:
For DC accuracy, the MAX11612/MAX11614/MAX11616 are tested at VDD= 5V and the
MAX11613/MAX11615/MAX11617are tested at VDD= 3V. All devices are configured for unipolar, single-ended inputs.
Note 3:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4:
Offset nulled.
Note 5:
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7:
The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 8:
When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩseries resistor (see the Typical Operating Circuit).
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 10:
Measured as for the MAX11613/MAX11615/MAX11617:VVVFSREF)(.).)272127−×⎡⎢⎢⎥⎥
Typical Operating Characteristics
(VDD= 3.3V (MAX11613/MAX11615/MAX11617), VDD= 5V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, (50% duty cycle),
fSAMPLE= 94.4ksps, single-ended, unipolar, TA= +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX11612 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX11612 toc02
DIGITAL OUTPUT CODE
INL (LSB)4000100015005002000250030003500
-6010k20k30k40k50k
FFT PLOT

MAX11612 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
fSAMPLE = 94.4ksps
fIN = 10kHz
SUPPLY CURRENT
vs. TEMPERATURE
MAX11612 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (
INTERNAL REFERENCE MAX11617/MAX11615/
MAX11613
INTERNAL REFERENCE MAX11616/MAX11614/
MAX11612
EXTERNAL REFERENCE MAX11616/MAX11614/
MAX11612
EXTERNAL REFERENCE MAX11617/MAX11615/
MAX11613
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX11612 toc05
IDD
SDA = SCL = VDD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX11612 toc06
SUPPLY CURRENT (
MAX11616/MAX11614/MAX11612
MAX11617/MAX11615/MAX11613
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages

and for the MAX11612/MAX11614/MAX11616, where N is the number of bits:
Note 11:
A master device must provide a data hold time for SDA (referred to VILof SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12:
The minimum value is specified at TA= +25°C.
Note 13:
CB= total capacitance of one bus line in pF.
Note 14:
fSCLmust meet the minimum clock low time plus the rise/fall times.VVVFS
REF)(.).)452145−×⎡⎢⎢⎥⎥
TIMING CHARACTERISTICS (Figure 1) (continued)

(VDD= 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD= 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF= 2.048V
(MAX11613/MAX11615/MAX11617), VREF= 4.096V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C, see Tables 1–5 for programming notation.) (Note 1)
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages

AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
MAX11612 toc07
CONVERSION RATE (ksps)
AVERAGE I
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
MAX11616/MAX11614/MAX11612
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)

MAX11612 toc08
CONVERSION RATE (ksps)
AVERAGE I604020
MAX11617/MAX11615/MAX11613
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11612 toc09
TEMPERATURE (°C)
REF
NORMALIZED
NORMALIZED TO VALUE AT TA = +25°C
MAX11616/MAX11614/MAX11612
MAX11617/MAX11615/MAX11613
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX11612 toc10
VDD (V)
REF
(V)
MAX11616/MAX11614/MAX11612
NORMALIZED TO
REFERENCE VALUE AT
VDD = 5V
MAX11617/MAX11615/MAX11613
NORMALIZED TO
REFERENCE VALUE AT
VDD = 3.3V
OFFSET ERROR vs. TEMPERATURE

MAX11612 toc11
TEMPERATURE (°C)
OFFSET ERROR (LSB)653550-10520-25
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX11612 toc12
VDD (V)
OFFSET ERROR (LSB)
Typical Operating Characteristics (continued)
(VDD= 3.3V (MAX11613/MAX11615/MAX11617), VDD= 5V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, (50% duty cycle),
fSAMPLE= 94.4ksps, single-ended, unipolar, TA= +25°C, unless otherwise noted.)
Pin Description
PIN
MAX11612
MAX11613
MAX11614
MAX11615MAX11615
MAX11616
MAX11617MAX11617
µMAXWLPQSOPWLPQSOPWLP
NAMEFUNCTION

1, 2, 3A1, A2,5, 6, 7A1, A2, A35, 6, 7A1, A2, A3AIN0, AIN1,
AIN2—8–12A4, B4, C4,
D4, B18–12A4, B4, C4,
D4, C3AIN3–AIN7———4, 3, 2B3, B1, C2AIN8–AIN10
Analog InputsA4————AIN3/REF
Analog Input 3/Reference Input or
Output. Selected in the setup register
(see Tables 1 and 6).—1B2——REFReference Input or Output. Selected in
the setup register (see Tables 1 and 6).——1B2AIN11/REF
Analog Input 11/Reference Input or
Output. Selected in the setup register
(see Tables 1 and 6).C413D213D2SCLClock InputC314D314D3SDAData Input/Output
B1, B2,
B3, B4,B3, C2, C3,15D1GNDGroundC116C116C1VDDPositive Supply. Bypass to GND with a
0.1µF capacitor.—2, 3, 4———N .C .N o connecti on. N ot i nter nal l y connected .
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
GAIN ERROR vs. TEMPERATURE

MAX11612 toc13
TEMPERATURE (°C)
GAIN ERROR (LSB)653550-10520-25
GAIN ERROR vs. SUPPLY VOLTAGE
MAX11612 toc14
VDD (V)
GAIN ERROR (LSB)
Typical Operating Characteristics (continued)
(VDD= 3.3V (MAX11613/MAX11615/MAX11617), VDD= 5V (MAX11612/MAX11614/MAX11616), fSCL= 1.7MHz, (50% duty cycle),
fSAMPLE= 94.4ksps, single-ended, unipolar, TA= +25°C, unless otherwise noted.)
tHD.STA
tSU.DAT
tHIGHtF
tHD.DATtHD.STASrA
SCL
SDA
tSU.STAtLOWtBUF
tSU.STO
tHD.STA
tSU.DAT
tHIGH
tFCL
tHD.DATtHD.STASrA
SCL
SDA
tSU.STAtLOWtBUF
tSU.STO
tRCLtRCL1
HS MODEF/S MODE
A. F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
B. HS-MODE 2-WIRE SERIAL-INTERFACE TIMING
tFDAtRDAtRtF
Figure 1. 2-Wire Serial-Interface Timing
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
Detailed Description

The MAX11612–MAX11617 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX11612/MAX11613
are 4-channel ADCs, the MAX11614/MAX11615 are
8-channel ADCs, and the MAX11616/MAX11617 are
12-channel ADCs. These devices feature a high-speed,
2-wire serial interface supporting data rates up to
1.7MHz. Figure 2 shows the simplified internal structure
for the MAX11616/MAX11617.
Power Supply

The MAX11612–MAX11617 operate from a single sup-
ply and consume 670µA (typ) at sampling rates up to
94.4ksps. The MAX11613/MAX11615/MAX11617 fea-
ture a 2.048V internal reference and the MAX11612/
MAX11614/MAX11616 feature a 4.096V internal refer-
ence. All devices can be configured for use with an
external reference from 1V to VDD.
Analog Input and Track/Hold

The MAX11612–MAX11617 analog-input architecture
contains an analog-input multiplexer (mux), a fully dif-
ferential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer con-
nects CT/Hbetween the analog input selected by
CS[3:0] (see the Configuration/Setup Bytes (Write Cycle)
section) and GND (Table 3). In differential mode, the
analog-input multiplexer connects CT/Hto the + and -
analog inputs selected by CS[3:0] (Table 4).
ANALOG
INPUT
MUX
AIN1
AIN11/REF
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX11616)
2.048V (MAX11617)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
AND RAM
REF
T/H12-BIT
ADC
VDD
GND
MAX11616
MAX11617
Figure 2. MAX11616/MAX11617 Simplified Functional Diagram
VDD
IOL
IOH
VOUT
400pF
SDA
Figure 3. Load Circuit
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages

During the acquisition interval, the T/H switches are in
the track position and CT/Hcharges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/Has a stable sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of a 12-bit resolution. This action
requires 12 conversion clock cycles and is equivalent
to transferring a charge of 11pF ✕(VIN+- VIN-) from
CT/Hto the binary weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larg-
er source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte, see the Slave Address section. The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion or a series of conversions is then
internally clocked and the MAX11612–MAX11617 holds
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
edge of the clock during the read (R/W= 1) bit. Hold
mode is then entered on the rising edge of the second
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 12
clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ≥9 ✕(RSOURCE+ RIN) ✕CIN
where RSOURCEis the analog-input source impedance,
RIN= 2.5kΩ, and CIN= 22pF. tACQis 1.5/fSCLfor internal
clock mode and tACQ= 2/fSCLfor external clock mode.
Analog Input Bandwidth

The MAX11612–MAX11617 feature input-tracking circuit-
ry with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed tran-
sient events and measure periodic signals with band-
widths exceeding the ADC’s sampling rate by using
under sampling techniques. To avoid high-frequency
signals being aliased into the frequency band of interest,
anti-alias filtering is recommended.
Analog Input Range and Protection

Internal protection diodes clamp the analog input to
VDDand GND. These diodes allow the analog inputs to
TRACK
TRACK
HOLD
CT/H
CT/H
TRACK
TRACK
HOLD
AIN0
AIN1
AIN2
AIN3/REF
GND
ANALOG INPUT MUX
CAPACITIVE
DAC
REF
CAPACITIVE
DAC
REFMAX11612
MAX11613
HOLD
HOLD
TRACK
HOLD
VDD/2
Figure 4. Equivalent Input Circuit
MAX11612–MAX11617
Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages

swing from (GND - 0.3V) to (VDD+ 0.3V) without caus-
ing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above VDD.
Single-Ended/Differential Input

The SGL/DIFof the configuration byte configures the
MAX11612–MAX11617 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF= 1), the digital conversion results are
the difference between the analog input selected by
CS[3:0] and GND (Table 3). In differential mode (SGL/
DIF= 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS[3:0] (Table 4).
Unipolar/Bipolar

When operating in differential mode, the BIP/UNIbit of
the set-up byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±VREF/2. The digital output code is bina-
ry in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11612–MAX11617 al-
ways operates in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface

The MAX11612–MAX11617 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX11612–MAX11617 and the master
at rates up to 1.7MHz. The MAX11612–MAX11617 are
slaves that transfer and receive data. The master (typi-
cally a microcontroller) initiates data transfer on the bus
and generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ωor greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional. They
protect the input architecture of the MAX11612–
MAX11617 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
Bit Transfer

One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11612–MAX11617.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions

The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a
STOP condition (P), a low-to-high transition on SDA
while SCL is high (Figure 5). A repeated START condi-
tion (Sr) can be used in place of a STOP condition to
leave the bus active and the interface mode
unchanged (see the HS Modesection).
Acknowledge Bits

Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11612–MAX11617 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
SCL
SDASr
Figure 5. START and STOP Conditions
SCL
SDANOT ACKNOWLEDGE
ACKNOWLEDGE89
Figure 6. Acknowledge Bits
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