MAX11610EEE+T ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCsApplications SystemsPACKAGE ADDRESSMedical Instruments Received-Signal-StrengthMAX11606EUA+ -40°C t ..
MAX11611EEE+ ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCsEVALUATION KIT AVAILABLE MAX11606–MAX116112Low-Power, 4-/8-/12-Channel, I C,10-Bit ADCs in Ultra-S ..
MAX11613EUA+ ,Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small PackagesFeaturesThe MAX11612–MAX11617 low-power, 12-bit, multi- 2♦ High-Speed I C-Compatible Serial Interfa ..
MAX11614EEE+ ,Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small PackagesELECTRICAL CHARACTERISTICS(V = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V = 4.5V to 5.5V (MAX1161 ..
MAX11615EEE+ ,Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small PackagesApplications SystemsMAX11613EWC+ -40°C to +85°C 12 WLP 0110100Medical Instruments Received-Signal-S ..
MAX11617EEE+ ,Low-Power, 4-/8-/12-Channel, I²C, 12-Bit ADCs in Ultra-Small PackagesApplicationsMAX11612EUA+ -40°C to +85°C 8 µMAX 0110100Handheld Portable Solar-Powered RemoteMAX1161 ..
MAX3486CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486CSA+ ,3.3V Powered, 10Mbps and Slew-Rate Limited, True RS-485/RS-422 Transceivers
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3486ECSA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX11609EEE+-MAX11610EEE+-MAX11610EEE+T-MAX11611EEE+
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small PackagesEVALUATION KIT AVAILABLE
Handheld Portable
Applications
Medical Instruments
Battery-Powered Test
Equipment
Solar-Powered Remote
Systems
Received-Signal-Strength
Indicators
System Supervision
General DescriptionThe MAX11606–MAX11611 low-power, 10-bit, multichan-
nel analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an 2C-compatible 2-wire serial interface. These devices
operate from a single supply of 2.7V to 3.6V (MAX11607/
MAX11609/MAX11611) or 4.5V to 5.5V (MAX11606/
MAX11608/MAX11610) and require only 670µA at the
maximum sampling rate of 94.4ksps. Supply current falls
below 230µA for sampling rates under 46ksps.
AutoShutdown™ powers down the devices between conver-
sions, reducing supply current to less than 1µA at low
throughput rates. The MAX11606/MAX11607 have 4 analog
input channels each, the MAX11608/MAX11609 have 8 ana-
log input channels each, while the MAX11610/MAX11611
have 12 analog input channels each. The fully differential
analog inputs are software configurable for unipolar or bipo-
lar, and single ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11607/
MAX11609/MAX11611 feature a 2.048V internal reference
and the MAX11606/MAX11608/MAX11610 feature a
4.096V internal reference.
The MAX11606/MAX11607 are available in an 8-pin
µMAX®package. The MAX11607 is also available in an
ultra-small 1.9mm x 2.2mm WLP package. The
MAX11608–MAX11611 are available in a 16-pin QSOP
package. The MAX11606–MAX11611 are guaranteed
over the extended temperature range (-40°C to +85°C).
For pin-compatible 12-bit parts, refer to the
MAX11612–MAX11617 data sheet. For pin-compatible
8-bitparts, refer to the MAX11600–MAX11605 data sheet.
Applications
FeaturesHigh-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed ModeSingle-Supply
2.7V to 3.6V (MAX11607/MAX11609/MAX11611)
4.5V to 5.5V (MAX11606/MAX11608/MAX11610)Ultra-Small Packages
8-Pin µMAX (MAX11606/MAX11607)
12-Pin 1.9mm x 2.2mm, Wafer-Level Package
(MAX11607)
16-Pin QSOP (MAX11608–MAX11611)Internal Reference
2.048V (MAX11607/MAX11609/MAX11611)
4.096V (MAX11606/MAX11608/MAX11610)External Reference: 1V to VDDInternal Clock4-Channel Single-Ended or 2-Channel Fully
Differential (MAX11606/MAX11607)8-Channel Single-Ended or 4-Channel Fully
Differential (MAX11608/MAX11609)12-Channel Single-Ended or 6-Channel Fully
Differential (MAX11610/MAX11611)Internal FIFO with Channel-Scan ModeLow Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down ModeSoftware-Configurable Unipolar/Bipolar
Ordering Information
PARTTEMP RANGEPIN-
PACKAGE2C SLAVE
ADDRESS
MAX11606EUA+-40°C to +85°C8 µMAX0110100
MAX11607EUA+-40°C to +85°C8 µMAX0110100
MAX11607EWC+*-40°C to +85°C12 WLP0110100
MAX11608EEE+-40°C to +85°C16 QSOP0110011
MAX11609EEE+-40°C to +85°C16 QSOP0110011
MAX11610EEE+-40°C to +85°C16 QSOP0110101
MAX11611EEE+-40°C to +85°C16 QSOP0110101
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
+Denotes a lead(Pb)-free/RoHs-compliant package.
*Future product—contact factory for availability.
Pin Configurations, Typical Operating Circuit, and Selector
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF= 2.048V
(MAX11607/MAX11609/MAX11611), VREF= 4.096V (MAX11606/MAX11608/MAX11610), fSCL= 1.7MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming notation.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0–AIN11,
REF to GND............-0.3V to the lower of (VDD+ 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 5.9mW/°C above +70°C)..........470.6mW
12-Pin WLP (derate 16.1mW/°C above +70°C).........1288mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 2)Resolution10Bits
Relative AccuracyINL(Note 3)±1LSB
Differential NonlinearityDNLNo missing codes over temperature±1LSB
Offset Error±1LSB
Offset-Error Temperature
CoefficientRelative to FSR0.3ppm/°C
Gain Error(Note 4)±1LSB
Gain-Temperature CoefficientRelative to FSR0.3ppm/°C
Channel-to-Channel Offset
Matching±0.1LSB
Channel-to-Channel Gain
Matching±0.1LSB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps)Signal-to-Noise Plus DistortionSINAD60dB
Total Harmonic DistortionTHDUp to the 5th harmonic-70dB
Spurious Free Dynamic RangeSFDR70dB
Full-Power BandwidthSINAD > 57dB3.0MHz
Full-Linear Bandwidth-3dB point5.0MHz
CONVERSION RATEInternal clock6.8Conversion Time (Note 5)tCONVExternal clock10.6µs
Internal clock, SCAN[1:0] = 0153
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX11610/MAX11611)53Throughput RatefSAMPLE
External clock94.4
ksps
Track/Hold Acquisition Time800ns
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)(VDD= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF= 2.048V
(MAX11607/MAX11609/MAX11611), VREF= 4.096V (MAX11606/MAX11608/MAX11610), fSCL= 1.7MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInternal Clock Frequency2.8MHz
External clock, fast mode60Aperture Delay (Note 6)tADExternal clock, high-speed mode30ns
ANALOG INPUT (AIN0–AIN11)Unipolar0VREFInput-Voltage Range, Single-
Ended and Differential (Note 7)Bipolar0±VREF/2V
Input Multiplexer Leakage CurrentOn/off leakage current, VAIN_ = 0V or VDD±0.01±1µA
Input CapacitanceCIN22pF
INTERNAL REFERENCE (Note 8)AX 11607/M AX11609/M AX 116111.9682.0482.128Reference VoltageVREFTA = + 25° C M AX 11606/M AX11608/M AX 116103.9394.0964.256V
Reference-Voltage Temperature
CoefficientTCVREF25ppm/°C
REF Short-Circuit Current2mA
REF Source Impedance1.5kΩ
EXTERNAL REFERENCEREF Input-Voltage RangeVREF(Note 9)1VDDV
REF Input CurrentIREFfSAMPLE = 94.4ksps40µA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)Input High VoltageVIH0.7 x VDDV
Input Low VoltageVIL0.3 x VDDV
Input HysteresisVHYST0.1 x VDDV
Input CurrentIINVIN = 0 to VDD±10µA
Input CapacitanceCIN15pF
Output Low VoltageVOLISINK = 3mA0.4V
POWER REQUIREMENTSMAX11607/MAX11609/MAX116112.73.6Supply VoltageVDDMAX11606/MAX11608/MAX116104.55.5V
Internal reference9001150fSAMPLE = 94.4ksps
external clockExternal reference670900
Internal reference530fSAMPLE = 40ksps
internal clockExternal reference230
Internal reference380fSAMPLE = 10ksps
internal clockExternal reference60
Internal reference330fSAMPLE =1ksps
internal clockExternal reference6
Supply CurrentIDD
Shutdown (internal reference off)0.510
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)(VDD= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF= 2.048V
(MAX11607/MAX11609/MAX11611), VREF= 4.096V (MAX11606/MAX11608/MAX11610), fSCL= 1.7MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming notation.) (Note 1)
TIMING CHARACTERISTICS (Figure 1)(VDD= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF= 2.048V
(MAX11607/MAX11609/MAX11611), VREF= 4.096V (MAX11606/MAX11608/MAX11610), fSCL= 1.7MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTSPower-Supply Rejection RatioPSRRFull-scale input (Note 10)±0.01±0.5LSB/V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICS FOR FAST MODESerial-Clock FrequencyfSCL400kHz
Bus Free Time Between a
STOP (P) and a
START (S) Condition
tBUF1.3µs
Hold Time for START (S) ConditiontHD,STA0.6µs
Low Period of the SCL ClocktLOW1.3µs
High Period of the SCL ClocktHIGH0.6µs
Setup Time for a Repeated START
Condition (Sr)tSU,STA0.6µs
Data Hold TimetHD,DAT(Note 11)0900ns
Data Setup TimetSU,DAT100ns
Rise Time of Both SDA and SCL
Signals, ReceivingtRMeasured from 0.3VDD to 0.7VDD20 + 0.1CB300ns
Fall Time of SDA TransmittingtFMeasured from 0.3VDD to 0.7VDD (Note 12)20 + 0.1CB300ns
Setup Time for STOP (P) ConditiontSU,STO0.6µs
Capacitive Load for Each Bus LineCB400pF
Pulse Width of Spike SuppressedtSP50ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 13)Serial-Clock FrequencyfSCLH(Note 14)1.7MHz
Hold Time, Repeated START
Condition (Sr)tHD,STA160ns
Low Period of the SCL ClocktLOW320ns
High Period of the SCL ClocktHIGH120ns
Setup Time for a Repeated START
Condition (Sr)tSU,STA160ns
Data Hold TimetHD,DAT(Note 11)0150ns
Data Setup TimetSU,DAT10ns
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Note 1:All WLP devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
Note 2:For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at VDD= 5V and the MAX11607/MAX11609/MAX11611
are tested at VDD= 3V. All devices are configured for unipolar, single-ended inputs.
Note 3:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 4:Offset nulled.
Note 5:Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7:The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 8:When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩseries resistor (see the Typical Operating Circuit).
Note 9:ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 10:Measured as follows for the MAX11607/MAX11609/MAX11611:
and for the MAX11606/MAX11608/MAX11610, where N is the number of bits:
Note 11:A master device must provide a data hold time for SDA (referred to VILof SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12:The minimum value is specified at TA= +25°C.
Note 13:CB= total capacitance of one bus line in pF.
Note 14:fSCLmust meet the minimum clock low time plus the rise/fall times.VVVFS
REF)(.).)452145−
[]×⎡⎢⎤⎥VVVFS
REF)(.).)272127−×⎡⎢⎤⎥
TIMING CHARACTERISTICS (Figure 1) (continued)(VDD= 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD= 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF= 2.048V
(MAX11607/MAX11609/MAX11611), VREF= 4.096V (MAX11606/MAX11608/MAX11610), fSCL= 1.7MHz, TA= TMINto TMAX, unless other-
wise noted. Typical values are at TA= +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRise Time of SCL Signal
(Current Source Enabled)tRCLMeasured from 0.3VDD to 0.7VDD2080ns
Rise Time of SCL Signal after
Acknowledge BittRCL1Measured from 0.3VDD to 0.7VDD20160ns
Fall Time of SCL SignaltFCLMeasured from 0.3VDD to 0.7VDD2080ns
Rise Time of SDA SignaltRDAMeasured from 0.3VDD to 0.7VDD20160ns
Fall Time of SDA SignaltFDAMeasured from 0.3VDD to 0.7VDD (Note 12)20160ns
Setup Time for STOP (P) ConditiontSU,STO160ns
Capacitive Load for Each Bus LineCB400pF
Pulse Width of Spike SuppressedtSP(Notes 11 and 14)010ns
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Typical Operating Characteristics(VDD= 3.3V (MAX11607/MAX11609/MAX11611), VDD= 5V (MAX11606/MAX11608/MAX11610), fSCL= 1.7MHz, external clock,
fSAMPLE= 94.4ksps, single-ended, unipolar, TA= +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX11606 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX11606 toc02
DIGITAL OUTPUT CODE
INL (LSB)
-2010k20k30k40k50k
FFT PLOTMAX11606 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
fSAMPLE = 94.4ksps
fIN = 10kHz
SUPPLY CURRENT
vs. TEMPERATURE
MAX11606 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (
INTERNAL REFERENCE
MAX11610/MAX11608/
MAX11606
MAX11610/MAX11608/
MAX11606
MAX11611/MAX11609/
MAX11607
MAX11611/MAX11609/
MAX11607INTERNAL REFERENCE
EXTERNAL REFERENCE
EXTERNAL REFERENCE
SETUP BYTE
EXT REF: 10111011INT REF: 11011011
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX11606 toc05
SUPPLY VOLTAGE (V)
IDD
SDA = SCL = VDD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX11606 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (
MAX11611/MAX11609/MAX11607
MAX11610/MAX11608/MAX11606
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
MAX11606 toc07
CONVERSION RATE (ksps)
AVERAGE I
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
MAX11610/MAX11608/MAX11606200
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (EXTERNAL CLOCK)
MAX11606 toc08
CONVERSATION RATE (ksps)
AVERAGE IA
MAX11611/MAX11609/MAX11607
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small PackagesINTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11606 toc09
TEMPERATURE (°C)
REF
NORMALIZED
MAX11610/MAX11608/MAX11606
MAX11611/MAX11609/MAX11607
NORMALIZED TO REFERENCE VALUE
TA = +25°C
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX11606 toc10
VDD (V)
REF
NORMALIZED
MAX11610/11608/MAX11606,
NORMALIZED TO
REFERENCE VALUE AT
VDD = 5V
MAX11611/11609/MAX11607,
NORMALIZED TO
REFERENCE VALUE AT
VDD = 3.3V
Typical Operating Characteristics (continued)(VDD= 3.3V (MAX11607/MAX11609/MAX11611), VDD= 5V (MAX11606/MAX11608/MAX11610), fSCL= 1.7MHz, external clock,
fSAMPLE= 94.4ksps, single-ended, unipolar, TA= +25°C, unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
MAX11606 toc11
TEMPERATURE (°C)
OFFSET ERROR (LSB)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX11606 toc12
VDD (V)
OFFSET ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX11606 toc13
TEMPERATURE (°C)
GAIN ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX11606 toc14
VDD (V)
GAIN ERROR (LSB)
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Pin Description
PIN
MAX11606
MAX11607MAX11607MAX11608
MAX11609
MAX11610
MAX11611
µMAXWLPQSOP
NAMEFUNCTION1, 2, 3A1, A2, A35, 6, 75, 6, 7AIN0, AIN1, AIN2—8–128–12AIN3–AIN7——4, 3, 2AIN8, AIN9, AIN10
Analog InputsA4——AIN3/REFAnalog Input 3/Reference Input or Output. Selected in
the setup register (see Tables 1 and 6).—1—REFReference Input or Output. Selected in the setup
register (see Tables 1 and 6).——1AIN11/REFAnalog Input 11/Reference Input or Output. Selected in
the setup register (see Tables 1 and 6).C41313SCLClock InputC31414SDAData Input/OutputB1–B4, C21515GNDGround
8C11616VDDPositive Supply. Bypass to GND with a 0.1_F capacitor.—2, 3, 4—N.C.No Connection. Not internally connected.
tHD:STA
tSU:DAT
tHIGHtF
tHD:DATtHD:STASrA
SCL
SDA
tSU:STAtLOWtBUF
tSU:STO
tHD:STA
tSU:DAT
tHIGH
tFCL
tHD:DATtHD:STASrA
SCL
SDA
tSU:STAtLOWtBUF
tSU:STO
tRCLtRCL1
HS MODEF/S MODE
A. F/S-MODE 2-WIRE SERIAL-INTERFACE TIMING
B. HS-MODE 2-WIRE SERIAL-INTERFACE TIMINGtFDAtRDAtRtF
Figure 1. 2-Wire Serial-Interface Timing
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Detailed DescriptionThe MAX11606–MAX11611 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX11606/MAX11607
are 4-channel ADCs, the MAX11608/MAX11609 are
8-channel ADCs, and the MAX11610/MAX11611 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 2 shows the simplified internal structure
for the MAX11610/MAX11611.
Power SupplyThe MAX11606–MAX11611 operates from a single sup-
ply and consumes 670µA (typ) at sampling rates up to
94.4ksps. The MAX11607/MAX11609/MAX11611 feature
a 2.048V internal reference and the MAX11606/
MAX11608/MAX11610 feature a 4.096V internal refer-
ence. All devices can be configured for use with an
external reference from 1V to VDD.
Analog Input and Track/HoldThe MAX11606–MAX11611 analog-input architecture
contains an analog-input multiplexer (mux), a fully dif-
ferential track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog-input multiplexer con-
nects CT/Hbetween the analog input selected by
CS[3:0] (see the Configuration/Setup Bytes (Write
Cycle) section) and GND (Table 3). In differential mode,
the analog- input multiplexer connects CT/Hto the + and
- analog inputs selected by CS[3:0] (Table 4).
During the acquisition interval, the T/H switches are in
the track position and CT/Hcharges to the analog input
ANALOG
INPUT
MUX
AIN1
AIN11/REF
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX11610)
2.048V (MAX11611)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
AND RAM
REF
T/H10-BIT
ADC
VDD
GND
MAX11610
MAX11611
Figure 2. MAX11610/MAX11611 Functional Diagram
VDD
IOL
IOH
VOUT
400pF
SDA
Figure 3. Load Circuit
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packagessignal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/Has a stable sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of 10-bit resolution. This action
requires 10 conversion clock cycles and is equivalent
to transferring a charge of 11pF ✕(VIN+- VIN-) from
CT/Hto the binary weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larg-
er source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte (see the Slave Address section). The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion or a series of conversions is then
internally clocked and the MAX11606–MAX11611 holds
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
edge of the clock during the read (R/W = 1) bit. Hold
mode is then entered on the rising edge of the second
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 10
clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ≥9 ✕(RSOURCE+ RIN) ✕CIN
where RSOURCEis the analog-input source impedance,
RIN= 2.5kΩ, and CIN= 22pF. tACQis 1.5/fSCLfor internal
clock mode and tACQ= 2/fSCLfor external clock mode.
Analog Input BandwidthThe MAX11606–MAX11611 feature input-tracking cir-
cuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and ProtectionInternal protection diodes clamp the analog input to
VDDand GND. These diodes allow the analog inputs to
TRACK
TRACK
HOLD
CT/H
CT/H
TRACK
TRACK
HOLD
AIN0
AIN1
AIN2
AIN3/REF
GND
ANALOG INPUT MUX
CAPACITIVE
DAC
REF
CAPACITIVE
DAC
REFMAX11606
MAX11607
HOLD
HOLD
TRACK
HOLD
VDD/2
Figure 4. Equivalent Input Circuit
MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packagesswing from (VGND- 0.3V) to (VDD+ 0.3V) without caus-
ing damage to the device. For accurate conversions
the inputs must not go more than 50mV below VGNDor
above VDD.
Single-Ended/Differential InputThe SGL/DIFof the configuration byte configures the
MAX11606–MAX11611 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF= 1), the digital conversion results are
the difference between the analog input selected by
CS[3:0] and GND (Table 3). In differential mode (SGL/
DIF= 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS[3:0] (Table 4).
Unipolar/BipolarWhen operating in differential mode, the BIP/UNIbit of
the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±VREF/2. The digital output code is bina-
ry in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11606–MAX11611
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital InterfaceThe MAX11606–MAX11611 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX11606–MAX11611 and the master
at rates up to 1.7MHz. The MAX11606–MAX11611 are
slaves that transfer and receive data. The master (typi-
cally a microcontroller) initiates data transfer on the bus
and generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ωor greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional.
They protect the input architecture of the MAX11606–
MAX11611 from high voltage spikes on the bus lines,
minimize crosstalk, and undershoot of the bus signals.
Bit TransferOne data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11606–
MAX11611. The data on SDA must remain stable dur-
ing the high period of the SCL clock pulse. Changes in
SDA while SCL is stable are considered control signals
(see the START and STOP Conditions section). Both
SDA and SCL remain high when the bus is not busy.
START and STOP ConditionsThe master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see the HS Modesection).
Acknowledge BitsData transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11606–MAX11611 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
SCL
SDASr
Figure 5. START and STOP Conditions
SCL
SDANOT ACKNOWLEDGE
ACKNOWLEDGE89
Figure 6. Acknowledge Bits
