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MAX11600EKA+TN/AN/a2500avai2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCs
MAX11603EEE+MAXIMN/a200avai2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCs
MAX11605EEE+MAXIMN/a200avai2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCs


MAX11600EKA+T ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCsFeatures2♦ High-Speed I C-Compatible Serial InterfaceThe MAX11600–MAX11605 low-power, 8-bit, multic ..
MAX11603EEE+ ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCsApplicationsMedical InstrumentsBattery-Powered Test EquipmentPin Configurations and Typical Operati ..
MAX11605EEE+ ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCsELECTRICAL CHARACTERISTICS(V = 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), V = 4.5V to 5.5V (MAX1160 ..
MAX11609EEE+ ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCsFeatures2The MAX11606–MAX11611 low-power, 10-bit, multichan- ♦ High-Speed I C-Compatible Serial Int ..
MAX11610EEE+ ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCsELECTRICAL CHARACTERISTICS(V = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V = 4.5V to 5.5V (MAX1160 ..
MAX11610EEE+T ,2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCsApplications SystemsPACKAGE ADDRESSMedical Instruments Received-Signal-StrengthMAX11606EUA+ -40°C t ..
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MAX11600EKA+T-MAX11603EEE+-MAX11605EEE+
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 8-Bit ADCs
General Description
The MAX11600–MAX11605 low-power, 8-bit, multichan-
nel, analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply and require only 350µA at
the maximum sampling rate of 188ksps. Auto-
Shutdown™ powers down the devices between conver-
sions, reducing supply current to less than 1µA at low
throughput rates. The MAX11600/MAX11601 provide 4
analog input channels each, the MAX11602/MAX11603
provide 8 analog input channels each while the
MAX11604/MAX11605 provide 12 analog input channels.
The analog inputs are software configurable for unipolar or
bipolar and single-ended or pseudo-differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX11601/
MAX11603/MAX11605 feature a 2.048V internal refer-
ence and the MAX11600/MAX11602/MAX11604 feature
a 4.096V internal reference.
The MAX11600/MAX11601 are available in 8-pin SOT23
packages. The MAX11602–MAX11605 are available in
16-pin QSOP packages. The MAX11600–MAX11605 are
guaranteed over the extended industrial temperature
range (-40°C to +85°C). Refer to the MAX11606–
MAX11611 for 10-bit devices and to the MAX11612–
MAX11617 for 12-bit devices.
Applications

Handheld Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Features
High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
Single Supply
2.7V to 3.6V (MAX11601/MAX11603/MAX11605)
4.5V to 5.5V (MAX11600/MAX11602/MAX11604)
Internal Reference
2.048V (MAX11601/MAX11603/MAX11605)
4.096V (MAX11600/MAX11602/MAX11604)
External Reference: 1V to VDDInternal Clock4-Channel Single-Ended or 2-Channel Pseudo-
Differential (MAX11600/MAX11601)
8-Channel Single-Ended or 4-Channel Pseudo-
Differential (MAX11602/MAX11603)
12-Channel Single-Ended or 6-Channel Pseudo-
Differential (MAX11604/MAX11605)
Internal FIFO with Channel-Scan ModeLow Power
350µA at 188ksps
110µA at 75ksps
8µA at 10ksps
1µA in Power-Down Mode
Software Configurable Unipolar/BipolarSmall Packages
8-Pin SOT23 (MAX11600/MAX11601)
16-Pin QSOP (MAX11602–MAX11605)
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
Ordering Information/Selector Guide

19-4554; Rev 2; 3/10
PARTTEMP RANGEPIN-PACKAGETUE
(LSB)
INPUT
CHANNELS
INTERNAL
REFERENCE (V)
TOP
MARK
MAX11600EKA+
-40°C to +85°C8 SOT23±244.096AEQH
MAX11601EKA+
-40°C to +85°C8 SOT23±242.048AEQI
MAX11602EEE+
-40°C to +85°C16 QSOP±184.096—
MAX11603EEE+
-40°C to +85°C16 QSOP±182.048—
MAX11604EEE+
-40°C to +85°C16 QSOP±1124.096—
MAX11605EEE+
-40°C to +85°C16 QSOP±1122.048—
+Denotes a lead(Pb)-free/RoHS-compliant package.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
Pin Configurations and Typical Operating Circuit appear
at end of data sheet.
EVALUATION KIT
AVAILABLE
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VDD= 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD= 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF= 2.048V (MAX11601/MAX11603/MAX11605), VREF= 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL=
1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0–AIN11, REF to
GND......................-0.3V to the lower of (VDD+ 0.3V) and +6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin SOT23 (derate 7.1mW/°C above +70°C).............567mW
16-Pin QSOP (derate 8.3mW/°C above +70°C).........666.7mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)

Resolution8Bits
Relative AccuracyINL(Note 2)±1LSB
Differential NonlinearityDNLNo missing codes over temperature±1LSB
Offset Error±1.5LSB
Offset-Error Temperature
Coefficient3ppm/°C
Gain Error(Note 3)±1LSB
Gain Temperature Coefficient±1ppm/°C
MAX11600/MAX11601±0.5±2
MAX11602/MAX11603±0.5±1Total Unadjusted ErrorTUE
MAX11604/MAX11605±0.5±1
LSB
Channel-to-Channel Offset
Matching±0.1LSB
Channel-to-Channel Gain
Matching±0.5LSB
Input Common-Mode Rejection
RatioCMRRPseudo-differential input mode75dB
DYNAMIC PERFORMANCE (fIN(sine wave) = 25kHz, VIN = VREF(P-P), fSAMPLE = 188ksps, RIN = 100Ω)

Signal-to-Noise Plus DistortionSINAD49dB
Total Harmonic DistortionTHDUp to the 5th harmonic-69dB
Spurious-Free Dynamic RangeSFDR69dB
Channel-to-Channel Crosstalk(Note 4)75dB
Full-Power Bandwidth-3dB point2.0MHz
Full-Linear BandwidthSINAD > 49dB200kHz
CONVERSION RATE

Internal clock6.1Conversion Time (Note 5)tCONVExternal clock4.7µs
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD= 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF= 2.048V (MAX11601/MAX11603/MAX11605), VREF= 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL=
1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Internal clock, SCAN[1:0] = 01
(MAX11600/MAX11601)76
SCAN[1:0] = 00 CS[3:0] = 0111
(MAX11602/MAX11603)76
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX11604/MAX11605)77
Throughput RatefSAMPLE
External clock188
ksps
Track/Hold Acquisition Time588ns
Internal Clock Frequency2.25MHz
External clock, fast mode45Aperture DelaytADExternal clock, high-speed mode30ns
ANALOG INPUT (AIN0–AIN11)

Unipolar0VREFInput Voltage Range, Single
Ended and Differential (Note 6)Bipolar±VREF/2V
Input Multiplexer Leakage CurrentOn/off-leakage current, VAIN_ = 0 or VDD,
no clock, fSCL = 0±0.01±1µA
Input CapacitanceCIN18pF
INTERNAL REFERENCE (Note 7)
AX11601/M AX 11603/MAX 116051.9252.0482.171Reference VoltageVREFTA = +25°CM AX11600/M AX 11602/MAX 116043.8504.0964.342V
Reference Temperature
CoefficientTCREF120ppm/°C
Reference Short-Circuit Current10mA
Reference Source Impedance(Note 8)675Ω
EXTERNAL REFERENCE

Reference Input Voltage RangeVREF(Note 9)1.0VDDV
REF Input CurrentIREFfSAMPLE = 188ksps1430µA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)

Input High VoltageVIH0.7 x VDDV
Input Low VoltageVIL0.3 x VDDV
Input HysteresisVHYST0.1 x VDDV
Input CurrentIINVIN = 0 to VDD±10µA
Input CapacitanceCIN15pF
Output Low VoltageVOLISINK = 3mA0.4V
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD= 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF= 2.048V (MAX11601/MAX11603/MAX11605), VREF= 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL=
1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS

MAX11601/MAX11603/MAX116052.73.6Supply Voltage (Note 10)VDDMAX11600/MAX11602/MAX116044.55.5V
Internal REF, external clock350650fSAMPLE =
188kspsExternal REF, external clock250
External REF, external clock110fSAMPLE =
75kspsExternal REF, internal clock150
External REF, external clock8fSAMPLE =
10kspsExternal REF, internal clock10
External REF, external clock2fSAMPLE =
1kspsExternal REF, internal clock2.5
Supply CurrentIDD
Power-down110
Power-Supply Rejection RatioPSRR(Note 11)±0.25±1LSB/V
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)

Serial-Clock FrequencyfSCL400kHz
Bus Fr ee Ti m e Betw een a S TO P ( P )
and a S TART ( S ) C ond i ti ontBUF1.3µs
Hold Time for START ConditiontHD.STA0.6µs
Low Period of the SCL ClocktLOW1.3µs
High Period of the SCL ClocktHIGH0.6µs
Setup Time for a Repeated START
Condition (Sr)tSU.STA0.6µs
Data Hold TimetHD.DAT(Note 12)0150ns
Data Setup TimetSU.DAT100ns
Rise Time of Both SDA and SCL
Signals, ReceivingtR(Note 13)20 + 0.1CB300ns
Fall Time of SDA TransmittingtF(Note 13)20 + 0.1CB300ns
Setup Time for STOP ConditiontSU.STO0.6µs
Capacitive Load for Each Bus LineCB400pF
Pulse Width of Spike SuppressedtSP50ns
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)

Serial-Clock FrequencyfSCLH(Note 14)1.7MHz
Hold Time (Repeated) START
ConditiontHD.STA160ns
Low Period of the SCL ClocktLOW320ns
High Period of the SCL ClocktHIGH120ns
Setup Time for a Repeated START
Condition (Sr)tSU.STA160ns
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), VDD= 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
VREF= 2.048V (MAX11601/MAX11603/MAX11605), VREF= 4.096V (MAX11600/MAX11602/MAX11604). External clock, fSCL=
1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Data Hold TimetHD.DAT(Note 12)0150ns
Data Setup TimetSU.DAT10ns
Rise Time of SCL Signal
(Current Source Enabled)tRCL(Note 13)2080ns
Rise Time of SCL Signal After
Acknowledge BittRCL1(Note 13)20160ns
Fall Time of SCL SignaltFCL(Note 13)2080ns
Rise Time of SDA SignaltRDA(Note 13)20160ns
Fall Time of SDA SignaltFDA(Note 13)20160ns
Setup Time for STOP ConditiontSU, STO160ns
Capacitive Load for Each Bus LineCB400pF
Pulse Width of Spike SuppressedtSP010ns
Note 1:
The MAX11600/MAX11602/MAX11604 are tested at VDD= 5V and the MAX11601/MAX11603/MAX11605 are tested at VDD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3:
Offset nulled.
Note 4:
Ground on channel; sine wave applied to all off channels.
Note 5:
Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6:
The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7:
When AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) is configured to be an inter-
nal reference (SEL[2:1] = 11), decouple AIN_/REF or REF to GND with a 0.01µF capacitor.
Note 8:
The switch connecting the reference buffer to AIN_/REF or REF has a typical on-resistance of 675Ω.
Note 9:
ADC performance is limited by the converter’s noise floor, typically 1.4mVP-P.
Note 10:
Electrical characteristics are guaranteed from VDD(MIN)to VDD(MAX). For operation beyond this range, see the Typical
Operating Characteristics.
Note 11:
Power-supply rejection ratio is measured as:
for the MAX11601/MAX11603/MAX11605, where N is the number of bits.
Power-supply rejection ratio is measured as:
for the MAX11600/MAX11602/MAX11604, where N is the number of bits.
Note 12:
A master device must provide a data hold time for SDA (referred to VILof SCL) to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13:
CB= total capacitance of one bus line in pF. tR, tFDA,and tFmeasured between 0.3VDDand 0.7VDD. The minimum value is
specified at TA = +25°C with CB= 400pF.
Note 14:
fSCLHmust meet the minimum clock low time plus the rise/fall times.VVVFS
REF45245−()[]×VVVFS
REF27227
()−()[]×
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
Typical Operating Characteristics

(VDD= 3.3V (MAX11601/MAX11603/MAX11605), VDD= 5V (MAX11600/MAX11602/MAX11604), fSCL= 1.7MHz, external clock (33% duty
cycle), fSAMPLE= 188ksps, single ended, unipolar, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. VOLTAGE
MAX11600 toc01
VDD (V)
IDD
A) INTERNAL 4.096VREF
B) INTERNAL 2.048VREF
C) EXTERNAL 4.096VREF
D) EXTERNAL 2.048VREFA
SUPPLY CURRENT
vs. TEMPERATURE
MAX11600 toc02
TEMPERATURE (°C)-153560
INTERNAL 4.096VREF
INTERNAL 2.048VREF
EXTERNAL 4.096VREF
EXTERNAL 2.048VREF
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX11600 toc03
VDD (V)
IDD
SDA = SCL = VDD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX11600 toc04
TEMPERATURE (°C)
IDD
SDA = SCL = VDD
VDD = 5V
VDD = 3.3V
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (INTERNAL CLOCK)
MAX11600 toc05
CONVERSION RATE (ksps)
AVERAGE I
A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF
INTERNAL CLOCK MODE
fSCL = 1.7MHz
AVERAGE SUPPLY CURRENT VS.
CONVERSION RATE (EXTERNAL CLOCK)
MAX11600 toc06
CONVERSION RATE (ksps)
AVERAGE I
A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF
EXTERNAL CLOCK MODE
fSCL = 1.7MHz
NORMALIZED 4.096V REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX11600 toc7
REF
NORMALIZED
INTERNAL 4.096V REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11600 toc08
REF
NORMALIZED
INTERNAL 2.048V REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX11600 toc09
REF
NORMALIZED
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

INTERNAL 2.048V REFERENCE VOLTAGE
vs. TEMPERATURE
MAX11600 toc10
TEMPERATURE (°C)
REF
NORMALIZED
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX11600 toc11
DIGITAL OUTPUT CODE
DNL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX11600 toc12
DIGITAL OUTPUT CODE
INL (LSB)
-20100k
FFT PLOT

MAX11600 toc13
FREQUENCY (Hz)
AMPLITUDE (dBc)
40k20k60k80k
fSAMPLE = 188ksps
fIN = 25kHz
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX11600 toc14
VDD (V)
OFFSET ERROR (LSB)
VREF = 2.048V
OFFSET ERROR vs. TEMPERATURE
MAX11600 toc15
OFFSET ERROR (LSB)
VDD = 3.3V
VREF = 2.048V
GAIN ERROR vs. SUPPLY VOLTAGE
MAX11600 toc16
GAIN ERROR (LSB)
VREF = 2.048V
Typical Operating Characteristics (continued)

(VDD= 3.3V (MAX11601/MAX11603/MAX11605), VDD= 5V (MAX11600/MAX11602/MAX11604), fSCL= 1.7MHz, external clock (33% duty
cycle), fSAMPLE= 188ksps, single ended, unipolar, TA= +25°C, unless otherwise noted.)
MAX11600–MAX11605
Detailed Description

The MAX11600–MAX11605 ADCs use successive-
approximation conversion techniques and input T/H cir-
cuitry to capture and convert an analog signal to a
serial 8-bit digital output. The MAX11600/MAX11601
are 4-channel ADCs, the MAX11602/MAX11603 are
8-channel ADCs and the MAX11604/MAX11605 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 3 shows the simplified functional dia-
gram for the MAX11604/MAX11605.
Power Supply

The MAX11600–MAX11605 operate from a single supply
and consume 350µA at sampling rates up to 188ksps.
The MAX11601/MAX11603/MAX11605 feature a 2.048V
internal reference and the MAX11600/MAX11602/
MAX11604 feature a 4.096V internal reference. All
devices can be configured for use with an external refer-
ence from 1V to VDD.
Analog Input and Track/Hold

The MAX11600–MAX11605 analog input architecture
contains an analog input multiplexer (MUX), a T/H
capacitor, T/H switches, a comparator, and a switched
capacitor digital-to-analog converter (DAC) (Figure 4).
In single-ended mode, the analog input multiplexer con-
nects CT/Hto the analog input selected by CS[3:0] (see
the Configuration/Setup Bytes (Write Cycle) section). The
charge on CT/His referenced to GND when converted. In
pseudo-differential mode, the analog input multiplexer
connects CT/H to the positiveanalog input selected by
CS[3:0]. The charge on CT/His referenced to the nega-
tive analog input when converted.
The MAX11600–MAX11605 input configuration is
pseudo-differential in that only the signal at the positive
analog input is sampled with the T/H circuitry. The nega-
tive analog input signal must remain stable within
±0.5 LSB (±0.1 LSB for best results) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from the negative analog input to GND.
See the Single-Ended/Pseudo-Differential Inputsection.
During the acquisition interval, the T/H switches are in
the track position and CT/Hcharges to the analog input
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/Has a sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 8-bit resolution. This action
requires eight conversion clock cycles and is equiva-
lent to transferring a charge of 18pF ✕(VIN+ - VIN-)
from CT/Hto the binary weighted capacitive DAC, form-
ing a digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance below 1.5kΩ
does not significantly degrade sampling accuracy. To
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
PIN
MAX11600
MAX11601
MAX11602
MAX11603
MAX11604
MAX11605
NAMEFUNCTION

1, 2, 312, 11, 1012, 11, 10AIN 0, AIN 1, AIN 29–59–5AIN3–AIN7—4, 3, 2AIN8–AIN10
Analog Inputs——AIN3/REFAnalog Input 3/Reference Input/Output. Selected in the setup register
(see Tables 1 and 6).1—REFReference Input/Output. Selected in the setup register (see Tables 1
and 6).—1AIN11/REFAnalog Input 11/Reference Input/Output. Selected in the setup
register (see Tables 1 and 6).1313SCLClock Input1414SDAData Input/Output1515GNDGround
81616VDDPositive Supply. Bypass to GND with a 0.1µF capacitor.2, 3, 4—N.C.No Connection
Pin Description
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to GND. This input capacitor forms an RC filter
with the source impedance limiting the analog input
bandwidth. For larger source impedances, use a buffer
amplifier to maintain analog input signal integrity.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the ninth falling clock edge
of the address byte (see the Slave Address section).
The T/H circuitry enters hold mode two internal clock
cycles later. A conversion or a series of conversions is
then internally clocked (eight clock cycles per conver-
sion) and the MAX11600–MAX11605 hold SCL low.
When operating in external clock mode, the T/H circuit-
ry enters track mode on the seventh falling edge of a
valid slave address byte. Hold mode is then entered on
the falling edge of the eighth clock cycle. The conver-
sion is performed during the next eight clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of input capacitance. If the
analog input source impedance is high, the acquisition
time lengthens and more time must be allowed
between conversions. The acquisition time (tACQ) is the
minimum time needed for the signal to be acquired. It is
calculated by:
tACQ≥6.25 ✕(RSOURCE+ RIN) ✕CIN
where RSOURCEis the analog input source impedance,
RIN= 2.5kΩ, and CIN= 18pF. tACQis 1/fSCLfor external
clock mode. For internal clock mode, the acquisition
time is two internal clock cycles. To select RSOURCE,
allow 625ns for tACQ in internal clock mode to account
for clock frequency variations.
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

tHD.STA
tSU.DAT
tHIGHtF
tHD.DATtHD.STASrA
SCL
SDA
tSU.STAtLOWtBUF
tSU.STO
tHD.STA
tSU.DAT
tHIGH
tFCL
tHD.DATtHD.STASrA
SCL
SDA
tSU.STAtLOWtBUF
tSU.STO
tRCLtRCL1
HS MODEF/S MODE
a) F/S-MODE I2C SERIAL-INTERFACE TIMING
b) HS-MODE I2C SERIAL-INTERFACE TIMINGtFDAtRDAtRtF
Figure 1. I2C Serial-Interface Timing
VDD
IOL = 3mA
IOH = 0mA
VOUT
400pF
SDA
Figure 2. Load Circuit
MAX11600–MAX11605
Analog Input Bandwidth

The MAX11600–MAX11605 feature input tracking cir-
cuitry with a 2MHz small signal bandwidth. The 2MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and Protection

Internal protection diodes clamp the analog input to
VDDand GND. These diodes allow the analog inputs to
swing from (GND - 0.3V) to (VDD+ 0.3V) without caus-
ing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above VDD. If the analog input exceeds VDDby more
than 50mV, the input current should be limited to 2mA.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

ANALOG
INPUT
MUX
AIN1
AIN11/REF
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX11604)
2.048V (MAX11605)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER AND
12-BYTE RAM
THE MAX11600/MAX11601/MAX11604/MAX11605
USE THE SAME PIN FOR AIN_ AND REF, WHILE THE
MAX11602/MAX11603 USE DIFFERENT PINS.
SEE THE PIN DESCRIPTION SECTION.
REF
T/H8-BIT
ADC
VDD
GND
MAX11604
MAX11605
Figure 3. MAX11604/MAX11605 Simplified Functional Diagram
TRACKHOLD
CT/H
TRACKHOLD
DIFFERENTIAL
SINGLE ENDED
AIN0
AIN1
AIN2
AIN3/REF
GND
ANALOG INPUT MUX
CAPACITIVE
DAC
REF
MAX11600
MAX11601
Figure 4. Equivalent Input Circuit
Single-Ended/Pseudo-Differential Input
The SGL/DIFbit of the configuration byte configures the
MAX11600–MAX11605 analog input circuitry for single-
ended or pseudo-differential inputs (Table 2). In single-
ended mode (SGL/DIF= 1), the digital conversion results
are the difference between the analog input selected by
CS[3:0] and GND (Table 3). In pseudo-differential mode
(SGL/DIF= 0), the digital conversion results are the differ-
ence between the positive and the negative analog inputs
selected by CS[3:0] (Table 4). The negative analog input
signal must remain stable within ±0.5 LSB (±0.1 LSB for
best results) with respect to GND during a conversion.
Unipolar/Bipolar

When operating in pseudo-differential mode, the BIP/
UNIbit of the setup byte (Table 1) selects unipolar or
bipolar operation.Unipolar mode sets the differential
analog input range from zero to VREF. A negative differ-
ential analog input in unipolar mode causes the digital
output code to be zero. Selecting bipolar mode sets the
differential input range to ±VREF/2, with respect to the
negative input. The digital output code is binary in
unipolar mode and two’s complement binary in bipolar
mode (see the Transfer Functions section).
In single-ended mode, the MAX11600–MAX11605
always operate in unipolar mode regardless of the
BIP/UNIsetting, and the analog inputs are internally ref-
erenced to GND with a full-scale input range from zero
to VREF.
Digital Interface

The MAX11600–MAX11605 feature a 2-wire interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate bidirectional communi-
cation between the MAX11600–MAX11605 and the mas-
ter at rates up to 1.7MHz. The MAX11600–MAX11605 are
slaves that transmit and receive data. The master (typical-
ly a microcontroller) initiates data transfer on the bus and
generates SCL to permit that transfer.
SDA and SCL must be pulled high. This is typically
done with pullup resistors (500Ωor greater) (see
Typical Operating Circuit). Series resistors (RS) are
optional. They protect the input architecture of the
MAX11600–MAX11605 from high-voltage spikes on the
bus lines and minimize crosstalk and undershoot of the
bus signals.
Bit Transfer

One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data in or out of the MAX11600–MAX11605. The data
on SDA must remain stable during the high period of
the SCL clock pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). Both SDA and SCL idle high when
the bus is not busy.
START and STOP Conditions

The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA, while
MAX11600–MAX11605
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
BIT 7
(MSB)BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
(LSB)

REGSEL2SEL1SEL0CLKBIP/UNIRSTX
BITNAMEDESCRIPTION
REGRegister bit. 1 = setup byte, 0 = configuration byte (Table 2).SEL2SEL1SEL0
Three bits select the reference voltage and the state of AIN_/REF
(MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) (Table 6).
Default to 000 at power-up.CLK1 = external clock, 0 = internal clock. Defaulted to zero at power-up.BIP/UNI1 = bipolar, 0 = unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section).RST1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.XDon’t care; can be set to 1 or 0.
Table 1. Setup Byte Format
MAX11600–MAX11605
SCL is high (Figure 5). A repeated START condition (Sr)
can be used in place of a STOP condition to leave the
bus active and in its current timing mode (see the HS
Mode section).
Acknowledge Bits

Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX11600–MAX11605 (slave) gener-
ate acknowledge bits. To generate an acknowledge bit,
the receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the clock
pulse (Figure 6). To generate a not acknowledge bit, the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse and leaves
it high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication at a later time.
Slave Address

A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX11600–MAX11605
continuously wait for a START condition followed by
their slave address. When the MAX11600–MAX11605
recognize their slave address, they are ready to accept
or send data. The slave address has been factory pro-
grammed and is always 1100100 for the MAX11600/
MAX11601, 1101101 for MAX11602/MAX11603, and
1100101 for MAX11604/MAX11605 (Figure 7). The least
significant bit (LSB) of the address byte (R/W) deter-
mines whether the master is writing to or reading from
the MAX11600–MAX11605 (R/W= zero selects a write
condition. R/W= 1 selects a read condition). After
receiving the address, the MAX11600–MAX11605
(slave) issue an acknowledge by pulling SDA low for
one clock cycle.
Bus Timing

At power-up, the MAX11600–MAX11605 bus timing
defaults to fast mode (F/S mode), allowing conversion
rates up to 44ksps. The MAX11600–MAX11605 must
operate in high-speed mode (HS mode) to achieve
conversion rates up to 188ksps. Figure 1 shows the bus
timing for the MAX11600–MAX11605 2-wire interface.
HS Mode

At power-up, the MAX11600–MAX11605 bus timing is
set for F/S mode. The master selects HS mode by
addressing all devices on the bus with the HS mode
master code 0000 1XXX (X = don’t care). After success-
fully receiving the HS-mode master code, the
MAX11600–MAX11605issues a not acknowledge,
allowing SDA to be pulled high for one clock cycle
(Figure 8). After the not acknowledge, the
MAX11600–MAX11605 are in HS mode. The master must
then send a repeated START followed by a slave
address to initiate HS mode communication. If the mas-
ter generates a STOP condition, the MAX11600–
MAX11605 return to F/S mode.
Configuration/Setup Bytes (Write Cycle)

Write cycles begin with the master issuing a START
condition followed by 7 address bits (Figure 7) and 1
write bit (R/W= zero). If the address byte is successful-
ly received, the MAX11600–MAX11605 (slave) issue an
acknowledge. The master then writes to the slave. The
slave recognizes the received byte as the setup byte
(Table 1) if the most significant bit (MSB) is 1. If the
MSB is zero, the slave recognizes that byte as the con-
figuration byte (Table 2). The master can write either 1
or 2 bytes to the slave in any order (setup byte then
configuration byte; configuration byte then setup byte;
setup byte only; configuration byte only; Figure 9). If the
slave receives bytes successfully, it issues an acknowl-
edge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS mode, a STOP condition returns the
bus to F/S mode (see the HS Mode section).
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

SCL
SDASr
Figure 5. START and STOP Conditions
SCL
SDANOT ACKNOWLEDGE
ACKNOWLEDGE89
Figure 6. Acknowledge Bits
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