MAX1146BCUP+ ,Multichannel, True-Differential, Serial, 14-Bit ADCsApplicationsPortable Data LoggingData Acquisition Pin Configurations appear at end of data sheet.Me ..
MAX1147BEUP ,Multichannel, True-Differential, Serial, 14-Bit ADCsELECTRICAL CHARACTERISTICS(V = 5V (MAX1146/MAX1148), V = 3.3V (MAX1147/MAX1149), SHDN = V , V = 0, ..
MAX1149BCUP+ ,Multichannel, True-Differential, Serial, 14-Bit ADCsFeaturesThe MAX1146–MAX1149 low-power, 14-bit, multichan-♦ 8-Channel Single-Ended or 4-Channel Diff ..
MAX1149BEUP ,Multichannel, True-Differential, Serial, 14-Bit ADCsApplicationsPortable Data LoggingPin Configurations appear at end of data sheet.Data AcquisitionMed ..
MAX114CAG ,+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1レA Power-DownFeaturesThe MAX114/MAX118 are microprocessor-compatible, ' Single +5V Supply Operation 8-bit, 4-cha ..
MAX114CAG ,+5V, 1Msps, 4 & 8-Channel, 8-Bit ADCs with 1レA Power-DownELECTRICAL CHARACTERISTICS(V = +5V ±5%, REF+ = 5V, REF- = GND, Read Mode (MODE = GND), T = T to T , ..
MAX3485CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3485CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3485CSA+T ,3.3V Powered, 10Mbps and Slew-Rate Limited, True RS-485/RS-422 Transceivers
MAX3485CSA-T ,3.3V Powered, 10Mbps and Slew-Rate Limited, True RS-485/RS-422 Transceivers
MAX3485ECSA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3485ECSA ,3.3V-Powered / 15kV ESD-Protected / 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX1146BCUP+-MAX1149BCUP+
Multichannel, True-Differential, Serial, 14-Bit ADCs
General DescriptionThe MAX1146–MAX1149 low-power, 14-bit, multichan-
nel, analog-to-digital converters (ADCs) feature an
internal track/hold (T/H), voltage reference, and clock.The MAX1146/MAX1148 operate from a single +4.75V
to +5.25V supply, and the MAX1147/MAX1149 operatefrom a single +2.7V to +3.6V supply. All analog inputs
are software configurable for unipolar/bipolar and sin-
gle-ended/differential operation.
The 4-wire serial interface connects directly toSPI™/QSPI™/MICROWIRE™ devices without external
logic. The serial strobe output (SSTRB) allows conve-
nient connection to digital signal processors. TheMAX1146–MAX1149 use an internal clock or an exter-
nal serial-interface clock to perform successive-approx-imation analog-to-digital conversions.
The MAX1146/MAX1148 include an internal +4.096Vreference, while the MAX1147/MAX1149 include an
internal +2.500V reference. All devices accept an exter-nal reference from 1.5V to VDD.
The MAX1146–MAX1149 provide a hardware shutdownand two software power-down modes. Using the soft-
ware power-down modes allows the devices to be pow-ered down between conversions. When powered down,
accessing the serial interface automatically powers up
the devices. The quick turn-on time allows power-downbetween all conversions. This technique reduces sup-
ply current to under 120µA for quick turn-on.
The MAX1146–MAX1149 are available in a 20-pin
TSSOP package.
ApplicationsPortable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Process Control
Features8-Channel Single-Ended or 4-Channel Differential
Inputs (MAX1148/MAX1149)4-Channel Single-Ended or 2-Channel Differential
Inputs (MAX1146/MAX1147)Internal Multiplexer and T/HSingle-Supply Operation
4.75V to 5.25V Supply (MAX1146/MAX1148)
2.7V to 3.6V Supply (MAX1147/MAX1149)Internal Reference
+4.096V (MAX1146/MAX1148)
+2.500V (MAX1147/MAX1149)116ksps Sampling RateLow Power
1.1mA (116ksps)
120µA (10ksps)
12µA (1ksps)
300nA (Power-Down Mode)SPI-/QSPI-/MICROWIRE Compatible20-Pin TSSOP
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Ordering Information/Selector Guide19-3488; Rev 2; 1/07
EVALUATION KIT
AVAILABLE
PARTTEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
INPUT
CHANNELS
INTERNAL
REFERENCE (V)
PKG
CODE
MAX1146BCUP 0°C to +70°C20 TSSOP±24+4.096U20-3
MAX1146BEUP-40°C to +85°C20 TSSOP±24+4.096U20-3
MAX1147BCUP 0°C to +70°C20 TSSOP±24+2.500U20-3
MAX1147BEUP-40°C to +85°C20 TSSOP±24+2.500U20-3
MAX1148BCUP 0°C to +70°C20 TSSOP±28+4.096U20-3
MAX1148BEUP-40°C to +85°C20 TSSOP±28+4.096U20-3
MAX1149BCUP 0°C to +70°C20 TSSOP±28+2.500U20-3
MAX1149BEUP-40°C to +85°C20 TSSOP±28+2.500U20-3
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations appear at end of data sheet.
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 5V (MAX1146/MAX1148), VDD= 3.3V (MAX1147/MAX1149), SHDN= VDD, VCOM= 0, fSCLK= 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ= VDD, CREF= 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA= TMINto TMAX, unless otherwise noted. Typical values are at= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND............................................-0.3V to +6.0V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7, COM to AGND..........................-0.3V to (VDD+ 0.3V)
REF, REFADJ to AGND..............................-0.3V to (VDD+ 0.3V)
Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)
Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
20 TSSOP (derate 10.9mW/°C above +70°C).............879mW
Operating Temperature Ranges
MAX114_ BC_ _..................................................0°C to +70°C
MAX114_ BE_ _...............................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)Resolution14Bits
Relative Accuracy (Note 2)INL±0.7±2LSB
Differential NonlinearityDNLNo missing codes over temperature-1.0±0.5+1.5LSB
Offset Error±10LSB
Offset Temperature Coefficient0.3ppm/°C
Gain Error(Note 3)±20LSB
Gain Temperature Coefficient±0.8ppm/°C
Channel-to-Channel Offset
Matching±1LSB
Channel-to-Channel Gain
Matching±1LSB
DYNAMIC SPECIFICATIONS (1kHz sine-wave input, 2.5VP-P, full-scale analog input, 116ksps, 2.1MHz external clock)Signal-to-Noise Plus Distortion
RatioSINAD7781dB
Total Harmonic DistortionTHDUp to the 5th harmonic-96-88dB
Spurious-Free Dynamic RangeSFDR8498dB
Channel-to-Channel Crosstalk(Note 4)-85dB
Small-Signal BandwidthSSBW-3dB point3.0MHz
Full-Power BandwidthFPBWSINAD > 68dB2.0MHz
CONVERSION RATEExternal clock, 2.1MHz 15 SCLK cycles7.2Conversion Time (Note 5)tCONVInternal clock68µs
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V (MAX1146/MAX1148), VDD= 3.3V (MAX1147/MAX1149), SHDN= VDD, VCOM= 0, fSCLK= 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ= VDD, CREF= 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA= TMINto TMAX, unless otherwise noted. Typical values are at= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS18 clocks/conversion60.3Internal clock mode,
fSCLK = 2.1MHz24 clocks/conversion51.5
18 clocks/conversion116.66Throughput RatefSAMPLEExternal clock mode,
fSCLK = 2.1MHz24 clocks/conversion87.50
ksps
T/H Acquisition TimetACQ1.4µs
Aperture DelaytAD20ns
Aperture JittertAJ<50ps
External clock mode0.12.1Serial Clock FrequencyfSCLKInternal clock mode02.1MHz
Internal Clock Frequency2.1MHz
ANALOG INPUTS (CH0–CH7, COM)Unipolar, COM = 00VREFInput Voltage Range, Single-
Ended and Differential (Note 6)Bipolar, COM = VREF / 2, single-ended±VREF / 2V
Multiplexer Leakage CurrentOn/off-leakage current, VCH_ = 0 to VDD±0.01±1µA
Input Capacitance18pF
INTERNAL REFERENCE (CREF = 2.2µF, CREFADJ = 0.01µF)MAX1147/MAX1149, TA = +25°C2.4802.5002.520REF Output VoltageVREFMAX1146/MAX1148, TA = +25°C4.0764.0964.116V
REF Short-Circuit CurrentIREFSCREF = DGND20mA
MAX114_ BC _ _±30±50VREF Tempco (Note 7)MAX114_ BE _ _±40±60ppm/°C
Load Regulation0 to 0.2mA output load (Note 8)2.0mV
Capacitive Bypass at REF2µF
Capacitive Bypass at REFADJ0.01µF
REFADJ Output Voltage1.250V
REFADJ Input Range±18mV
REFADJ Logic HighPull REFADJ high to disable the internal
bandgap reference and reference buffer
VDD -
0.25VV
MAX1147/MAX11492.000Reference Buffer Voltage GainMAX1146/MAX11483.277V/V
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)(VDD= 5V (MAX1146/MAX1148), VDD= 3.3V (MAX1147/MAX1149), SHDN= VDD, VCOM= 0, fSCLK= 2.1MHz, external clock (50%
duty cycle), 18 clocks/conversion (116ksps), VREFADJ= VDD, CREF= 2.2µF, external +4.096V reference at REF (MAX1146/
MAX1148), external 2.500V reference at REF (MAX1147/MAX1149), TA= TMINto TMAX, unless otherwise noted. Typical values are at= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EXTERNAL REFERENCE AT REFREF Input Voltage RangeVREF1.5VDD +
50mVV
125450REF Input CurrentIREFShutdown0.0110µA
REF Input Resistance68kΩ
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)VDD < 3.6V2.0Input High VoltageVIHVDD > 3.6V3.0V
Input Low VoltageVIL0.8V
Input HysteresisVHYST0.2V
Input LeakageIIN±1µA
Input CapacitanceCIN10pF
DIGITAL OUTPUT (DOUT, SSTRB)Output-Voltage LowVOLISINK = 2mA0.4V
Output-Voltage HighVOHISOURCE = 2mAVDD - 0.5V
Tri-State Leakage CurrentILCS = VDD±10µA
Tri-State Output CapacitanceCOUTCS = VDD10pF
POWER REQUIREMENTSMAX1147/MAX11492.73.6Positive Supply VoltageVDDMAX1146/MAX11484.755.25V
116ksps1.11.5
10ksps0.12External
reference1ksps0.012
Supply Current (Note 8)IDD
Normal
operation, full-
scale inputInternal reference at
116ksps1.92.4mA
Fast power-down120
Full power-down0.3Shutdown Supply Current
(Note 8)
SHDN = DGND0.310
Power-Supply Rejection (Note 9)PSRExternal reference±0.2mV
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Note 1:Tested at VDD= 3.0V (MAX1147/MAX1149) or 5.0V(MAX1146/MAX1148); VCOM= 0; unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Offset nulled. Measured with external reference.
Note 4:“On” channel grounded; full-scale 1kHz sine wave applied to all “off” channels.
Note 5:Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. (See
Figures 8–11.)
Note 6:The common-mode range for the analog inputs is from AGND to VDD.
Note 7:Digital inputs equal VDDor DGND.
Note 8:External load should not change during conversion for specified accuracy.
Note 9:Measured as (VFS x 3.6V) - (VFS x 2.7V) for the MAX1147/MAX1149 and (VFS x 5.25V) - (VFS x 4.75V) for the
MAX1146/MAX1148. VDD= 3.6V to 2.7V for MAX1147/MAX1149 and VDD= 5.25V to 4.75V for the MAX1146/MAX1148.
TIMING CHARACTERISTICS(VDD= 4.75V to 5.25V (MAX1146/MAX1148), VDD= 2.7V to 3.6V (MAX1147/MAX1149), SHDN= VDD, VCOM= 0, fSCLK= 2.1MHz,
external clock (50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ= VDD, CREF= 2.2µF, external +4.096V reference at REF
for the MAX1146/MAX1148, external 2.500V reference at REF for the MAX1147/MAX1149, TA= TMINto TMAX, unless otherwise noted.
Typical values are at TA= +25°C.) (Figures 1, 2, and 3)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSDIN to SCLK Setup TimetDS50ns
DIN to SCLK Hold TimetDH0ns
SCLK Fall to Output Data ValidtDOVCLOAD = 50pF1080ns
CS Fall to DOUT EnabletDOECLOAD = 50pF120ns
CS Rise to DOUT DisabletDODCLOAD = 50pF120ns
SHDN Rise CS Fall to SCLK Rise
TimetCSS50ns
SHDN Rise CS Fall to SCLK Rise
Hold TimetCSH50ns
External clock mode0.12.1SCLK Clock FrequencyfSCLKInternal clock mode02.1MHz
SCLK Pulse-Width HightCHInternal clock mode100ns
SCLK Pulse-Width LowtCLInternal clock mode100ns
CS Fall to SSTRB Output EnabletSTEExternal clock mode only120ns
CS Rise to SSTRB Output DisabletSTDExternal clock mode only120ns
SSTRB Rise to SCLK RisetSCKInternal clock mode only0ns
SCLK Fall to SSTRB EdgetSCST80ns
CS Pulse WidthtCSW100ns
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCsVDD
DGND
DOUT
6kΩ
CLOAD
50pF
DGND
6kΩ
DOUT
CLOAD
50pF
DGND
a) HIGH-Z TO VOH AND VOL TO VOHb) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for Enable Time
VDD
DGND
DOUT
6kΩ
CLOAD
50pF
DGND
6kΩ
DOUT
CLOAD
50pF
DGND
a) VOH TO HIGH-Zb) VOL TO HIGH-Z
Figure 2. Load Circuits for Disable Time
HIGH-Z
SCLK
DINSTARTSEL2SEL1SEL0PD1PD09
tACQ
SSTRB
(INTERNAL CLOCK MODE)
SSTRB
(EXTERNAL CLOCK MODE)
DOUTD13D12D11D10HIGH-Z
tCSH
tCH
tCL
tCSS
tDStDH
fSCLK
tDOE
tSTE
tDOVD1D0
tDOD
tSTD
tCSW
HIGH-Z
HIGH-Z
tSCK
tSCST
tSCST
SGL/DIFUNI/BIP
Figure 3. Detailed Operating Characteristics
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
INL vs. OUTPUT CODEMAX1146 toc01
OUTPUT CODE
INL (LSB)
DNL vs. OUTPUT CODE
MAX1146 toc02
OUTPUT CODE
DNL (LSB)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
MAX1146 toc03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
INTERNAL REFERENCE
EXTERNAL REFERENCE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)MAX1146 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
INTERNAL REFERENCE
EXTERNAL REFERENCE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)MAX1146 toc05
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (
SUPPLY CURRENT
vs. CONVERSION RATE
MAX1146 toc07
CONVERSION RATE (ksps)
SUPPLY CURRENT (
FAST POWER-DOWN
FULL
POWER-DOWN
SUPPLY CURRENT vs. TEMPERATUREMAX1146 toc08
TEMPERATURE (°C)
SUPPLY CURRENT (mA)3510-15
MAX1146/MAX1148 INTERNAL REFERENCE
MAX1147/MAX1149 INTERNAL REFERENCE
MAX1146/MAX1148 EXTERNAL REFERENCE
MAX1147/MAX1149 EXTERNAL REFERENCE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATUREMAX1146 toc09
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT (3510-15
MAX1146/MAX1148
MAX1147/MAX1149
Typical Operating Characteristics(VDD= +5.0V (MAX1146/MAX1148), VDD= +3.3V (MAX1147/MAX1149), SHDN= VDD, VCOM= 0, fSCLK= 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ= VDD, external +4.096V reference at REF (MAX1146/MAX1148), exter-
nal +2.500V reference at REF (MAX1147/MAX1149), CREF= 2.2µF, CLOAD= 50pF, TA= +25°C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)MAX1146 toc06
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (
4.755.25
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)MAX1146 toc10
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)
MAX1146 toc11
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE vs. TEMPERATURE
(MAX1146/MAX1148)
MAX1146 toc12
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)3510-15
REFERENCE VOLTAGE vs. TEMPERATURE
(MAX1147/MAX1149)
MAX1146 toc13
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)3510-15
REFERENCE BUFFER POWER-UP DELAY
vs. TIME IN SHUTDOWN
MAX1146 toc14
TIME IN SHUTDOWN (s)
DELAY (0.10.01
CREF = 4.7μF
CREFADJ = 0.01μF
FFT PLOTMAX1146 toc15
FREQUENCY (Hz)
AMPLITUDE (dB)
fIN = 1kHz
fSAMPLE = 116ksps
VDD = 5V/3V
EFFECTIVE NUMBER OF BITS
vs. FREQUENCYMAX1146 toc16
FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS37281910
Typical Operating Characteristics (continued)
(VDD= +5.0V (MAX1146/MAX1148), VDD= +3.3V (MAX1147/MAX1149), SHDN= VDD, VCOM= 0, fSCLK= 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ= VDD, external +4.096V reference at REF (MAX1146/MAX1148), exter-
nal +2.500V reference at REF (MAX1147/MAX1149), CREF= 2.2µF, CLOAD= 50pF, TA= +25°C, unless otherwise noted.)
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
GAIN ERROR vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)MAX1146 toc19
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
MAX1146 toc20
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc21
SUPPLY VOLTAGE (V)
GAIN MATCHING (LSB)
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
XMAX1146 toc22
SUPPLY VOLTAGE (V)
GAIN MATCHING (LSB)
Typical Operating Characteristics (continued)
(VDD= +5.0V (MAX1146/MAX1148), VDD= +3.3V (MAX1147/MAX1149), SHDN= VDD, VCOM= 0, fSCLK= 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ= VDD, external +4.096V reference at REF (MAX1146/MAX1148), exter-
nal +2.500V reference at REF (MAX1147/MAX1149), CREF= 2.2µF, CLOAD= 50pF, TA= +25°C, unless otherwise noted.)
OFFSET ERROR vs. SUPPLY VOLTAGE
(MAX1147/MAX1149)MAX1146 toc17
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. SUPPLY VOLTAGE
(MAX1146/MAX1148)
MAX1146 toc18
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
4.755.25
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
OFFSET ERROR vs. TEMPERATUREMAX1146 toc28
TEMPERATURE (°C)
OFFSET ERROR (LSB)35-1510
Typical Operating Characteristics (continued)
(VDD= +5.0V (MAX1146/MAX1148), VDD= +3.3V (MAX1147/MAX1149), SHDN= VDD, VCOM= 0, fSCLK= 2.1MHz, external clock
(50% duty cycle), 18 clocks/conversion (116ksps), VREFADJ= VDD, external +4.096V reference at REF (MAX1146/MAX1148), exter-
nal +2.500V reference at REF (MAX1147/MAX1149), CREF= 2.2µF, CLOAD= 50pF, TA= +25°C, unless otherwise noted.)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATUREMAX1146 toc26
TEMPERATURE (°C)
OFFSET MATCHING (LSB)35-1510
GAIN ERROR vs. TEMPERATURE
MAX1146 toc27
TEMPERATURE (°C)
GAIN ERROR (LSB)35-1510
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE (MAX1147/MAX1149)
MAX1146 toc24
SUPPLY VOLTAGE (V)
OFFSET MATCHING (LSB)
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE (MAX1146/MAX1148)
MAX1146 toc25
SUPPLY VOLTAGE (V)
OFFSET MATCHING (LSB)
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
MAX1146 toc23
TEMPERATURE (°C)
GAIN MATCHING (LSB)35-1510
-4085
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
PIN
MAX1148
MAX1149
MAX1146
MAX1147
NAMEFUNCTION1CH02CH13CH24CH3—CH4—CH5—CH6—CH7
Analog Inputs9COMCommon Input. Negative analog input in single-ended mode. COM sets zero-code voltage in
unipolar and bipolar mode.10SHDNActive-Low Shutdown Input. Pulling SHDN low shuts down the device reducing supply current
to 0.2µA. Driving shutdown high enables the devices.11REF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital
conversion. In internal reference mode, the MAX1146/MAX1148 VREF is +4.096V, and the
MAX1147/MAX1149 VREF is +2.500V.12REFADJ
Bandgap Reference Output and Reference Buffer Input. Bypass to AGND with a 0.01µF
capacitor. Connect REFADJ to VDD to disable the internal bandgap reference and reference-
buffer amplifier.13AGNDAnalog Ground14DGNDDigital Ground15DOUTSerial Data Output. Data is clocked out at the falling edge of SCLK when CS is low. DOUT is
high impedance when CS is high.16SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC conversion
begins, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for two clock periods before the MSB decision. SSTRB is high impedance when CS is high
(external clock mode).17DINSerial Data Input. Data is clocked in at the rising edge of SCLK when CS is low. DIN is high
impedance when CS is high.18CSActive-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.19SCLKSerial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed
in external clock mode. (Duty cycle must be 40% to 60%.)20VDDPositive Supply Voltage. Bypass to AGND with a 0.1µF capacitor.5–8N.C.No Connection. Not internally connected.
Pin Description
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Detailed DescriptionThe MAX1146–MAX1149 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 14-bit digital
output. A flexible serial interface provides easy inter-
face to microprocessors (µPs). Figure 4 shows the typi-
cal application circuit and Figure 5 shows a functional
diagram of the MAX1148/MAX1149.
True-Differential Analog Input and
Track/HoldThe MAX1146–MAX1149 analog input architecture con-
tains an analog input multiplexer (MUX), two T/H
capacitors, T/H switches, a comparator, and two
switched capacitor digital-to-analog converters (DACs)
(Figure 6).
In single-ended mode, the analog input MUX connects
IN+ to the selected input channel and IN- to COM. In
differential mode, IN+ and IN- are connected to the
selected analog input pairs such as CH0/CH1. Select
the analog input channels according to Tables 1–5.
The analog input multiplexer switches to the selected
channel on the control byte’s fifth SCLK falling edge. At
this time, the T/H switches are in the track position and
CT/H+and CT/H-track the analog input signal. At the
control byte’s eighth SCLK falling edge, the MUX opens
and the T/H switches move to the hold position, retain-
ing the charge on CT/H+and CT/H-as a sample of the
input signal. See Figures 8–11 for input MUX and T/H
switch positioning.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator-input voltage to
0 within the limits of 14-bit resolution. This action
requires 15 conversion clock cycles and is equivalent
to transferring a charge of 18pF ×(VIN+- VIN-) from
CT/H+and CT/H-to the binary-weighted capacitive
DAC, forming a digital representation of the analog
input signal.
After conversion, the T/H switches move from the hold
position to the track position and the MUX switches
back to the last specified position. In internal clock
mode, the conversion is complete on the rising edge of
SSTRB. In external clock mode, the conversion is com-
plete on the eighteenth SCLK falling edge.
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, the acquisi-
tion time lengthens. The MAX1146–MAX1149 provide
three SCLK cycles (tACQ) in which the T/H capacitance
must acquire a charge representing the input signal,
typically the last three SCLKs of the control word. The
input source impedance (RSOURCE) should be mini-
mized to allow the T/H capacitance to charge within
this allotted time.
tACQ= 11.5 ×(RSOURCE+ RIN) ×CIN
where RSOURCEis the analog input source impedance,
RIN is 2.6kΩ(which is the sum of the analog input MUX
and T/H switch resistances), and CINis 18pF (which is
the sum of CT/H+, CT/H-, and input stray capacitance).
To minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to AGND. This input capacitor reduces the input’s
AC impedance but forms an RC filter with the source
impedance, limiting the analog input bandwidth. For
larger source impedance, use a buffer amplifier such as
the MAX4430 to maintain analog input signal integrity.
MAX1148
MAX1149
SCLK
DIN
DOUT
SSTRB
VDD
VDD
VDD
VSS
REFADJCOM
ANALOG
INPUTSCH4
CH5
CH6
CH7
CH0
CH1
CH2
CH3
REF
AGNDDGND0.01μF
0.1μF4.7μF
2.2μF
I/O
I/O
I/O
SCK
MOSI
MISO
10Ω
SHDN
Figure 4. Typical Application Circuit
MAX1149
ANALOG
INPUT
MUX
CONTROL
LOGIC
INTERNAL
CLOCK
INPUT
SHIFT
REGISTER
OUTPUT
SHIFT
REGISTER
+1.250V
BANDGAP
REFERENCE
T/H
DOUT
SSTRB
VDD
AGND
SCLK
DIN
COM
REFADJ
REF
CH6
CH7
CH4
CH5
CH1
CH2
CH3
CH0
DGND
SAR
ADC
REF
CLOCKOUT
20kΩ
AV = 2.0V/V
SHDN
Figure 5. Functional Diagram
MAX1146–MAX1149
Multichannel, True-Differential,
Serial, 14-Bit ADCs
Input BandwidthThe MAX1146–MAX1149 feature input tracking circuitry
with a 3.0MHz small-signal bandwidth. The 3.0MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input ProtectionInternal protection diodes clamp the analog input to
VDDand AGND. These diodes allow the analog inputs
to swing from (AGND - 0.3V) to (VDD+ 0.3V) without
causing damage to the device. For accurate conver-
sions, the inputs must not go more than 50mV below
AGND or above VDD.
Note:If the analog input exceeds 50mV beyond the sup-
ply rails, limit the current to 2mA.
Quick LookUse the circuit of Figure 7 to quickly evaluate the
MAX1148/MAX1149. The MAX1148/MAX1149 require a
control byte to be written to DIN using SCLK before
each conversion. Connecting DIN to VDDand clocking
SCLK feeds in a control byte of $FF HEX (see Table 1).
Trigger single-ended unipolar conversions on CH7 in
external clock mode without powering down between
conversions. In external clock mode, the SSTRB output
pulses high for two clock periods before the MSB of the
14-bit conversion result is shifted out of DOUT. Varying
the analog input to CH7 alters the sequence of bits
from DOUT. A total of 18 clock cycles are required per
conversion (Figure 10). All transitions of the SSTRB and
DOUT outputs occur on the falling edge of SCLK.
MAX1148
MAX1149
CH0
ANALOG INPUT MUX
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
IN+
IN-
TRACK
HOLD
CT/H+
CT/H-
TRACK
TRACK
REF
14-BIT
CAPACITIVE
DAC
14-BIT
CAPACITIVE
DAC
REF
HOLD
HOLD
Figure 6. Equivalent Input Circuit
