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MAX1137EUA+MAXIMN/a5000avai2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
MAX1139EEE-T |MAX1139EEETMAXIMN/a12006avai2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs


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MAX3483EEPA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EESA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EESA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EESA ,3.3V-Powered, 【15kV ESD-Protected, 12Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483EESA+ ,3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483ESA ,3.3V-Powered, 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers


MAX1137EUA+-MAX1139EEE-T
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Hand-Held Portable
Applications
Medical Instruments
Battery-Powered Test
Equipment
Solar-Powered Remote
Systems
Received-Signal-Strength
Indicators
System Supervision
General Description

The MAX1136–MAX1139 low-power, 10-bit, multichannel
analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an 2C-compatible 2-wire serial interface. These devices
operate from a single supply of 2.7V to 3.6V (MAX1137/
MAX1139) or 4.5V to 5.5V (MAX1136/MAX1138) and
require only 670µA at the maximum sampling rate of
94.4ksps. Supply current falls below 230µA for sampling
rates under 46ksps. AutoShutdown™ powers down the
devices between conversions, reducing supply current to
less than 1µA at low throughput rates. The
MAX1136/MAX1137 have four analog input channels
each, while the MAX1138/MAX1139 have 12 analog input
channels each. The fully differential analog inputs are
software configurable for unipolar or bipolar, and single
ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX1137/
MAX1139 feature a 2.048V internal reference and the
MAX1136/MAX1138 feature a 4.096V internal reference.
The MAX1136/MAX1137 are available in an 8-pin µMAX®
package. The MAX1138/MAX1139 are available in a
16-pin QSOP package. The MAX1136–MAX1139 are
guaranteed over the extended temperature range
(-40°C to +85°C). For pin-compatible 12-bit parts, refer to
the MAX1236–MAX1239 data sheet. For pin-compatible
8-bit parts, refer to the MAX1036–MAX1039 data sheet.
Applications
Features
High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
Single-Supply
2.7V to 3.6V (MAX1137/MAX1139)
4.5V to 5.5V (MAX1136/MAX1138)
Internal Reference
2.048V (MAX1137/MAX1139)
4.096V (MAX1136/MAX1138)
External Reference: 1V to VDDInternal Clock4-Channel Single-Ended or 2-Channel Fully
Differential (MAX1136/MAX1137)
12-Channel Single-Ended or 6-Channel Fully
Differential (MAX1138/MAX1139)
Internal FIFO with Channel-Scan ModeLow Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
Software-Configurable Unipolar/BipolarSmall Packages
8-Pin µMAX (MAX1136/MAX1137)
16-Pin QSOP (MAX1138/MAX1139)
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Ordering Information

19-2334; Rev 6; 3/10
Pin Configurations and Typical Operating Circuit appear at
PARTTEMP RANGEPIN-
PACKAGE2C SLAVE
ADDRESS
MAX1136EUA+
-40°C to +85°C8 µMAX0110100
MAX1137EUA+
-40°C to +85°C8 µMAX0110100
MAX1138EEE+
-40°C to +85°C16 QSOP0110101
MAX1139EEE+
-40°C to +85°C16 QSOP0110101
Selector Guide
PARTINPUT
CHANNELS
INTERNAL
REFERENCE
(V)
SUPPLY
VOLTAGE
(V)
INL
(LSB)

MAX113644.0964.5 to 5.5±1
MAX113742.0482.7 to 3.6±1
MAX1138124.0964.5 to 5.5±1
MAX1139122.0482.7 to 3.6±1
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
+Denotes a lead(Pb)-free/RoHS-compliant package.
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS

(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C. See
Tables 1–5 for programming notation.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0–AIN11,
REF to GND............-0.3V to the lower of (VDD+ 0.3V) and 6V
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current Into Any Pin.........................................±50mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 5.9mW/°C above +70°C)..........470.6mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)

Resolution10Bits
Relative AccuracyINL(Note 2)±1LSB
Differential NonlinearityDNLNo missing codes over temperature±1LSB
Offset Error±1LSB
Offset-Error Temperature
CoefficientRelative to FSR0.3ppm/°C
Gain Error(Note 3)±1LSB
Gain-Temperature CoefficientRelative to FSR0.3ppm/°C
Channel-to-Channel Offset
Matching±0.1LSB
Channel-to-Channel Gain
Matching±0.1LSB
DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps)

Signal-to-Noise Plus DistortionSINAD60dB
Total Harmonic DistortionTHDUp to the 5th harmonic-70dB
Spurious Free Dynamic RangeSFDR70dB
Full-Power BandwidthSINAD > 57dB3.0MHz
Full-Linear Bandwidth-3dB point5.0MHz
CONVERSION RATE

Internal clock6.8Conversion Time (Note 4)tCONVExternal clock10.6µs
Internal clock, SCAN[1:0] = 0153
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX1138/MAX1139)53Throughput RatefSAMPLE
External clock94.4
ksps
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C. See
Tables 1–5 for programming notation.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Internal Clock Frequency2.8MHz
External clock, fast mode60Aperture Delay (Note 5)tADExternal clock, high-speed mode30ns
ANALOG INPUT (AIN0–AIN11)

Unipolar0VREFInput-Voltage Range, Single-
Ended and Differential (Note 6)Bipolar0±VREF/2V
Input Multiplexer Leakage CurrentON/OFF leakage current, VAIN_ = 0 or VDD±0.01±1µA
Input CapacitanceCIN22pF
INTERNAL REFERENCE (Note 7)

MAX1137/MAX11391.9682.0482.128Reference VoltageVREFTA = +25°CMAX1136/MAX11383.9394.0964.256V
Reference-Voltage Temperature
CoefficientTCVREF25ppm/°C
REF Short-Circuit Current2mA
REF Source Impedance1.5kΩ
EXTERNAL REFERENCE

REF Input-Voltage RangeVREF(Note 8)1VDDV
REF Input CurrentIREFfSAMPLE = 94.4ksps40µA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)

Input High VoltageVIH0.7 ✕ VDDV
Input Low VoltageVIL0.3 ✕ VDDV
Input HysteresisVHYST0.1 ✕ VDDV
Input CurrentIINVIN 0 to VDD±10µA
Input CapacitanceCIN15pF
Output Low VoltageVOLISINK = 3mA0.4V
POWER REQUIREMENTS

MAX1137/MAX11392.73.6Supply VoltageVDDMAX1136/MAX11384.55.5V
Internal reference9001150fSAMPLE = 94.4ksps
external clockExternal reference670900
Internal reference530fSAMPLE = 40ksps
internal clockExternal reference230
Internal reference380fSAMPLE = 10ksps
internal clockExternal reference60
Internal reference330fSAMPLE =1ksps
internal clockExternal reference6
Supply CurrentIDD
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)

(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C. See
Tables 1–5 for programming notation.)
TIMING CHARACTERISTICS (Figure 1)

(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C. See
Tables 1–5 for programming notation.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS

Power-Supply Rejection RatioPSRRFull-scale input (Note 9)±0.01±0.5LSB/V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
TIMING CHARACTERISTICS FOR FAST MODE

Serial Clock FrequencyfSCL400kHz
Bus Free Time Between a
STOP (P) and a
START (S) Condition
tBUF1.3µs
Hold Time for START (S) ConditiontHD, STA0.6µs
Low Period of the SCL ClocktLOW1.3µs
High Period of the SCL ClocktHIGH0.6µs
Setup Time for a Repeated START
Condition (Sr)tSU, STA0.6µs
Data Hold TimetHD, DAT(Note 10)0900ns
Data Setup TimetSU, DAT100ns
Rise Time of Both SDA and SCL
Signals, ReceivingtRMeasured from 0.3VDD to 0.7VDD20 + 0.1CB300ns
Fall Time of SDA TransmittingtFMeasured from 0.3VDD to 0.7VDD (Note 11)20 + 0.1CB300ns
Setup Time for STOP (P) ConditiontSU, STO0.6µs
Capacitive Load for Each Bus LineCB400pF
Pulse Width of Spike SuppressedtSP50ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 12)

Serial Clock FrequencyfSCLH(Note 13)1.7MHz
Hold Time, Repeated START
Condition (Sr)tHD, STA160ns
Low Period of the SCL ClocktLOW320ns
High Period of the SCL ClocktHIGH120ns
Setup Time for a Repeated START
Condition (Sr)tSU, STA160ns
Data Hold TimetHD, DAT(Note 10)0150ns
Data Setup TimetSU, DAT10ns
Note 1:For DC accuracy, the MAX1136/MAX1138 are tested at VDD= 5V and the MAX1137/MAX1139 are tested at VDD= 3V. All
devices are configured for unipolar, single-ended inputs.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3:
Offset nulled.
Note 4:
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5:
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6:
The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7:
When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩseries resistor (see the Typical Operating Circuit).
Note 8:
ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 9:
Measured as for the MAX1137/MAX1139
and for the MAX1136/MAX1138
Note 10:
A master device must provide a data hold time for SDA (referred to VILof SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 11:
The minimum value is specified at +25°C.
Note 12:
CB= total capacitance of one bus line in pF.
Note 13:
fSCLmust meet the minimum clock low time plus the rise/fall times.VVVFS
REF)(.).)452145−
[]×⎡⎢⎤⎥VVVFS
REF)(.).)272127−
[]×⎡⎢⎤⎥
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)

(VDD= 2.7V to 3.6V (MAX1137/MAX1139), VDD= 4.5V to 5.5V (MAX1136/MAX1138), VREF= 2.048V (MAX1137/MAX1139), VREF=
4.096V (MAX1136/MAX1138), fSCL= 1.7MHz, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C. See
Tables 1–5 for programming notation.).)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS

Rise Time of SCL Signal
(Current Source Enabled)tRCLMeasured from 0.3VDD to 0.7VDD2080ns
Rise Time of SCL Signal after
Acknowledge BittRCL1Measured from 0.3VDD to 0.7VDD20160ns
Fall Time of SCL SignaltFCLMeasured from 0.3VDD to 0.7VDD2080ns
Rise Time of SDA SignaltRDAMeasured from 0.3VDD to 0.7VDD20160ns
Fall Time of SDA SignaltFDAMeasured from 0.3VDD to 0.7VDD (Note 11)20160ns
Setup Time for STOP (P) ConditiontSU, STO160ns
Capacitive Load for Each Bus LineCB400pF
Pulse Width of Spike SuppressedtSP(Notes 10 and 13)010ns
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Typical Operating Characteristics

(VDD= 3.3V (MAX1137/MAX1139), VDD= 5V (MAX1136/MAX1138), fSCL= 1.7MHz, external clock, fSAMPLE= 94.4ksps, single-
ended, unipolar, TA= +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX1136 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX1136 toc02
DIGITAL OUTPUT CODE
INL (LSB)
-2010k20k30k40k50k
FFT PLOT

MAX1136 toc03
FREQUENCY (Hz)
AMPLITUDE (dBc)
fSAMPLE = 94.4ksps
fIN = 10kHz
SUPPLY CURRENT vs. TEMPERATURE
MAX1136 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (
INTERNAL REFERENCEMAX1138/1136
MAX1139/1137
MAX1138/1136
MAX1139/1137
INTERNAL REFERENCE
EXTERNAL REFERENCE
EXTERNAL REFERENCE
SETUP BYTE
EXT REF: 10111011
INT REF: 11011011
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1136 toc05
INPUT VOLTAGE (V)
IDD
SDA = SCL = VDD
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1136 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (
MAX1138
MAX1139
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (EXTERNAL CLOCK)
MAX1136 toc07
AVERAGE I
A) INTERNAL REFERENCE ALWAYS ON
B) EXTERNAL REFERENCE
MAX1138
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1136
toc08
REF
NORMALIZED
MAX1138
MAX1139
NORMALIZED TO REFERENCE VALUE
AT +25°C
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1136 toc09
REF
NORMALIZED
MAX1138/MAX1136,
NORMALIZED TO
REFERENCE VALUE AT
VDD = 5V
MAX1139/MAX1137,
NORMALIZED TO
REFERENCE VALUE AT
VDD = 3.3V
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Typical Operating Characteristics (continued)

(VDD= 3.3V (MAX1137/MAX1139), VDD= 5V (MAX1136/MAX1138), fSCL= 1.7MHz, external clock, fSAMPLE= 94.4ksps, single-
ended, unipolar, TA= +25°C, unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
MAX1136 toc10
TEMPERATURE (°C)
OFFSET ERROR (LSB)
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1136 toc11
VDD (V)
OFFSET ERROR (LSB)
GAIN ERROR vs. TEMPERATURE
MAX1136 toc12
TEMPERATURE (°C)
GAIN ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1136 toc13
VDD (V)
GAIN ERROR (LSB)
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Pin Description
PIN
MAX1136
MAX1137
MAX1138
MAX1139
NAMEFUNCTION

1, 2, 31, 2, 3AIN0–AIN24–8AIN3–AIN716, 15, 14AIN8–AIN10
Analog Inputs—AIN3/REFAnalog Input 3/Reference Input or Output. Selected in the Setup Register.
(See Tables 1 and 6.)13AIN11/REFAnalog Input 11/Reference Input or Output. Selected in the Setup Register.
(See Tables 1 and 6.)9SCLClock Input10SDAData Input/Output11GNDGround
812VDDPositive Supply. Bypass to GND with a 0.1µF capacitor.
tHD.STA
tSU.DAT
tHIGHtF
tHD.DATtHD.STASrA
SCL
SDA
tSU.STAtLOWtBUF
tSU.STO
tHD.STA
tSU.DAT
tHIGH
tFCL
tHD.DATtHD.STASrA
SCL
SDA
tSU.STAtLOWtBUF
tSU.STO
tRCLtRCL1
HS-MODEF/S-MODE
A. F/S-MODE 2-WIRE SERIAL INTERFACE TIMING
B. HS-MODE 2-WIRE SERIAL INTERFACE TIMING
tFDAtRDAtRtF
Detailed Description
The MAX1136–MAX1139 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX1136/MAX1137 are
4-channel ADCs, and the MAX1138/MAX1139 are
12-channel ADCs. These devices feature a high-speed
1.7MHz. Figure 2 shows the simplified internal structure
for the MAX1138/MAX1139.
Power Supply

The MAX1136–MAX1139 operates from a single supply
and consumes 670µA (typ) at sampling rates up to
94.4ksps. The MAX1137/MAX1139 feature a 2.048V
internal reference and the MAX1136/MAX1138 feature
a 4.096V internal reference. All devices can be config-
ured for use with an external reference from 1V to VDD.
Analog Input and Track/Hold

The MAX1136–MAX1139 analog-input architecture con-
tains an analog-input multiplexer (mux), a fully differen-
tial track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode the analog-input multiplexer con-
nects CT/Hbetween the analog input selected by
CS[3:0] (see the Configuration/Setup Bytes section)
and GND (Table 3). In differential mode, the analog-
input multiplexer connects CT/Hto the “+” and “-” ana-
log inputs selected by CS[3:0] (Table 4).
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs

ANALOG
INPUT
MUX
AIN1
AIN11/REF
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN0
SCL
SDA
INPUT SHIFT REGISTER
SETUP REGISTER
CONFIGURATION REGISTER
CONTROL
LOGIC
REFERENCE
4.096V (MAX1138)
2.048V (MAX1139)
INTERNAL
OSCILLATOR
OUTPUT SHIFT
REGISTER
AND RAM
REF
T/H10-BIT
ADC
VDD
GND
MAX1138
MAX1139
Figure 2. MAX1138/MAX1139 Functional Diagram
VDD
IOL
IOH
VOUT
400pF
SDA
Figure 3. Load Circuit
MAX1136–MAX1139
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on CT/Has a stable sample of the input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of 10-bit resolution. This action
requires 10 conversion clock cycles and is equivalent
to transferring a charge of 11pF ✕(VIN+- VIN-) from
CT/Hto the binary weighted capacitive DAC, forming a
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source impedances,
connect a 100pF capacitor from the analog input to GND.
This input capacitor forms an RC filter with the source
impedance limiting the analog-input bandwidth. For larg-
er source impedances, use a buffer amplifier to maintain
analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte (see the Slave Address section). The
T/H circuitry enters hold mode on the falling clock edge of
the acknowledge bit of the address byte (the ninth clock
pulse). A conversion, or series of conversions, are then
internally clocked and the MAX1136–MAX1139 holds
SCL low. With external clock mode, the T/H circuitry
enters track mode after a valid address on the rising
edge of the clock during the read (R/W= 1) bit. Hold
mode is then entered on the rising edge of the second
clock pulse during the shifting out of the first byte of the
result. The conversion is performed during the next 10
clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (tACQ) is the minimum time needed for the signal
to be acquired. It is calculated by:
tACQ≥9 ✕(RSOURCE+ RIN) ✕CIN
where RSOURCEis the analog-input source impedance,
RIN= 2.5kΩ, and CIN= 22pF. tACQis 1.5/fSCLfor internal
clock mode and tACQ= 2/fSCLfor external clock mode.
Analog Input Bandwidth

The MAX1136–MAX1139 feature input-tracking circuitry
with a 5MHz small-signal bandwidth. The 5MHz input
bandwidth makes it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and Protection

Internal protection diodes clamp the analog input to
VDDand GND. These diodes allow the analog inputs to
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs

TRACK
TRACK
HOLD
CT/H
CT/H
TRACK
TRACK
HOLD
AIN0
AIN1
AIN2
AIN3/REF
GND
ANALOG INPUT MUX
CAPACITIVE
DAC
REF
CAPACITIVE
DAC
REFMAX1136
MAX1137
HOLD
HOLD
TRACK
HOLD
VDD/2
swing from (GND - 0.3V) to (VDD+ 0.3V) without caus-
ing damage to the device. For accurate conversions
the inputs must not go more than 50mV below GND or
above VDD.
Single-Ended/Differential Input

The SGL/DIFof the configuration byte configures the
MAX1136–MAX1139 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF= 1), the digital conversion results are the
difference between the analog input selected by CS[3:0]
and GND (Table 3). In differential mode (SGL/ DIF= 0) the
digital conversion results are the difference between the
“+” and the “-” analog inputs selected by CS[3:0] (Table 4).
Unipolar/Bipolar

When operating in differential mode, the BIP/UNIbit of
the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode will cause the digital output
code to be zero. Selecting bipolar mode sets the differ-
ential input range to ±VREF/2. The digital output code is
binary in unipolar mode and two’s complement in bipo-
lar mode, see the Transfer Functions section.
In single-ended mode the MAX1136–MAX1139 will
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface

The MAX1136–MAX1139 feature a 2-wire interface con-
sisting of a serial data line (SDA) and serial clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX1136–MAX1139 and the master at
rates up to 1.7MHz. The MAX1136–MAX1139 are slaves
that transfer and receive data. The master (typically a
microcontroller) initiates data transfer on the bus and
generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ωor greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional.
They protect the input architecture of the MAX1136–
MAX1139 from high voltage spikes on the bus lines, min-
imize crosstalk, and undershoot of the bus signals.
Bit Transfer

One data bit is transferred during each SCL clock
cycle. A minimum of eighteen clock cycles are required
to transfer the data in or out of the MAX1136–MAX1139.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions

The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see HS-mode).
Acknowledge Bits

Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX1136–MAX1139 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 6). To generate a not-acknowledge, the receiv-
er allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves
SDA high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer the bus master should reattempt
communication at a later time.
MAX1136–MAX1139
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs

SCL
SDASr
Figure 5. START and STOP Conditions
SCL
SDANOT ACKNOWLEDGE
ACKNOWLEDGE89
Figure 6. Acknowledge Bits
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