MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceMAX1132/MAX113319-2083; Rev 0; 8/0116-Bit ADC, 200ksps, 5V Single-Supplywith Reference
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with Referenceapplications. The MAX1132 accepts input signals of 0to +12V (unipolar) or ±12V (bipolar), while the ..
MAX1132BEAP ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX1132BEAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX1132BEAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceELECTRICAL CHARACTERISTICS(AV = DV = +5V ±5%, f = 4.8MHz, external clock (50% duty cycle), 24 clock ..
MAX3483CPA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483CPA+ ,3.3V Powered, 10Mbps and Slew-Rate Limited, True RS-485/RS-422 Transceivers
MAX3483CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483CSA ,3.3V-Powered / 10Mbps and Slew-Rate-Limited True RS-485/RS-422 Transceivers
MAX3483CSA+ ,3.3V Powered, 10Mbps and Slew-Rate Limited, True RS-485/RS-422 Transceivers
MAX1132BCAP+-MAX1132BEAP+-MAX1133BCAP+-MAX1133BEAP+
16-Bit ADC, 200ksps, 5V Single-Supply with Reference
General DescriptionThe MAX1132/MAX1133 are 200ksps, 16-bit ADCs.
These serially interfaced ADCs connect directly to
SPI™, QSPI™, and MICROWIRE™ devices without
external logic. They combine an input scaling network,
internal track/hold, clock, a +4.096V reference, and
three general-purpose digital output pins (for external
multiplexer or PGA control) in a 20-pin SSOP package.
The excellent dynamic performance (SINAD ≥85dB),
high-speed (200ksps), and low power (7.5mA) of these
ADCs, make them ideal for applications such as indus-
trial process control, instrumentation, and medical
applications. The MAX1132 accepts input signals of 0
to +12V (unipolar) or ±12V (bipolar), while the
MAX1133 accepts input signals of 0 to +4.096V (unipo-
lar) or ±4.096V (bipolar). Operating from a single
+4.75V to +5.25V analog supply and a +4.75V to
+5.25V digital supply, power-down modes reduce
current consumption to 1mA at 10ksps and further
reduce supply current to less than 20µA at slower data
rates. A serial strobe output (SSTRB) allows direct con-
nection to the TMS320 family of digital signal proces-
sors. The MAX1132/MAX1133 user can select either the
internal clock, or an external serial-interface clock for
the ADC to perform analog-to-digital conversions.
The MAX1132/MAX1133 feature internal calibration cir-
cuitry to correct linearity and offset errors. On-demand
calibration allows the user to optimize performance.
Three user-programmable logic outputs are provided
for the control of an 8-channel mux or a PGA.
ApplicationsIndustrial Process Control
Industrial I/O Modules
Data-Acquisition Systems
Medical Instruments
Portable and Battery-Powered Equipment
Features200ksps (Bipolar) and 150ksps (Unipolar)
Sampling ADC16-Bits, No Missing Codes1.5LSB INL Guaranteed85dB (min) SINAD +5V Single-Supply OperationLow-Power Operation, 7.5mA (Unipolar Mode)2.5µA Shutdown ModeSoftware-Configurable Unipolar and Bipolar Input
Ranges
0 to +12V and ±12V (MAX1132)
0 to +4.096V and ±4.096V (MAX1133)
Internal or External ReferenceInternal or External ClockSPI/QSPI/MICROWIRE-Compatible Serial Interface Three User-Programmable Logic Outputs Small 20-Pin SSOP Package
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with ReferenceTOP VIEW
SHDN
RST
AGND
AIN
CREF
AVDD
AGND
REFADJ
REF
DIN
DVDD
DGND
SCLK
SSTRB
DGNDDOUT
MAX1132
MAX1133
SSOP
Pin Configuration19-2083; Rev 0; 8/01
EVALUATION KIT
AVAILABLE
Ordering Information
PART TEMP. RANGE PIN-PACKAGEINL
(LSB)
MAX1132ACAP*0°C to +70°C20 SSOP±1.5
MAX1132BCAP0°C to +70°C20 SSOP±2.5
Functional Diagram appears at end of data sheet.
Typical Application Circuit appears at end of data sheet.SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND, DVDDto DGND.............................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND.....................................................................±16.5V
REFADJ, CREF, REF to AGND.................-0.3V to (AVDD+ 0.3V)
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND.........................-0.3V to (DVDD+ 0.3V)
Continuous Power Dissipation (TA= +70°C)
20-Pin SSOP (derate 8.00mW/°C above +70°C).........640mW
Operating Temperature Ranges
MAX113_CAP......................................................0°C to +70°C
MAX113_EAP....................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
ELECTRICAL CHARACTERISTICS(AVDD= DVDD= +5V ±5%, fSCLK= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external
VREF= +4.096V, VREFADJ= AVDD, CREF= 2.2µF, CCREF= 1µF, TA = TMINto TMAX, unless otherwise noted. Typical values are at = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DC ACCURACY (Note 1)Resolution16Bits
MAX113_A±1.5Relative Accuracy (Note 2)INLBipolar modeMAX113_B±2.5LSB
No Missing Codes16Bits
MAX113_A-1+1Differential NonlinearityDNLBipolar modeMAX113_B-1+1.75LSB
Transition Noise0.77LSBRMS
MAX1132±4UnipolarMAX1133±2
MAX1132±6Offset Error
BipolarMAX1133±5
Unipolar±0.2Gain Error (Note 3)Bipolar±0.3%FSR
Offset D r i ft ( Bi p ol ar and U ni p ol ar ) Excluding reference drift±1ppm/oCai n D r i ft ( Bi p ol ar and U ni p ol ar ) Excluding reference drift±1ppm/oC
DYNAMIC SPECIFICATIONS (5kHz sine-wave input, 200ksps, 4.8MHz clock, bipolar input mode. MAX1132: 24Vp-p.MAX1133: 8.192Vp-p)
fIN = 5kHz85SINADfIN = 100kHz85dB
fIN = 5kHz87SNRfIN = 100kHz92dB
fIN = 5kHz-90THDfIN = 100kHz-92dB
fIN = 5kHz92SFDRfIN = 100kHz96dB
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +5V ±5%, fSCLK= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external
VREF= +4.096V, VREFADJ= AVDD, CREF= 2.2µF, CCREF= 1µF, TA = TMINto TMAX, unless otherwise noted. Typical values are at = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ANALOG INPUTUnipolar012MAX1132Bipolar-1212
Unipolar04.096Input Range
MAX1133Bipolar- 4.0964.096
Unipolar7.510.0MAX1132Bipolar5.97.9
Unipolar1001000Input Impedance
MAX1133Bipolar3.44.5
Input Capacitance32pF
CONVERSION RATEInternal Clock Frequency4MHz
Aperture DelaytAD10ns
Aperture JittertAS50ps
MODE 1 (24 External Clock Cycles per Conversion)Unipolar0.13External Clock FrequencyfSCLKBipolar0.14.8MHz
Unipolar4.17125Sample RatefS = fSCLK/24Bipolar4.17200ksps
Unipolar8240Conversion Time (Note 4)tCONV+ACQ =
24 / fSCLKBipolar5240µs
MODE 2 (Internal Clock Mode)External Clock Frequency
(Data Transfer Only)8MHz
Conversion TimeSSTRB low pulse width46µs
Unipolar1.82Acquisition TimeBipolar1.14µs
MODE 3 (32 External Clock Cycles per Conversion)External Clock FrequencyfSCLKUnipolar or bipolar0.14.8MHz
Sample RatefS = fSCLK/32Unipolar or bipolar3.125150ksps
Conversion Time (Note 4)tCONV+ACQ =
32 / fSCLKUnipolar or bipolar6.67320µs
INTERNAL REFERENCEOutput VoltageVREF4.0564.0964.136V
REF Short-Circuit Current24mA
Output Tempco±20ppm/oC
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
ELECTRICAL CHARACTERISTICS (continued)(AVDD= DVDD= +5V ±5%, fSCLK= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external
VREF= +4.096V, VREFADJ= AVDD, CREF= 2.2µF, CCREF= 1µF, TA = TMINto TMAX, unless otherwise noted. Typical values are at = +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSCapacitive Bypass at REF0.4710µF
Maximum Capacitive Bypass at
REFADJ10µF
REFADJ Output Voltage4.096V
REFADJ Input RangeFor small adjustments from 4.096V±100mV
REFADJ Buffer Disable
ThresholdTo power-down the internal referenceAV D D -
0.5V
AV D D -
0.1V V
Buffer Voltage Gain1V/V
EXTERNAL REFERENCE (Reference buffer disabled. Reference applied to REF)Input Range (Notes 5 and 6)3.04.0964.2V
VREF = 4.096V, fSCLK = 4.8MHz250
VREF = 4.096V, fSCLK = 0230Input Current
In power-down, fSCLK = 00.1
DIGITAL INPUTSInput High VoltageVIH2.4V
Input Low VoltageVIL0.8V
Input LeakageIINVIN = 0 or DVDD±1µA
Input HysteresisVHYST0.2V
Input CapacitanceCIN10pF
DIGITAL OUTPUTSOutput High VoltageVOHISOURCE = 0.5mADVDD -
0.5V
ISINK = 5mA0.4Output Low VoltageVOLISINK = 16mA0.8V
Three-State Leakage CurrentILCS = DVDD±10µA
Three-State Output
CapacitanceCS = DVDD10pF
POWER SUPPLIESAnalog Supply (Note 7)AVDD4.7555.25V
Digital Supply (Note 7)DVDD4.7555.25V
Unipolar mode58
Bipolar mode8.511mAAnalog Supply CurrentIANALOG
SHDN = 0, or softw are power -down mode0.310µA
Unipolar or bipolar mode2.53.5mADigital Supply CurrentIDIGITALSHDN = 0, or softw are power -down mode2.210µA
Power-Supply Rejection Ratio
(Note 8)PSRRAVDD = DVDD = 4.75V to 5.25V72dB
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Note 1:Tested at AVDD = DVDD = +5V, bipolar input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nulled.
Note 3:Offset nulled.
Note 4:Conversion time is defined as the number of clock cycles multiplied by the clock period, clock has 50% duty cycle.
Includes the acquisition time.
Note 5:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 6:When an external reference has a different voltage than the specified typical value, the full scale of the ADC will scale
proportionally.
Note 7:Electrical characteristics are guaranteed from AVDD(MIN)= DVDD(MIN)to AVDD(MAX)= DVDD(MAX). For operations beyond
this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 8:Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
TIMING CHARACTERISTICS (Figures 5 and 6)(AVDD= DVDD= +5V ±5%, TA= TMINto TMAX, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQ1.14µs
DIN to SCLK SetuptDS50ns
DIN to SCLK HoldtDH0ns
SCLK to DOUT ValidtDO70ns
CS Fall to DOUT EnabletDVCLOAD = 50pF80ns
CS Rise to DOUT DisabletTRCLOAD = 50pF80ns
CS to SCLK Rise SetuptCSS100ns
CS to SCLK Rise HoldtCSH0ns
SCLK High Pulse WidthtCH80ns
SCLK Low Pulse WidthtCL80ns
SCLK Fall to SSTRBtSSTRBCLOAD = 50pF80ns
CS Fall to SSTRB EnabletSDVCLOAD = 50pF, external clock mode80ns
CS Rise to SSTRB DisabletSTRCLOAD = 50pF, external clock mode80ns
SSTRB Rise to SCLK RisetSCKInternal clock mode0ns
RST Pulse WidthtRS208ns
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Typical Operating Characteristics(MAX1132/MAX1133: AVDD= DVDD= +5V , fSCLK= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps),
bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, TA= 25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1132 toc01
DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1132 toc02
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
MAX1132 toc03
TEMPERATURE (°C)
TOTAL SUPPLY CURRENT (mA)A
A: AVDD, DVDD = +4.75V
B: AVDD, DVDD = +5.00V
C: AVDD, DVDD = +5.25V
OFFSET VOLTAGE vs. TEMPERATUREMAX1132 toc04
TEMPERATURE (°C)
OFFSET VOLTAGE (mV)
A: AVDD, DVDD = +4.75V
B: AVDD, DVDD = +5.00V
C: AVDD, DVDD = +5.25V
GAIN ERROR vs. TEMPERATURE
MAX1132 toc05
TEMPERATURE (°C)
GAIN ERROR (% FULL SCALE)
A: AVDD, DVDD = +4.75V
B: AVDD, DVDD = +5.00V
C: AVDD, DVDD = +5.25V
TOTAL SUPPLY CURRENT vs.
CONVERSION RATE (USING SHUTDOWN)
MAX1132 toc06
CONVERSION RATE (ksps)
TOTAL SUPPLY CURRENT (mA)
NORMALIZED REF VOLTAGE
vs. TEMPERATURE
MAX1132 toc07
NORMALIZED REF VOLTAGE (V)
FFT PLOT
MAX1132 toc08
AMPLITUDE (dB)
fSAMPLE = 200kHz
fIN = 5kHz90
SINAD PLOT
MAX1132 toc09
AMPLITUDE (dB)
fSAMPLE = 200kHz
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Typical Operating Characteristics (continued)(MAX1132/MAX1133: AVDD= DVDD= +5V , fSCLK= 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps),
bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, TA= 25°C, unless otherwise noted.)
SFDR PLOT
MAX1132 toc10
FREQUENCY (kHz)
AMPLITUDE (dB)
fSAMPLE = 200kHz
THD PLOT
MAX1132 toc11
FREQUENCY (kHz)
AMPLITUDE (dB)
fSAMPLE = 200kHz
PINNAMEFUNCTIONREF
Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at
REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AVDD. Bypass to
AGND with a 2.2µF capacitor when using the internal reference.REFADJBandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22µF. When using an
external reference, connect REFADJ to AVDD to disable the internal bandgap reference.AGNDAnalog Ground. This is the primary analog ground (Star Ground).
4AVDDAnalog Supply. 5V ±5%. Bypass AVDD to AGND (pin 3) with a 0.1µF capacitor.DGNDDigital GroundSHDNShutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.P2User-Programmable Output 2P1User-Programmable Output 1P0User-Programmable Output 0SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period
before the MSB decision. It is high impedance when CS is high in external clock mode.DOUTSerial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.
Each bit is clocked out of DOUT at the falling edge of SCLK.RSTReset Inp ut. D r i ve RST l ow to p ut the d evi ce i n the p ow er - on d efaul t m od e. S ee the P ow er - O n Reset secti on.
Pin Description
MAX1132/MAX1133
Detailed DescriptionThe MAX1132/MAX1133 analog-to-digital converters
(ADCs) use a successive-approximation technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 16-bit digital output. The MAX1132/MAX1133
easily interfaces to microprocessors (µPs). The data
bits can be read either during the conversion in exter-
nal clock mode or after the conversion in internal clock
mode.
In addition to a 16-bit ADC, the MAX1132/MAX1133
include an input scaler, an internal digital microcon-
troller, calibration circuitry, an internal clock generator,
and an internal bandgap reference. The input scaler for
the MAX1132 enables conversion of input signals rang-
ing from 0 to +12V (unipolar input) or ±12V (bipolar
input). The MAX1133 accepts 0 to +4.096V (unipolar
input) or ±4.096V (bipolar input). Input range selection
is software controlled.
Calibration To minimize linearity, offset, and gain errors, the
MAX1132/MAX1133 have on-demand software calibra-
tion. Initiate calibration by writing a Control-Byte with bit
M1 = 0, and bit M0 = 1 (see Table 1). Select internal or
external clock for calibration by setting the INT/EXTbit
in the Control Byte. Calibrate the MAX1132/MAX1133
with the clock used for performing conversions.
Offsets resulting from synchronous noise (such as the
conversion clock) are canceled by the MAX1132/
MAX1133’s calibration circuitry. However, because the
magnitude of the offset produced by a synchronous
signal depends on the signal’s shape, recalibration
clock or other digital signals change, as might occur if
more than one clock signal or frequency is used.
Input ScalerThe MAX1132/MAX1133 have an input scaler which
allows conversion of true bipolar input voltages while
operating from a single +5V supply. The input scaler
attenuates and shifts the input as necessary to map the
external input range to the input range of the internal
DAC. The MAX1132 analog input range is 0 to +12V
(unipolar) or ±12V (bipolar). The MAX1133 analog input
range is 0 to +4.096V (unipolar) or ±4.096V (bipolar).
Unipolar and bipolar mode selection is configured with
bit 6 of the serial Control Byte.
Figure 1 shows the equivalent input circuit of the
MAX1132/MAX1133. The resistor network on the analog
input provides ±16.5V fault protection. This circuit limits
the current going into or out of the pin to less than 2mA.
The overvoltage protection is active, even if the device
is in a power-down mode, or if AVDD= 0.
Digital InterfaceThe digital interface pins consist of SHDN, RST, SSTRB,
DOUT, SCLK, DIN and CS. Bringing SHDNlow, places
the MAX1132/MAX1133 in its 2.5µA shutdown mode. A
logic low on RSThalts the MAX1132/MAX1133 opera-
tion and returns the part to its power-on reset state.
In external clock mode, SSTRB is is low and pulses
high for one clock cycle at the start of conversion. In
internal clock mode, SSTRB goes low at the start of the
conversion and goes high to indicate the conversion is
finished.
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
PINNAMEFUNCTIONSCLKSerial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated
on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed.DGNDDigital Ground. Connect to pin 5.DVDDDigital Supply. 5V ±5%. Bypass DVDD to DGND (pin 14) with a 0.1µF capacitor.DINSerial Data Input. Serial data on DIN is latched on the rising edge of SCLK.CSChip-Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high impedance.
In external clock mode, SSTRB is high impedance when CS is high.CREFReference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1µF.AGNDAnalog Ground. Connect pin 19 to pin 3.AINAnalog Input
Pin Description (continued)
The DIN input accepts Control Byte data which is
clocked in on each rising edge of SCLK. After CSgoes
low or after a conversion or calibration completes, the
first logic “1” clocked into DIN is interpreted as the
START bit, the MSB of the 8-bit Control Byte.
The SCLK input is the serial data transfer clock which
clocks data in and out of the MAX1132/MAX1133.
SCLK also drives the A/D conversion steps in external
clock mode (see Internal and External Clock Modes
section).
DOUT is the serial output of the conversion result.
DOUT is updated on the falling edge of SCLK. DOUT is
high-impedance when CSis high.must be low for the MAX1132/MAX1133 to accept a
Control Byte. The serial interface is disabled when CS
is high.
User-Programmable Outputs The MAX1132/MAX1133 have three user-programma-
ble outputs, P0, P1 and P2. The power-on default state
for the programmable outputs is zero. These are push-
pull CMOS outputs suitable for driving a multiplexer, a
PGA, or other signal preconditioning circuitry. The user-
programmable outputs are controlled by bits 0, 1, and
2 of the Control Byte (Table 2).
The user-programmable outputs are set to zero during
power-on reset (POR) or when RSTgoes low. During
hardware or software shutdown P0, P1, and P2 are
unchanged and remain low-impedance.
Starting a ConversionStart a conversion by clocking a Control Byte into the
device’s internal shift register. With CSlow, each rising
edge on SCLK clocks a bit from DIN into the
MAX1132/MAX1133’s internal shift register. After CS
goes low or after a conversion or calibration completes,
the first arriving logic “1” is defined as the start bit of
the Control Byte. Until this first start bit arrives, any
number of logic “0” bits can be clocked into DIN with
no effect. If at any time during acquisition or conversion,is brought high and then low again, the part is
placed into a state where it can recognize a new start
bit. If a new start bit occurs before the current conver-
sion is complete, the conversion is aborted and a new
acquisition is initiated.
Internal and External Clock ModesThe MAX1132/MAX1133 may use either the external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX1132/MAX1133. Bit 5 (INT/EXT) of the Control Byte
programs the clock mode.
External ClockIn external clock mode, the external clock not only
shifts data in and out, but it also drives the ADC con-
version steps. In short acquisition mode, SSTRB pulses
high for one clock period after the seventh falling edge
of SCLK following the start bit. The MSB of the conver-
sion is available at DOUT on the eighth falling edge of
SCLK (Figure 2).
In long acquisition mode, when using external clock,
SSTRB pulses high for one clock period after the fif-
teenth falling edge of SCLK following the start bit. The
MSB of the conversion is available at DOUT on the six-
teenth falling edge of SCLK (Figure 3).
In external clock mode, SSTRB is high-impedance
when CSis high. In external clock mode, CSis normally
held low during the entire conversion. If CSgoes high
during the conversion, SCLK is ignored until CSgoes
low. This allows external clock mode to be used with 8-
bit bytes.
Internal Clock In internal clock mode, the MAX1132/MAX1133 gener-
ates its own conversion clock. This frees the micro-
processor from the burden of running the SAR conver-
sion clock, and allows the conversion results to be read
back at the processor’s convenience, at any clock rate
up to 8MHz.
SSTRB goes low at the start of the conversion and goes
high when the conversion is complete. SSTRB will be
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with ReferenceS1 = BIPOLAR/UNIPOLAR
S2, S3 = T/H SWITCHAIN
2.5kΩ
VOLTAGE
REFERENCE
T/H OUT
HOLD
HOLD
TRACK
TRACK
BIPOLAR
UNIPOLAR
R2 = 7.6kΩ (MAX1132)
OR 2.5kΩ (MAX1133)
R3 = 3.9kΩ (MAX1132)
OR INFINITY (MAX1133)
CHOLD
30pF
Figure 1.Equivalent Input Circuit
MAX1132/MAX1133
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Table 1. Control Byte Format
BITNAMEDESCRIPTION7 (MSB)STARTThe first logic “1” bit, after CS goes low, defines the beginning of the Control ByteUNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog
input signals from 0 to +12V (MAX1132) or 0 to VREF (MAX1133) can be converted. In bipolar
mode analog input signals from -12V to +12V (MAX1132) or -VREF to +VREF (MAX1133) can be
converted.INT/EXTSelects the internal or external conversion clock. 1 = Internal, 0 = External.
4M1
M0MODE024 External clocks per conversion (short acquisition mode)1Start Calibration. Starts internal calibration.0Software power-down mode
3M0132 External clocks per conversion (long acquisition mode)
0(LSB)
These three bits are stored in a port register and output to pins P2, P1, P0 for use in addressing
a mux or PGA. These three bits are updated in the port register simultaneously when a new
Control Byte is written.
Table 2. User-Programmable Outputs
OUTPUT
PIN
PROGRAMMED
THROUGH
CONTROL BYTE
POWER-ON
OR RST
DEFAULT
DESCRIPTIONBit 20Bit 10Bit 00ser - p r og r am m ab l e outp uts fol l ow the state of the C ontr ol Byte’ s thr ee LS Bs
and ar e up d ated si m ul taneousl y w hen a new C ontr ol Byte i s w r i tten. O utp uts
ar e p ush- p ul l . In har d w ar e and softw ar e shutd ow n, these outp uts ar e
unchang ed and r em ai n l ow - i m p ed ance.
ACQUISITIONCONVERSIONIDLEIDLE
SCLK
DOUT
A/D
STATE
DIN
SSTRB1812
STARTM1M0P2P1P0UNI/
BIP
INT/
EXT2124
B12B11B14B13B10B9B4B15
MSB
LSB
FILLED WITH
ZEROSB2B3B1
tACQ
