MAX1081BEUP+ ,300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal ReferenceFeaturesThe MAX1080/MAX1081 10-bit analog-to-digital convert-♦ 8-Channel Single-Ended or 4-Channele ..
MAX1082ACUE ,300ksps/400ksps / Single-Supply / 4-Channel / Serial 10-Bit ADCs with Internal ReferenceApplicationsPin ConfigurationPortable Data Logging TOP VIEWData AcquisitionMedical Instruments V 1 ..
MAX1083BCUE ,300ksps/400ksps / Single-Supply / 4-Channel / Serial 10-Bit ADCs with Internal ReferenceFeaturesThe MAX1082/MAX1083 10-bit analog-to-digital convert- 4-Channel Single-Ended or 2-Channele ..
MAX1087EKA-T ,150ksps / 10-Bit / 2-Channel Single-Ended / and 1-Channel True-Differential ADCs in SOT23ApplicationsLow Power Data AcquisitionTEMP. PIN- TOPPARTRANGE PACKAGE MARKPortable Temperature Moni ..
MAX1087ETA+T ,150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23 and TDFNApplicationsMAX1086ETA+T -40°C to +85°C 8 TDFN-EP* AFQLow Power Data AcquisitionMAX1087EKA-T -40°C ..
MAX1089EKA+T ,150ksps / 10-Bit / 2-Channel Single-Ended / and 1-Channel True-Differential ADCs in SOT23ELECTRICAL CHARACTERISTICS(V = +2.7V to +3.6V, V = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5 ..
MAX3393EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX3393EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level ..
MAX3394EEBL+T ,±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up CircuitryApplicationsSelector Guide appears at end of data sheet.Multivoltage Bidirectional Level Translatio ..
MAX339CEE ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersGeneral DescriptionThe MAX338/MAX339 are monolithic, CMOS analog♦ On-Resistance, <400Ω maxmultiplex ..
MAX339CEE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, V = 0V, V = +2.4V, V = +0.8V, T = T ..
MAX339CPE ,Dual 4-channel, low-leakage, CMOS analog multiplexer.ApplicationsMAX338MJE -55°C to +125°C 16 CERDIP**Data-Acquisition Systems Sample-and-Hold CircuitsO ..
MAX1081BEUP+
300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal Reference
General DescriptionThe MAX1080/MAX1081 10-bit analog-to-digital convert-
ers (ADCs) combine an 8-channel analog-input multiplex-
er, high-bandwidth track/hold (T/H), and serial interface
with high conversion speed and low power consumption.
The MAX1080 operates from a single +4.5V to +5.5V sup-
ply; the MAX1081 operates from a single +2.7V to +3.6V
supply. Both devices’ analog inputs are software config-
urable for unipolar/bipolar and single-ended/pseudo-dif-
ferential operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1080/
MAX1081 use an external serial-interface clock to perform
successive-approximation analog-to-digital conversions.
The devices feature an internal +2.5V reference and a ref-
erence-buffer amplifier with a ±1.5% voltage-adjustment
range. An external reference with a 1V to VDD1range may
also be used.
The MAX1080/MAX1081 provide a hard-wired SHDNpin
and four software-selectable power modes (normal opera-
tion, reduced power (REDP), fast power-down (FASTPD),
and full power-down (FULLPD)). These devices can be
programmed to automatically shut down at the end of a
conversion or to operate with reduced power. When using
the power-down modes, accessing the serial interface
automatically powers up the devices, and the quick turn-
on time allows them to be shut down between all conver-
sions. This technique can cut supply current below 100mA
at lower sampling rates.
The MAX1080/MAX1081 are available in a 20-pin TSSOP
package. These devices are higher-speed versions of the
MAX148/MAX149. For more information, refer to the
respective data sheet.
ApplicationsPortable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
Features8-Channel Single-Ended or 4-Channel
Pseudo-Differential InputsInternal Multiplexer and Track/HoldSingle-Supply Operation
+4.5V to +5.5V (MAX1080)
+2.7V to +3.6V (MAX1081)Internal +2.5V Reference400ksps Sampling Rate (MAX1080)Low Power: 2.5mA (400ksps)
1.3mA (REDP)
0.9mA (FASTPD)
2µA (FULLPD)SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial InterfaceSoftware-Configurable Unipolar or Bipolar Inputs20-Pin TSSOP Package
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power
8-Channel, Serial 10-Bit ADCs with Internal ReferenceTOP VIEW
TSSOPVDD1
VDD2
DIN
SSTRB
DOUT
GND
REFADJ
REF
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX1080
MAX1081
SHDN
SCLK
19-1685; Rev 0; 5/00
PART
MAX1080ACUPMAX1080BCUP
MAX1080AEUP-40°C to +85°C
0°C to +70°C
0°C to +70°C
TEMP.
RANGE
PIN-
PACKAGE20 TSSOP
20 TSSOP
20 TSSOP
Typical Operating Circuit appears at end of data sheet.
Pin Configuration
INL
(LSB)±1/2
±1/2
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Ordering Information continued at end of data sheet.
Ordering Information
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS—MAX1080(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD_to GND..............................................................-0.3V to 6V
VDD1to VDD2.........................................................-0.3V to 0.3V
CH0–CH7, COM to GND..........................-0.3V to (VDD1+ 0.3V)
REF, REFADJ to GND..............................-0.3V to (VDD1+ 0.3V)
Digital Inputs to GND.................................................-0.3V to 6V
Digital Outputs to GND............................-0.3V to (VDD2+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
20-Pin TSSOP (derate 7.0mW/°C above +70°C)........559mW
Operating Temperature Ranges
MAX108_ _CUP.................................................0°C to +70°C
MAX108_ _EUP...............................................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s)................................+300°C
MAX1080A
SINAD > 58dB
-3dB point
fIN = 200kHz, VIN= 2.5Vp-p
fIN1= 99kHz, fIN2=102kHz
MAX1080B
No missing codes over temperature
Up to the 5th harmonic
CONDITIONSMHz0.56.4fSCLKSerial Clock Frequency<50Aperture Jitter10Aperture Delay468tACQTrack/Hold Acquisition Time2.5tCONVConversion Time (Note 5)
kHz350Full-Linear Bandwidth
MHz6Full-Power Bandwidth-78Channel-to-Channel Crosstalk
(Note 4)76IMDIntermodulation Distortion70SFDRSpurious-Free Dynamic Range-70THDTotal Harmonic Distortion
LSB±0.5INLRelative Accuracy (Note 2)
Bits10Resolution60SINADSignal-to-Noise plus Distortion
Ratio
LSB±0.1Channel-to-Channel Offset-Error
Matching
ppm/°C ±0.8Gain-Error Temperature
Coefficient
±1.0
LSB±1.0DNLDifferential Nonlinearity
LSB±3.0Offset Error
LSB±3.0Gain Error (Note 3)
UNITSMINTYPMAXSYMBOLPARAMETER4060Duty Cycle
DYNAMIC SPECIFICATIONS(100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)
DC ACCURACY(Note 1)
CONVERSION RATE
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power
8-Channel, Serial 10-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1080 (continued)(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETERTo power down the internal reference
For small adjustments, from 1.22V
0 to 1mA output load
On/off leakage current, VCH_= 0 or VDD1= +25°C
Bipolar, VCOMor VCH_ = VREF/2, referenced
to COM or CH_
Unipolar, VCOM= 0
V/V+2.05Buffer Voltage Gain1.4VDD1- 1.0REFADJ Buffer Disable
Threshold±100REFADJ Input Range1.22REFADJ Output Voltage0.0110Capacitive Bypass at REFADJ4.710Capacitive Bypass at REF
mV/mA0.12.0Load Regulation (Note 7)
ppm/°C±15TC VREFREF Output Temperature
Coefficient30REF Short-Circuit Current2.4802.5002.520VREFREF Output Voltage18Input Capacitance±0.001±1Multiplexer Leakage Current
±VREF/2V
VREF
VCH_Input Voltage Range, Single
Ended and Differential (Note 6)
VIN= 0 or VDD2
In power-down mode, fSCLK= 0
VREF= 2.500V, fSCLK= 0
VREF= 2.500V, fSCLK= 6.4MHz
(Note 8)CINInput Capacitance±1IINInput Leakage0.2VHYSTInput Hysteresis0.8VINLInput Low Voltage3.0VINHInput High Voltage
320µA
REF Input Current1.0VDD1+
50mVREF Input Voltage Range
ISINK= 5mAV0.4VOLOutput Voltage Low
ISOURCE= 1mAV4VOHOutput Voltage High= 5VµA±10ILThree-State Leakage Current= 5VpF15COUTThree-State Output Capacitance
ANALOG INPUTS(CH7–CH0, COM)
EXTERNAL REFERENCE(reference buffer disabled, reference applied to REF)
INTERNAL REFERENCE
DIGITAL INPUTS(DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS(DOUT, SSTRB)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal ReferenceVDD1=
VDD2=
5.5V
VDD1= VDD2= 5V ±10%, midscale input
CONDITIONSIVDD1+
IVDD2
Supply Current4.55.5VDD1,
VDD2
Positive Supply Voltage
(Note 9)
0.91.5210±0.5±2.0PSRPower-Supply Rejection
UNITSMINTYPMAXSYMBOLPARAMETERNormal operating mode (Note 10)
Reduced-power mode (Note 11)
Fast power-down mode (Note 11)
Full power-down mode (Note 11)
ELECTRICAL CHARACTERISTICS—MAX1080 (continued)(VDD1= VDD2= +4.5V to +5.5V, COM = GND, fSCLK= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS—MAX1081(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fSCLK= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
MAX1081A
SINAD > 58dB
-3dB point
fIN= 150kHz, VIN= 2.5Vp-p
fIN1= 73kHz, fIN2= 77kHz
MAX1081B
No missing codes over temperature
Up to the 5th harmonic
CONDITIONSkHz250Full-Linear Bandwidth
MHz3Full-Power Bandwidth-78Channel-to-Channel Crosstalk
(Note 4)76IMDIntermodulation Distortion70SFDRSpurious-Free Dynamic Range-70THDTotal Harmonic Distortion
LSB±0.5INLRelative Accuracy (Note 2)
Bits10Resolution60SINADSignal-to-Noise plus Distortion
Ratio
LSB±0.2Channel-to-Channel Offset-Error
Matching
ppm/°C ±1.6Gain-Error Temperature
Coefficient
±1.0
LSB±1.0DNLDifferential Nonlinearity
LSB±3.0Offset Error
LSB±3.0Gain Error (Note 3)
UNITSMINTYPMAXSYMBOLPARAMETER
POWER SUPPLY
DC ACCURACY(Note 1)
DYNAMIC SPECIFICATIONS(75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power
8-Channel, Serial 10-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1081(continued)(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fSCLK= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Normal operating mode
Normal operating mode
Normal operating mode
CONDITIONSMHz0.54.8fSCLKSerial Clock Frequency<50Aperture Jitter10Aperture Delay625tACQTrack/Hold Acquisition Time3.3tCONVConversion Time (Note 5)
UNITSMINTYPMAXSYMBOLPARAMETERTo power down the internal reference
For small adjustments, from 1.22V
0 to 0.75mA output load
On/off leakage current, VCH_= 0 or VDD1= +25°C
Bipolar, VCOMor VCH_ = VREF/2,
referenced to COM or CH_
Unipolar, VCOM= 0
V/V2.05Buffer Voltage Gain1.4VDD1- 1REFADJ Buffer Disable
Threshold±100REFADJ Input Range1.22REFADJ Output Voltage0.0110Capacitive Bypass at REFADJ4.710Capacitive Bypass at REF
mV/mA0.12.0Load Regulation (Note 7)
ppm/°C±15TC VREFREF Output Temperature
Coefficient15REF Short-Circuit Current2.4802.5002.520VREFREF Output Voltage18Input Capacitance±0.001±1Multiplexer Leakage Current
±VREF/24060Duty Cycle
VREF
VCH_Input Voltage Range, Single
Ended and Differential (Note 6)
VIN= 0 or VDD2
In power-down mode, fSCLK= 0
VREF= 2.500V, fSCLK= 0
VREF= 2.500V, fSCLK= 4.8MHz
(Note 8)15CINInput Capacitance±1IINInput Leakage0.2VHYSTInput Hysteresis0.8VINLInput Low Voltage2.0VINHInput High Voltage
REF Input Current320µA
2003501.0VDD1+
50mVREF Input Voltage Range
V/V+2.05Buffer Voltage Gain
CONVERSION RATE
ANALOG INPUTS(CH7–CH0, COM)
INTERNAL REFERENCE
EXTERNAL REFERENCE(reference buffer disabled, reference applied to REF)
DIGITAL INPUTS(DIN, SCLK, CS, SHDN)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal ReferenceVDD1=
VDD2=
3.6V
ISOURCE= 0.5mA
VDD1= VDD2= 2.7V to 3.6V, midscale input
CONDITIONSIVDD1+
IVDD2Supply Current2.73.6VDD1,
VDD2VDD2 - 0.5VVOHOutput Voltage High
Positive Supply Voltage
(Note 9)
Normal operating mode (Note 10)
Reduced-power mode (Note 11)
0.91.5Fast power-down mode (Note 11)
Full power-down mode (Note 11)µA210±0.5±2.0PSRPower-Supply Rejection
UNITSMINTYPMAXSYMBOLPARAMETERISINK= 5mAV0.4VOLOutput Voltage Low= 3VµA±10ILThree-State Leakage Current= 3VpF15COUTThree-State Output Capacitance
ELECTRICAL CHARACTERISTICS—MAX1081(continued)(VDD1= VDD2= +2.7V to +3.6V, COM = GND, fSCLK= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS–MAX1080(Figures 1, 2, 6, 7; VDD1= VDD2= +4.5V to +5.5V, TA= TMINto TMAX, unless otherwise noted.)
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CONDITIONS100tCSWCSPulse Width High65tSTECSFall to SSTRB Enable65tDOECSFall to DOUT Enable1065tSTDCSRise to SSTRB Disable1065tDODCSRise to DOUT Disable80tSTVSCLK Rise to SSTRB Valid80tDOVSCLK Rise to DOUT Valid62tCLSCLK Pulse Width Low62tCH156tCPSCLK Period
SCLK Pulse Width High1020tSTHSCLK Rise to SSTRB Hold1020tDOHSCLK Rise to DOUT Hold35tCS1CSRise to SCLK Rise Ignore35tCSOSCLK Rise to CSFall Ignore35tDSDIN to SCLK Setup0tDHDIN to SCLK Hold35tCSSCSFall to SCLK Rise Setup0tCSHSCLK Rise to CSRise Hold
UNITSMINTYPMAXSYMBOLPARAMETER
DIGITAL OUTPUTS(DOUT, SSTRB)
POWER SUPPLY
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power
8-Channel, Serial 10-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1081(Figures 1, 2, 6, 7; VDD1= VDD2= +2.7V to +3.6V, TA= TMINto TMAX, unless otherwise noted.)
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CLOAD= 20pF
CONDITIONS100tCSWCSPulse Width High85tSTECSFall to SSTRB Enable85tDOECSFall to DOUT Enable1385tSTDCSRise to SSTRB Disable1385tDODCSRise to DOUT Disable100tSTVSCLK Rise to SSTRB Valid100tDOVSCLK Rise to DOUT Valid83tCLSCLK Pulse Width Low83 tCH208tCPSCLK Period
SCLK Pulse Width High1320tSTHSCLK Rise to SSTRB Hold1320tDOHSCLK Rise to DOUT Hold45tCS1CSRise to SCLK Rise Ignore45tCSOSCLK Rise to CSFall ignore45tDSDIN to SCLK Setup0tDHDIN to SCLK Hold45tCSSCSFall to SCLK Rise Setup0tCSHSCLK Rise to CSRise Hold
UNITSMINTYPMAXSYMBOLPARAMETER
Note 1:Tested at VDD1= VDD2= VDD(MIN), COM = GND, unipolar single-ended input mode.
Note 2:Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:Offset nulled.
Note 4:Ground the “on” channel; sine wave is applied to all “off” channels.
Note 5:Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs (CH7–CH0 and COM) is from GND to VDD1.
Note 7: External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is the
result of production test limitations.
Note 8:ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9:Electrical characteristics are guaranteed from VDD1(MIN)= VDD2(MIN)to VDD1(MAX)= VDD2(MIN). For operations beyond
this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 10:AIN= midscale. Unipolar mode. MAX1080 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK= 6.4MHz, 0 to 5V.
MAX1081 tested with same loads, fSCLK= 4.8MHz, 0 to 3V.
Note 11:SCLK = DIN = GND, CS= VDD1.
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Typical Operating Characteristics(MAX1080: VDD1= VDD2= 5.0V, fSCLK= 6.4MHz; MAX1081: VDD1= VDD2= 3.0V, fSCLK= 4.8MHz; CLOAD= 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1080/1-01
DIGITAL OUTPUT CODE
INL (LSB)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1080/1-02
DIGITAL OUTPUT CODE
DNL (LSB)
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (CONVERTING)
MAX1080/1-03
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs. TEMPERATURE
MAX1080/1-04
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1081
MAX1080
NORMAL OPERATION (PD1 = PD0 = 1)
REDP (PD1 = 1, PD0 = 0)
FASTPD (PD1 = 0, PD0 = 1)
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (STATIC)
MAX1080/1-05
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT vs. TEMPERATURE
(STATIC)
MAX1080/1-06
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1080 (PD1 = 1, PD0 = 1)
MAX1080 (PD1 = 1, PD0 = 0)
MAX1080 (PD1 = 0, PD0 = 1)
MAX1081 (PD1 = 1, PD0 = 1)
MAX1081 (PD1 = 1, PD0 = 0)
MAX1081 (PD1 = 0, PD0 = 1)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1080/1-07
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
(PD1 = PD0 = 0)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1080/1-08
TEMPERATURE (°C)
SUPPLY CURRENT (
MAX1081
MAX1080
(PD1 = PD0 = 0)
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1080/1-09
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power
8-Channel, Serial 10-Bit ADCs with Internal ReferenceREFERENCE VOLTAGE vs. TEMPERATURE
MAX1080/1-10
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
MAX1081
MAX1080
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1080/1-11
VDD (V)
OFFSET ERROR (LSB)
OFFSET ERROR vs. TEMPERATURE
MAX1080/1-12
TEMPERATURE (°C)
OFFSET ERROR (LSB)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1080/1-13
VDD (V)
GAIN ERROR (LSB)
MAX1081
GAIN ERROR vs. TEMPERATURE
MAX1080/1-14
TEMPERATURE (°C)
GAIN ERROR (LSB)
-4010-15356085
ypical Operating Characteristics (continued)(MAX1080:VDD1= VDD2= 5.0V, fSCLK= 6.4MHz; MAX1081: VDD1= VDD2= 3.0V, fSCLK= 4.8MHz; CLOAD= 20pF, 4.7µF capacitor
at REF, 0.01µF capacitor at REFADJ, TA= +25°C, unless otherwise noted.)
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Pin DescriptionPositive Supply VoltageVDD219
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, connect REFADJ to
VDD1.REFADJ12
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CSis high.SSTRB15
Serial Data Input. Data is clocked in at SCLK’s rising edge.DIN16
Active-Low Chip Select. Data will not be clocked into DIN unless CSis low. When CSis high, DOUT
and SSTRB are high impedance.CS17
Serial Clock Input. Clocks data in and out of serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)SCLK18
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a 2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
VDD1.
REF11
Analog and Digital GroundGND13
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CSis high.DOUT14
Active-Low Shutdown Input. Pulling SHDNlow shuts down the device, reducing supply current to 2µA
(typ).SHDN10
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.COM9
PINSampling Analog InputsCH0–CH71–8
FUNCTIONNAMEVDD2
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
DOUT
a) High-Z to VOH and VOL to VOHb) High-Z to VOL and VOH to VOL
VDD2
GND
DOUT
CLOAD
20pF
CLOAD
20pF
GND
DOUT
a) VOH to High-Zb) VOL to High-Z
Figure 1. Load Circuits for Enable TimeFigure 2. Load Circuits for Disable Time
Positive Supply VoltageVDD120
Detailed DescriptionThe MAX1080/MAX1081 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 10-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1080/MAX1081.
Pseudo-Differential InputThe equivalent circuit of Figure 4 shows the MAX1080/
MAX1081s’ input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 1 and 2.
The MAX1080/MAX1081 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
sinusoidal signal at IN-, the input voltage is determined
by:
The maximum voltage variation is determined by:
A 2.6Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / fSCLK). When a DC refer-
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
CHOLDas a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLDfrom IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1/2 within the limits of 10-bit resolu-
tion. This action is equivalent to transferring a
12pF ✕[(VIN+ - VIN-)] charge from CHOLDto the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
max dV2f1LSBINCONV
REFCONVπ−−=()≤=
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power
8-Channel, Serial 10-Bit ADCs with Internal ReferenceINPUT
SHIFTREGISTERCONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFTREGISTER
+1.22V
REFERENCE
T/HANALOGINPUT
MUX
10 + 2-BIT
SAR ADC
DOUT
SSTRB
VDD1
VDD2
GND
SCLK
DIN
COM
REFADJ
REF
OUT
REF
CLOCK
+2.500V
17k
CH67
CH78
CH45
CH56
CH12
CH23
CH34
CH01
MAX1080
MAX1081
SHDN
2.05A≈
Figure 3. Functional Diagram
CHOLD
12pF
RIN
800Ω
HOLD
INPUT
MUX
CSWITCH*
*INCLUDES ALL INPUT PARASITICS
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
CH0
REF
GND
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
ZERO
VDD1/2
COMPARATOR
CAPACITIVE
DAC
6pF
TRACK
Figure 4. Equivalent Input CircuitININVsin(2ft)−−=()
Table 1. Channel Selection in Single-Ended Mode (SGL/DIF= 1)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH7COM0+–1+–0+–1+–0+–1+–0+–1+ –
Table 2. Channel Selection in Pseudo-Differential Mode (SGL/DIF= 0)
SEL2SEL1SEL0CH0CH1CH2CH3CH4CH5CH6CH70+–1+–0+–1+–0–+1–+0–+1–+
MAX1080/MAX1081
300ksps/400ksps, Single-Supply, Low-Power,
8-Channel, Serial 10-Bit ADCs with Internal Reference
Track/HoldThe T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter con-
verts the “+” input. If the converter is set up for differen-
tial inputs, the difference of [(IN+) - (IN-)]is converted.
At the end of the conversion, the positive input con-
nects back to IN+ and CHOLDcharges to the input sig-
nal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. It is calculated by the following equa-
tion:
tACQ= 7 ✕(RS+ RIN) ✕12pF
where RIN= 800Ω, RS= the source impedance of the
input signal, and tACQis never less than 468ns
(MAX1080) or 625ns (MAX1081). Note that source
impedances below 4kΩdo not significantly affect the
ADC’s AC performance.
Input BandwidthThe ADC’s input tracking circuitry has a 6MHz
(MAX1080) or 3MHz (MAX1081) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti-
alias filtering is recommended.
Analog Input ProtectionInternal protection diodes, which clamp the analog input
to VDD1and GND, allow the channel input pins to swing
from GND -0.3V to VDD1+ 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD1by more than 50mV or be
lower than GND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not allow the input current to exceed 2mA.
