MAX107ECS ,Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input AmplifierFeaturesThe MAX107 is a dual, 6-bit, analog-to-digital converter Two Matched 6-Bit, 400Msps ADCs(A ..
MAX107ECS+ ,Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input AmplifierFeaturesThe MAX107 is a dual, 6-bit, analog-to-digital converter♦ Two Matched 6-Bit, 400Msps ADCs(A ..
MAX1081BEUP+ ,300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal ReferenceFeaturesThe MAX1080/MAX1081 10-bit analog-to-digital convert-♦ 8-Channel Single-Ended or 4-Channele ..
MAX1082ACUE ,300ksps/400ksps / Single-Supply / 4-Channel / Serial 10-Bit ADCs with Internal ReferenceApplicationsPin ConfigurationPortable Data Logging TOP VIEWData AcquisitionMedical Instruments V 1 ..
MAX1083BCUE ,300ksps/400ksps / Single-Supply / 4-Channel / Serial 10-Bit ADCs with Internal ReferenceFeaturesThe MAX1082/MAX1083 10-bit analog-to-digital convert- 4-Channel Single-Ended or 2-Channele ..
MAX1087EKA-T ,150ksps / 10-Bit / 2-Channel Single-Ended / and 1-Channel True-Differential ADCs in SOT23ApplicationsLow Power Data AcquisitionTEMP. PIN- TOPPARTRANGE PACKAGE MARKPortable Temperature Moni ..
MAX3392EEBC-T ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications2SPI™, MICROWIRE™, and I C™ LevelI/O V 2 1 8 I/O V 1CC CCTranslation Low-Voltage ASIC L ..
MAX3392EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level ..
MAX3393EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX3393EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level ..
MAX3394EEBL+T ,±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up CircuitryApplicationsSelector Guide appears at end of data sheet.Multivoltage Bidirectional Level Translatio ..
MAX339CEE ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersGeneral DescriptionThe MAX338/MAX339 are monolithic, CMOS analog♦ On-Resistance, <400Ω maxmultiplex ..
MAX107ECS
Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier
General DescriptionThe MAX107 is a dual, 6-bit, analog-to-digital converter
(ADC) designed to allow fast and precise digitizing of in-
phase (I) and quadrature (Q) baseband signals. The
MAX107 converts the analog signals of both I and Q
components to digital outputs at 400Msps while achiev-
ing a signal-to-noise ratio (SNR) of typically 37dB with
an input frequency of 125MHz, and an integral nonlin-
earity (INL) and differential nonlinearity (DNL) of ±0.25
LSB. The MAX107 analog input preamplifiers feature a
400MHz, -0.5dB, and a 1.5GHz, -3dB analog input
bandwidth. Matching channel-to-channel performance
is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees
phase. Dynamic performance is 36.7dB signal-to-noise
plus distortion (SINAD) with a 125MHz analog input sig-
nal and a sampling speed of 400MHz. A fully differential
comparator design and encoding circuits reduce out-of-
sequence errors, and ensure excellent metastable per-
formance of only one error per 1016 clock cycles.
In addition, the MAX107 provides LVDS digital outputs
with an internal 6:12 demultiplexer that reduces the out-
put data rate to one-half the sample clock rate. Data is
output in two’s complement format. The MAX107 oper-
ates from a +5V analog supply and the LVDS output
ports operate at +3.3V. The data converter’s typical
power dissipation is 2.6W. The device is packaged in
an 80-pin, TQFP package with exposed paddle, and is
specified for the extended (-40°C to +85°C) tempera-
ture range. For a higher-speed, 800Msps version of the
MAX107, please refer to the MAX105 data sheet.
ApplicationsVSAT Receivers
WLANs
Test Instrumentation
Communications Systems
FeaturesTwo Matched 6-Bit, 400Msps ADCsExcellent Dynamic Performance
36.7dB SINAD at fIN ≈125MHz and
fCLK ≈400MHz Typical INL and DNL: ±0.25LSB Channel-to-Channel Phase Matching: ±0.2°Channel-to-Channel Gain Matching: ±0.04dB6:12 Demultiplexer reduces the Data Rates to
200MHzLow Error Rate: 1016Metastable States at
400MspsLVDS Digital Outputs in Two’s Complement
Format
MAX107
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
Block Diagram19-2007; Rev 0; 5/01
Ordering Information
Pin Configuration appears at end of data sheet.
MAX107
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
ABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, AVCCI, AVCCQ and AVCCR to AGND............-0.3V to +6V
OVCCI and OVCCQ to OGND...................................-0.3V to +4V
AGND to OGND...................................................-0.3V to +0.3V
P0I±to P5I±and A0I±to A5I±
DREADY+, DREADY- to OGNDI..............-0.3V to OVCCI+0.3V
P0Q±to P5Q±, A0Q±to A5Q±
DOR+ and DOR- to OGNDQ.................-0.3V to OVCCQ+0.3V
REF to AGNDR...........................................-0.3V to AVCCR+0.3V
Differential Voltage Between INI+ and INI-....................-2V, +2V
Differential Voltage Between INQ+ and INQ-.................-2V, +2V
Differential Voltage Between CLK+ and CLK-...............-2V, +2V
Maximum Current Into Any Pin...........................................50mA
Continuous Power Dissipation (TA= +70°C)
80-Pin TQFP (derate 44mW/°C above +70°C)..................3.5W
Operating Temperature Range
MAX107ECS.....................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead temperature (soldering, 10s)..................................+300°C
ELECTRICAL CHARACTERISTICS(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 401.408MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
MAX107
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 401.408MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
otherwise noted. Typical values are at TA= +25°C)
MAX107
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 401.408MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
MAX107
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
Note 1:INL and DNL is measured using a sine-histogram method.
Note 2:Input offset is the voltage required to cause a transition between codes 0 and -1.
Note 3:Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input voltage
level does not matter.
Note 4:The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting algo
rithm (e.g. FFT).
Note 5:Guaranteed by design and characterization.
Note 6:Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-mode
voltage expressed in dB.
Note 7:Measured with analog power supplies tied to the same potential.
Note 8:Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
Note 9:The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Note 10:Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
Note 11: Harmonic distortion components two through five are included in the total harmonic distortion specification.
Note 12:Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
frequency of fIN = 124.999 MHz.
Note 13:Measured with a differential probe, 1pF capacitance.
ELECTRICAL CHARACTERISTICS (continued)(AVCC= AVCCI = AVCCQ = AVCCR = +5V, OVCCI = OVCCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, fCLK= 401.408MHz, CL = 1µF to AGND at REF, RL= 100Ω±1% applied to digital LVDS outputs, TA= TMINto TMAX, unless
