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MAX106CHCMAXIMN/a1avai5V / 600Msps / 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier


MAX106CHC ,5V / 600Msps / 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold AmplifierFeaturesThe MAX106 PECL-compatible, 600Msps, 8-bit analog-to-' 600Msps Conversion Ratedigital conve ..
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MAX107ECS+ ,Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input AmplifierFeaturesThe MAX107 is a dual, 6-bit, analog-to-digital converter♦ Two Matched 6-Bit, 400Msps ADCs(A ..
MAX1081BEUP+ ,300ksps/400ksps, Single-Supply, Low-Power, 8-Channel, Serial 10-Bit ADCs with Internal ReferenceFeaturesThe MAX1080/MAX1081 10-bit analog-to-digital convert-♦ 8-Channel Single-Ended or 4-Channele ..
MAX1082ACUE ,300ksps/400ksps / Single-Supply / 4-Channel / Serial 10-Bit ADCs with Internal ReferenceApplicationsPin ConfigurationPortable Data Logging TOP VIEWData AcquisitionMedical Instruments V 1 ..
MAX1083BCUE ,300ksps/400ksps / Single-Supply / 4-Channel / Serial 10-Bit ADCs with Internal ReferenceFeaturesThe MAX1082/MAX1083 10-bit analog-to-digital convert- 4-Channel Single-Ended or 2-Channele ..
MAX3392EEBC ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX3392EEBC-T ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPApplications2SPI™, MICROWIRE™, and I C™ LevelI/O V 2 1 8 I/O V 1CC CCTranslation Low-Voltage ASIC L ..
MAX3392EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level ..
MAX3393EEUD ,【15kV ESD-Protected, 1レA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSPELECTRICAL CHARACTERISTICS(V = +1.65V to +5.5V, V = +1.2V to (V + 0.3V), GND = 0, I/O V and I/O V u ..
MAX3393EEUD+ ,±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level Translators in UCSP MAX3372E–MAX3379E/MAX3390E–MAX3393E±15kV ESD-Protected, 1µA, 16Mbps, Dual/Quad Low-Voltage Level ..
MAX3394EEBL+T ,±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/Octal-Level Translators with Speed-Up CircuitryApplicationsSelector Guide appears at end of data sheet.Multivoltage Bidirectional Level Translatio ..


MAX106CHC
5V / 600Msps / 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
General Description
The MAX106 PECL-compatible, 600Msps, 8-bit analog-to-
digital converter (ADC) allows accurate digitizing of ana-
log signals with bandwidths to 2.2GHz. Fabricated on
Maxim’s proprietary advanced GST-2 bipolar process, the
MAX106 integrates a high-performance track/hold (T/H)
amplifier and a quantizer on a single monolithic die.
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high, 7.6 effective bits performance at the
Nyquist frequency. A fully differential comparator design
and decoding circuitry combine to reduce out-of-
sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance of
one error per 1027clock cycles. Unlike other ADCs, which
can have errors that result in false full- or zero-scale out-
puts, the MAX106 limits the error magnitude to 1LSB.
The analog input is designed for either differential or sin-
gle-ended use with a ±250mV input voltage range. Dual,
differential, PECL-compatible output data paths ensure
easy interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3V to +5V for compatibility with +3.3V or
+5V referenced systems. Control inputs are provided for
interleaving additional MAX106 devices to increase the
effective system sampling rate.
The MAX106 is packaged in a 25mm x 25mm, 192-con-
tact Enhanced Super-Ball-Grid Array (ESBGA™), and is
specified over the commercial (0°C to +70°C) temperature
range. For a pin-compatible higher speed upgrade, refer
to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data
sheets.
Applications

Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/ECM Systems
ATE Systems
Features
600Msps Conversion Rate2.2GHz Full-Power Analog Input Bandwidth7.6 Effective Bits at fIN= 300MHz
(Nyquist frequency)
±0.25LSB INL and DNL 50ΩDifferential Analog Inputs±250mV Input Signal RangeOn-Chip, +2.5V Precision Bandgap Voltage
Reference
Latched, Differential PECL Digital OutputsLow Error Rate: 10-27Metastable StatesSelectable 8:16 DemultiplexerInternal Demux Reset Input with Reset Output192-Contact ESBGAPin Compatible with Faster MAX104/MAX108
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier

19-1486; Rev 0; 7/99
Typical Operating Circuit appears at end of data sheet.
Ordering Information
192-Contact ESBGA
Ball Assignment Matrix

ESBGA is a trademark of Amkor/Anam.
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCA to GNDA.........................................................-0.3V to +6V
VCCD to GNDD.........................................................-0.3V to +6V
VCCI to GNDI............................................................-0.3V to +6V
VCCO to GNDD........................................-0.3V to (VCCD + 0.3V)
AUXEN1, AUXEN2 to GND .....................-0.3V to (VCCD + 0.3V)
VEEto GNDI..............................................................-6V to +0.3V
Between GNDs......................................................-0.3V to +0.3V
VCCA to VCCD.......................................................-0.3V to +0.3V
VCCA to VCCI.........................................................-0.3V to +0.3V
PECL Digital Output Current...............................................50mA
REFIN to GNDR ........................................-0.3V to (VCCI + 0.3V)
REFOUT Current................................................+100µA to -5mA
ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V
TTL/CMOS Control Inputs
(DEMUXEN, DIVSELECT)....................-0.3V to (VCCD + 0.3V)
RSTIN+, RSTIN- ......................................-0.3V to (VCCO + 0.3V)
VOSADJ Adjust Input................................-0.3V to (VCCI + 0.3V)
CLK+ to CLK- Voltage Difference..........................................±3V
CLK+, CLK-.....................................(VEE- 0.3V) to (GNDD + 1V)
CLKCOM.........................................(VEE- 0.3V) to (GNDD + 1V)
VIN+ to VIN- Voltage Difference............................................±2V
VIN+, VIN- to GNDI................................................................±2V
Continuous Power Dissipation (TA= +70°C)
192-Contact ESBGA (derate 61mW/°C above +70°C)...4.88W
(with heatsink and 200LFM airflow,
derate 106mW/°C above +70°C)....................................8.48W
Operating Temperature Range
MAX106CHC........................................................0°C to +70°C
Operating Junction Temperature.....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V ±5%, VEE= -5.0V ±5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA= TMINto TMAX,
unless otherwise noted. Typical values are at TA= +25°C.)
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
AC ELECTRICAL CHARACTERISTICS

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, fINat -1dBFS, TA= +25°C,
unless otherwise noted.)
Note 1:
Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256 ·slope of the line.
Note 2:
The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3:
The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on
the CLK+ and CLK- inputs.
Note 4:
Input logic levels are measured with respect to the VCCO power-supply voltage.
Note 5:
All PECL digital outputs are loaded with 50Ωto VCCO - 2.0V. Measurements are made with respect to the VCCO power-
supply voltage.
Note 6:
The current in the VCCO power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the VTTtermination voltage.
Note 7:
Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the
common-mode voltage, expressed in dB.
Note 8:
Measured with the positive supplies tied to the same potential, VCCA = VCCD = VCCI. VCCvaries from +4.75V to +5.25V.
Note 9:
VEEvaries from -5.25V to -4.75V.
Note 10:
Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power
supply voltage, expressed in dB.
Note 11:
Effective number of bits (ENOB) and signal-to-noise plus distortion (SINAD) are computed from a curve fit referenced to the
theoretical full-scale range.
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Typical Operating Characteristics

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other-
wise noted.)
Note 12:
Total harmonic distortion (THD) is computed from the first five harmonics.
Note 13:
Guaranteed by design with a reset pulse width of one clock period or longer.
Note 14:
The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the DREADY signal (when
the output data changes) to the 50% point on a data output bit. This places the falling edge of the DREADY signal in the
middle of the data output valid window, within the differences between the DREADY and DATA rise and fall times, which
gives maximum setup and hold time for latching external data latches.
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other-
wise noted.)
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifierypical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other-
wise noted.)
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Pin Description
Typical Operating Characteristics (continued)

(VCCA = VCCI = VCCD = +5.0V, VEE= -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS= 600Msps, TA= +25°C, unless other-
wise noted.)
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Pin Description (continued)
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Pin Description (continued)
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Detailed Description

The MAX106 is an 8-bit, 600Msps flash ADC with on-
chip T/H amplifier and differential PECL-compatible
outputs. The ADC (Figure 1) employs a fully differential
8-bit quantizer and a unique encoding scheme to limit
metastable states to typically one error per 1027clock
cycles, with no error exceeding 1LSB max.
An integrated 8:16 output demultiplexer simplifies inter-
facing to the part by reducing the output data rate to
one-half the sampling clock rate. This demultiplexer
has internal reset capability that allows multiple
MAX106s to be time-interleaved to achieve higher
effective sampling rates.
When clocked at 600Msps, the MAX106 provides a typ-
ical effective number of bits (ENOB) of 7.6 bits at an
analog input frequency of 300MHz. The analog input of
the MAX106 is designed for differential or single-ended
use with a ±250mV full-scale input range. In addition,
this fast ADC features an on-board +2.5V precision
bandgap reference. If desired, an external reference
can also be used.
Figure 1. Simplified Functional Diagram
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Principle of Operation

The MAX106’s flash or parallel architecture provides
the fastest multibit conversion of all common integrated
ADC designs. The key to this high-speed flash archi-
tecture is the use of an innovative, high-performance
comparator design. The flash converter and down-
stream logic translate the comparator outputs into a
parallel 8-bit output code and pass this binary code on
to the optional 8:16 demultiplexer, where primary and
auxiliary ports output PECL-compatible data at up to
300Msps per port (depending on how the demultiplex-
er section is set on the MAX106). The ideal transfer
function appears in Figure 2.
On-Chip Track/Hold Amplifier

As with all ADCs, if the input waveform is changing
rapidly during conversion, ENOB and signal-to-noise
ratio (SNR) specifications will degrade. The MAX106’s
on-chip, wide-bandwidth (2.2GHz) T/H amplifier reduces
this effect and increases the ENOB performance signifi-
cantly, allowing precise capture of fast analog data at
high conversion rates.
The T/H amplifier buffers the input signal and allows a
full-scale signal input range of ±250mV. The T/H ampli-
fier’s differential 50Ωinput termination simplifies inter-
facing to the MAX106 with controlled impedance lines.
Figure 3 shows a simplified diagram of the T/H amplifier
stage internal to the MAX106.
Aperture width, delay, and jitter (or uncertainty) are
parameters that affect the dynamic performance of
high-speed converters. Aperture jitter, in particular,
directly influences SNR and limits the maximum slew
rate (dV/dt) that can be digitized without a significant
contribution of errors. The MAX106’s innovative T/H
amplifier design typically limits aperture jitter to less
than 0.5ps.
Aperture Width

Aperture width (tAW) is the time the T/H circuit requires
(Figure 4) to disconnect the hold capacitor from the
input circuit (for instance to turn off the sampling bridge
and put the T/H unit in hold mode).
Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation
(Figure 4) in the time between the samples.
Aperture Delay

Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 4).
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Internal Reference

The MAX106 features an on-chip +2.5V precision
bandgap reference that can be used by connecting
REFOUT to REFIN. This connects the reference output
to the positive input of the reference buffer. The buffer’s
negative input is internally tied to GNDR. GNDR must
be connected to GNDI on the user’s application board.
REFOUT can source up to 2.5mA to supply external
devices if required.
An adjustable external reference can be used to adjust
the ADC’s full-scale range. To use an external refer-
ence supply, connect a high-precision reference to the
REFIN pin and leave the REFOUT pin floating. In this
configuration, REFOUT must notbe simultaneously
connected at any time, to avoid conflicts between the
two references. REFIN has a typical input resistance of
5kΩand accepts input voltages of +2.5V ±200mV.
Using the MAX106’s internal reference is recommend-
ed for best performance.
Digital Outputs

The MAX106 provides data in offset binary format to dif-
ferential PECL outputs. A simplified circuit schematic of
the PECL output cell is shown in Figure 5. All PECL out-
puts are powered from VCCO, which may be operated
from any voltage between +3.0V to VCCD for flexible
interfacing with either +3.3V or +5V systems. The nomi-
nal VCCO supply voltage is +3.3V.
All PECL outputs on the MAX106 are open-emitter
types and must be terminated at the far end of each
transmission line with 50Ωto VCCO - 2V. Table 1 lists all
MAX106 PECL outputs and their functions.
Demultiplexer Operation

The MAX106 features an internal data demultiplexer,
which provides for three different modes of operation
(see the following sections on Demultiplexed DIV2
Mode, Non-Demultiplexed DIV1 Mode, and Decimation
DIV4 Mode) controlled by two TTL/CMOS-compatible
inputs: DEMUXEN and DIVSELECT.
DEMUXEN enables or disables operation of the internal
1:2 demultiplexer. A logic high on DEMUXEN activates
the internal demultiplexer, and a logic low deactivates
it. With the internal demultiplexer enabled, DIVSELECT
controls the selection of the operational mode. DIVSE-
LECT low selects demultiplexed DIV2 mode, and DIV-
SELECT high selects decimation DIV4 mode (Table 2).
Table 1. PECL Output Functions
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Non-Demultiplexed DIV1 Mode

The MAX106 may be operated at up to the full sam-
pling rate (600Msps) in non-demultiplexed DIV1 mode
(Table 2). In this mode, the internal demultiplexer is dis-
abled and sampled data is presented to the primary
port only, with the data repeated at the auxiliary port,
but delayed by one clock cycle (Figure 6). Since the
auxiliary output port contains the same data stream as
the primary output port, the auxiliary port can be shut
down to save power by connecting AUXEN1 and
AUXEN2 to digital ground (GNDD). This powers down
the internal bias cells and causes both outputs (true
and complementary) of the auxiliary port to pull up to a
logic-high level. To save additional power, the external
50Ωtermination resistors connected to the PECL termi-
nation power supply (VCCO - 2V) may be removed from
all auxiliary output ports.
Demultiplexed DIV2 Mode

The MAX106 features an internally selectable DIV2
mode (Table 2) that reduces the output data rate to
one-half of the sample clock rate. The demultiplexed
outputs are presented in dual 8-bit format with two con-
secutive samples appearing in the primary and auxil-
iary output ports on the rising edge of the data-ready
clock (Figure 7). The auxiliary data port contains the
previous sample, and the primary output contains the
most recent data sample. AUXEN1 and AUXEN2 must
be connected to VCCO to power up the auxiliary port
PECL output drives.
Figure 6. Non-Demuxed, DIV1-Mode Timing Diagram
MAX106
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
Decimation DIV4 Mode

The MAX106 also offers a special decimated, demulti-
plexed output (Figure 8) that discards every other input
sample and outputs data at one-quarter the input sam-
pling rate for system debugging at slower output data
rates. With an input clock of 600MHz, the effective out-
put data rate will be reduced to 150MHz per output port
in the DIV4 mode (Table 2). Since every other sample is
discarded, the effective sampling rate is 300Msps.
Overrange Operation

A single differential PECL overrange output bit (OR+,
OR-) is provided for both primary and auxiliary demulti-
plexed outputs. The operation of the overrange bit
depends on the status of the internal demultiplexer. In
demultiplexed DIV2 mode and decimation DIV4 mode,
the OR bit will flag an overrange condition if either the
primary or auxiliary port contains an overranged sam-
ple (Table 2). In non-demultiplexed DIV1 mode, the OR
port will flag an overrange condition only when the pri-
mary output port contains an overranged sample.
Applications Information
Single-Ended Analog Inputs

The MAX106 T/H amplifier is designed to work at full
speed for both single-ended and differential analog
inputs (Figure 9). Inputs VIN+ and VIN- feature on-chip,
laser-trimmed 50Ωtermination resistors to provide
excellent voltage standing-wave ratio (VSWR) perfor-
mance.
Table 2. Demultiplexer Operation

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