MAX1057BETM+ ,10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsFeaturesage from +2.7V to +3.6V (MAX1057) and from +4.75V to+5.25V (MAX1020/MAX1022/MAX1058). The d ..
MAX1058BETM+ ,10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO PortsFeatures such as an internal ±1°C accurate temperaturesensor, FIFO, scan modes, programmable intern ..
MAX105ECS ,Dual / 6-Bit / 800Msps ADC with On-Chip / Wideband Input AmplifierFeaturesThe MAX105 is a dual, 6-bit, analog-to-digital converter Two Matched 6-Bit, 800Msps ADCs(A ..
MAX105ECS+ ,Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input AmplifierFeaturesThe MAX105 is a dual, 6-bit, analog-to-digital converter♦ Two Matched 6-Bit, 800Msps ADCs(A ..
MAX1062ACUB+ ,14-Bit, +5V, 200ksps ADC with 10µA ShutdownELECTRICAL CHARACTERISTICS(AV = DV = +4.75V to +5.25V, f = 4.8MHz (50% duty cycle), 24 clocks/conve ..
MAX1062BCUB+ ,14-Bit, +5V, 200ksps ADC with 10µA Shutdownfeatures a separate digital supply, allowingdirect interfacing with 2.7V to 5.25V digital logic.♦ I ..
MAX338CEE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersGeneral DescriptionThe MAX338/MAX339 are monolithic, CMOS analog♦ On-Resistance, <400Ω maxmultiplex ..
MAX338CPE ,8-channel, low-leakage, CMOS analog multiplexer.ApplicationsMAX338MJE -55°C to +125°C 16 CERDIP**Data-Acquisition Systems Sample-and-Hold CircuitsO ..
MAX338CPE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersApplications (5mm x 5mm)Data-Acquisition Systems Sample-and-Hold CircuitsOrdering Information conti ..
MAX338CSE ,8-channel, low-leakage, CMOS analog multiplexer.MAX338/MAX33919-0272; Rev 0; 8/948-Channel/Dual 4-Channel,Low-Leakage, CMOS Analog Multiplexers____ ..
MAX338CSE+ ,8-Channel/Dual 4-Channel, Low-Leakage, CMOS Analog MultiplexersELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = +15V, V- = -15V, V = 0V, V = +2.4V, V = +0.8V, T = T ..
MAX338EPE ,8-channel, low-leakage, CMOS analog multiplexer.FeaturesThe MAX338/MAX339 are monolithic, CMOS analog' On-Resistance, <400Ω maxmultiplexers (muxes) ..
MAX1020BETX+-MAX1022BETX+-MAX1057BETM+-MAX1058BETM+
10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports
General DescriptionThe MAX1020/MAX1022/MAX1057/MAX1058 integrate a
multichannel, 10-bit, analog-to-digital converter (ADC)and an octal, 10-bit, digital-to-analog converter (DAC) in a
single IC. These devices also include a temperature sen-sor and configurable general-purpose I/O ports (GPIOs)
with a 25MHz SPI-/QSPI™-/MICROWIRE®-compatible
serial interface. The ADC is available in 8/12/16 input-channel versions. The octal DAC outputs settle within
2.0µs, and the ADC has a 225ksps conversion rate.
All devices include an internal reference (2.5V or 4.096V)
providing a well-regulated, low-noise reference for boththe ADC and DAC. Programmable reference modes for
the ADC and the DAC allow the use of an internal refer-ence, an external reference, or a combination of both.
Features such as an internal ±1°C accurate temperature
sensor, FIFO, scan modes, programmable internal or external clock modes, data averaging, and
AutoShutdown™ allow users to minimize both power con-sumption and processor requirements. The low glitch
energy (4nV•s) and low digital feedthrough (0.5nV•s) of
the integrated octal DACs make these devices ideal fordigital control of fast-response closed-loop systems.
The devices are guaranteed to operate with a supply volt-
age from +2.7V to +3.6V (MAX1057) and from +4.75V to
+5.25V (MAX1020/MAX1022/MAX1058). The devicesconsume 2.5mA at 225ksps throughput, only 22µA at
1ksps throughput, and under 0.2µA in the shutdownmode. The MAX1057/MAX1058 feature 12 GPIOs, while
the MAX1020 offers four GPIOs that can be configured as
inputs or outputs.
The MAX1057/MAX1058 are available in 48-pin thin QFNpackages. The MAX1020/MAX1022 are available in 36-
pin thin QFN packages. All devices are specified over the
-40°C to +85°C temperature range.
ApplicationsControls for Optical Components
Base-Station Control Loops
System Supervision and Control
Data-Acquisition Systems
Features10-Bit, 225ksps ADCAnalog Multiplexer with True-Differential
Track/Hold (T/H)16 Single-Ended Channels or 8 Differential
Channels (Unipolar or Bipolar)(MAX1057/MAX1058)
12 Single-Ended Channels or 6 DifferentialChannels (Unipolar or Bipolar) (MAX1022)
8 Single-Ended Channels or 4 DifferentialChannels (Unipolar or Bipolar) (MAX1020)
Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB DNL10-Bit, Octal, 2µs Settling DACUltra-Low Glitch Energy (4nV•s)
Power-Up Options from Zero Scale or Full ScaleExcellent Accuracy: ±1 LSB INLInternal Reference or External Single-Ended/
Differential ReferenceInternal Reference Voltage 2.5V or 4.096VInternal ±1°C Accurate Temperature SensorOn-Chip FIFO Capable of Storing 16 ADC
Conversion Results and One Temperature ResultOn-Chip Channel-Scan Mode and Internal Data-Averaging FeaturesAnalog Single-Supply Operation
+2.7V to +3.6V or +4.75V to +5.25VDigital Supply: 2.7V to VAVDD25MHz, SPI/QSPI/MICROWIRE Serial InterfaceAutoShutdown Between ConversionsLow-Power ADC
2.5mA at 225ksps22µA at 1ksps
0.2µA at ShutdownLow-Power DAC: 1.5mAEvaluation Kit Available (Order MAX1258EVKIT)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Ordering Information/Selector Guide19-3280; Rev 5; 2/12
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGE
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS**
ADC
CHANNELS
DAC
CHANNELSGPIOs
MAX1020BETX-40°C to +85°C36 TQFN-EP*4.0964.75 to 5.2510884
MAX1022BETX-40°C to +85°C36 TQFN-EP*4.0964.75 to 5.25101280
MAX1057BETM-40°C to +85°C48 TQFN-EP*2.52.7 to 3.61016812
MAX1058BETM-40°C to +85°C48 TQFN-EP*4.0964.75 to 5.251016812
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor
Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
*EP = Exposed pad.
**Number of resolution bits refers to both DAC and ADC.
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VAVDD= VDVDD= 2.7V to 3.6V (MAX1057), external reference VREF= 2.5V (MAX1057), VAVDD= VDVDD= 4.75V to 5.25V
(MAX1020/MAX1022/MAX1058), external reference VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle),
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1057), VAVDD= VDVDD= 5V
(MAX1020/MAX1022/MAX1058), TA= +25°C. Outputs are unloaded, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
DVDD to AVDD......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND........................-0.3V to (VDVDD + 0.3V)
Analog Inputs, Analog Outputs and REF_
to AGND.............................................-0.3V to (VAVDD + 0.3V)
Maximum Current into Any Pin (except AGND, DGND, AVDD,
DVDD, and OUT_)...........................................................50mA
Maximum Current into OUT_.............................................100mA
Continuous Power Dissipation (multilayer board, TA= +70°C)
36-Pin TQFN (6mm x 6mm)
(derate 35.7mW/°C above +70°C)......................2857.1mW
48-Pin TQFN (7mm x 7mm)
(derate 40mW/°C above +70°C)............................3200mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ADC
DC ACCURACY (Note 1)Resolution10Bits
Integral NonlinearityINL±0.5±1.0LSB
Differential NonlinearityDNL±0.5±1.0LSB
Offset Error±0.25±2.0LSB
Gain Error(Note 2)±0.025±2.0LSB
Gain Temperature Coefficient±1.4ppm/°C
Channel-to-Channel Offset±0.1LSB
YN A M IC SPEC IF I C A T IO N S ( 1 0 k H z s in e - w a v e in p u t , VIN = 2 .5 VP- P ( M A X1 0 5 7 ) , VIN = 4 .0 9 6 VP- P ( M A X1 0 2 0 /M A X1 0 2 2 /M A X1 0 5 8 ) , 2 5 k s p s , f SC LK = 3 .6 M H z) Signal-to-Noise Plus DistortionSINAD61dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)THD-70dBc
Spurious-Free Dynamic RangeSFDR66dBc
Intermodulation DistortionIMDfIN1 = 9.9kHz, fIN2 = 10.2kHz72dBc
Full-Linear BandwidthSINAD > 70dB100kHz
Full-Power Bandwidth-3dB point1MHz
CONVERSION RATE (Note 3)External reference0.8µs
Power-Up TimetPUInternal reference (Note 4)218onver si onl ock
Note:If the package power dissipation is not exceeded, one output at a time may be shorted to AVDD, DVDD, AGND, or DGND
indefinitely
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VDVDD= 2.7V to 3.6V (MAX1057), external reference VREF= 2.5V (MAX1057), VAVDD= VDVDD= 4.75V to 5.25V
(MAX1020/MAX1022/MAX1058), external reference VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle),
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1057), VAVDD= VDVDD= 5V
(MAX1020/MAX1022/MAX1058), TA= +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSAcquisition TimetACQ(Note 5)0.6µs
Internally clocked5.5Conversion TimetCONVExternally clocked3.6µs
External Clock FrequencyfCLKExternally clocked conversion (Note 5)0.13.6MHz
Duty Cycle4060%
Aperture Delay30ns
Aperture Jitter< 50ps
ANALOG INPUTSUnipolar0VREFInput Voltage Range (Note 6)Bipolar-VREF / 2VREF / 2V
Input Leakage Current±0.01±1µA
Input Capacitance24pF
INTERNAL TEMPERATURE SENSORTA = +25°C±0.7Measurement Error (Notes 5, 7)TA = TMIN to TMAX±1.0±3.0°C
Temperature Resolution1/8°C/LSB
INTERNAL REFERENCEMAX10572.4822.502.518REF1 Output Voltage (Note 8)MAX1020/MAX1022/MAX10584.0664.0964.126V
REF1 Voltage Temperature
CoefficientTCREF±30ppm/°C
REF1 Output Impedance6.5kΩ
VREF = 2.5V0.39REF1 Short-Circuit CurrentVREF = 4.096V0.63mA
EXTERNAL REFERENCEREF1 Input Voltage RangeVREF1REF mode 11 (Note 4)1VAVDD
+ 0.05V
REF mode 011VAVDD
+ 0.05REF2 Input Voltage Range
(Note 4)VREF2
REF mode 1101
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VDVDD= 2.7V to 3.6V (MAX1057), external reference VREF= 2.5V (MAX1057), VAVDD= VDVDD= 4.75V to 5.25V
(MAX1020/MAX1022/MAX1058), external reference VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle),
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1057), VAVDD= VDVDD= 5V
(MAX1020/MAX1022/MAX1058), TA= +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVREF = 2.5V (MAX1057), fSAMPLE =
225ksps2580
VREF = 4.096V
(MAX1020/MAX1022/MAX1058),
fSAMPLE = 225ksps80REF1 Input Current (Note 9)IREF1
Acquisition between conversions±0.01±1
VREF = 2.5V (MAX1057), fSAMPLE =
225ksps2580
VREF = 4.096V
(MAX1020/MAX1022/MAX1058),
fSAMPLE = 225ksps80REF2 Input CurrentIREF2
Acquisition between conversions±0.01±1
DAC
DC ACCURACY (Note 10)Resolution10Bits
Integral NonlinearityINL±0.5±1LSB
Differential NonlinearityDNLGuaranteed monotonic±0.5LSB
Offset ErrorVOS(Note 8)±3±10mV
Offset-Error Drift±10ppm of
FS/°C
Gain ErrorGE(Note 8)±1.25±10LSB
Gain Temperature Coefficient±8ppm of
FS/°C
DAC OUTPUTNo load0.02VAVDD -
Output-Voltage Range
10kΩ load to either rail0.1VAVDD -
DC Output Impedance0.5Ω
Capacitive Load(Note 11)1nF
VAVDD = 2.7V, VREF = 2.5V (MAX1057),
gain error < 1%2000
Resistive Load to AGNDRLVAVDD = 4.75V, VREF = 4.096V
(MAX1020/MAX1022/MAX1058),
gain error < 2%
500
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VDVDD= 2.7V to 3.6V (MAX1057), external reference VREF= 2.5V (MAX1057), VAVDD= VDVDD= 4.75V to 5.25V
(MAX1020/MAX1022/MAX1058), external reference VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle),
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1057), VAVDD= VDVDD= 5V
(MAX1020/MAX1022/MAX1058), TA= +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSFrom power-down mode, VAVDD = 5V25Wake-Up Time (Note 12)From power-down mode, VAVDD = 2.7V21µs
1kΩ Output TerminationProgrammed in power-down mode1kΩ
100kΩ Output TerminationAt wake-up or programmed in
power-down mode100kΩ
DYNAMIC PERFORMANCE (Notes 5, 13)Output-Voltage Slew RateSRPositive and negative3V/µs
Output-Voltage Settling TimetSTo 1 LSB, 400 - C00 hex (Note 7)25µs
Digital FeedthroughCode 0, all digital inputs from 0 to VDVDD0.5nV•s
Major Code Transition Glitch
ImpulseBetween codes 2047 and 20484nV•s
From VREF660Output Noise (0.1Hz to 50MHz)Using internal reference720µVP-P
From VREF260Output Noise (0.1Hz to 500kHz)Using internal reference320µVP-P
DAC-to-DAC Transition
Crosstalk0.5nV•s
INTERNAL REFERENCEMAX10572.4822.502.518REF1 Output Voltage (Note 8)MAX1020/MAX1022/MAX10584.0664.0964.126V
REF1 Temperature CoefficientTCREF±30ppm/°C
VREF = 2.5V0.39REF1 Short-Circuit CurrentVREF = 4.096V0.63mA
EXTERNAL-REFERENCE INPUTREF1 Input Voltage RangeVREF1REF modes 01, 10, and 11 (Note 4)0.7VAVDDV
REF1 Input ImpedanceRREF170100130kΩ
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)Input-Voltage HighVIHVDVDD = 2.7V to 5.25V2.4V
VDVDD = 3.6V to 5.25V0.8Input-Voltage LowVILVDVDD = 2.7V to 3.6V0.6V
Input Leakage CurrentIL±0.01±10µA
Input CapacitanceCIN15pF
DIGITAL OUTPUT (DOUT) (Note 14)Output-Voltage LowVOLISINK = 2mA0.4V
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VDVDD= 2.7V to 3.6V (MAX1057), external reference VREF= 2.5V (MAX1057), VAVDD= VDVDD= 4.75V to 5.25V
(MAX1020/MAX1022/MAX1058), external reference VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle),
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1057), VAVDD= VDVDD= 5V
(MAX1020/MAX1022/MAX1058), TA= +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput-Voltage HighVOHISOURCE = 2mAVDVDD -
0.5V
Tri-State Leakage Current±10µA
Tri-State Output CapacitanceCOUT15pF
DIGITAL OUTPUT (EOC) (Note 14)Output-Voltage LowVOLISINK = 2mA0.4V
Output-Voltage HighVOHISOURCE = 2mAVDVDD -
0.5V
Tri-State Leakage Current±10µA
Tri-State Output CapacitanceCOUT15pF
DIGITAL OUTPUTS (GPIO_) (Note 14)ISINK = 2mA0.4GPIOB_, GPIOC_ Output-
Voltage LowISINK = 4mA0.8V
GPIOB_, GPIOC_ Output-
Voltage HighISOURCE = 2mAVDVDD -
0.5V
GPIOA_ Output-Voltage LowISINK = 15mA0.8V
GPIOA_ Output-Voltage HighISOURCE = 15mAVDVDD -
0.8V
Tri-State Leakage Current±10µA
Tri-State Output CapacitanceCOUT15pF
POWER REQUIREMENTS (Note 15)Digital Positive-Supply VoltageVDVDD2.70VAVDDV
Idle, all blocks shut down0.24µADigital Positive-Supply CurrentDIDDOnly ADC on, external reference1mA
MAX10572.73.6Analog Positive-Supply VoltageVAVDDMAX1020/MAX1022/MAX10584.755.25V
Idle, all blocks shut down0.22µA
fSAMPLE = 225ksps2.84.2Only ADC on,
external referencefSAMPLE = 100ksps2.6Analog Positive Supply CurrentAIDD
All DACs on, no load, internal reference1.54.0
VAVDD = 2.7V, MAX1057-77
REF1 Positive-Supply RejectionPSRRVAVDD = 4.75V
MAX1020/MAX1022/MAX1058-80dB
MAX1057, VAVDD = 2.7V to 3.6V±0.1±0.5
DAC Positive-Supply RejectionPSRD
Output
code =
FFFhexAX 1020/M AX 1022/M AX 1058,
VAVDD = 4.75V to 5.25V ±0.1±0.5mV
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VDVDD= 2.7V to 3.6V (MAX1057), external reference VREF= 2.5V (MAX1057), VAVDD= VDVDD= 4.75V to 5.25V
(MAX1020/MAX1022/MAX1058), external reference VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle),
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1057), VAVDD= VDVDD= 5V
(MAX1020/MAX1022/MAX1058), TA= +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSMAX1057, VAVDD = 2.7V to±0.06±0.5
ADC Positive-Supply RejectionPSRA
Full-
scale
inputAX 1020/M AX 1022/M AX 1058,
VAVDD = 4.75V to 5.25V ±0.06±0.5mV
TIMING CHARACTERISTICS (Figures 6–13)SCLK Clock PeriodtCP40ns
SCLK Pulse-Width HightCH40/60 duty cycle16ns
SCLK Pulse-Width LowtCL60/40 duty cycle16ns
GPIO Output Rise/Fall After
CS RisetGODCLOAD = 20pF100ns
GPIO Input Setup Before CS FalltGSU0ns
LDAC Pulse WidthtLDACPWL20ns
CLOAD = 20pF, SLOW = 01.812.0SCLK Fall to DOUT Transition
(Note 16)tDOTCLOAD = 20pF, SLOW = 11040ns
CLOAD = 20pF, SLOW = 01.812.0SCLK Rise to DOUT Transition
(Notes 16, 17)tDOTCLOAD = 20pF, SLOW = 11040ns
CS Fall to SCLK Fall Setup TimetCSS10nsC LK Fal l to CS Ri se S etup Ti m etCSH0ns
DIN to SCLK Fall Setup TimetDS10ns
DIN to SCLK Fall Hold TimetDH02000ns
CS Pulse-Width HightCSPWH50ns
CS Rise to DOUT DisabletDODCLOAD = 20pF25ns
CS Fall to DOUT EnabletDOECLOAD = 20pF1.525.0ns
EOC Fall to CS FalltRDS30ns
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
CKSEL = 01 (voltage conversion)9
CKSEL = 10 (voltage conversion),
internal reference on9
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
tDOV
CKSEL = 10 (voltage conversion),
internal reference initially off80
CKSEL = 00, CKSEL = 01 (temp sense)40nsCNVST Pulse WidthtCSWCKSEL = 01 (voltage conversion)1.4µs
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)(VAVDD= VDVDD= 2.7V to 3.6V (MAX1057), external reference VREF= 2.5V (MAX1057), VAVDD= VDVDD= 4.75V to 5.25V
(MAX1020/MAX1022/MAX1058), external reference VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle),
TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVDD= VDVDD= 3V (MAX1057), VAVDD= VDVDD= 5V
(MAX1020/MAX1022/MAX1058), TA= +25°C. Outputs are unloaded, unless otherwise noted.)
Note 1:Tested at VDVDD= VAVDD= +3.6V (MAX1057), VDVDD= VAVDD= +5.25V (MAX1020/MAX1022/MAX1058).
Note 2:Offset nulled.
Note 3:No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Note 4:See Table 5 for reference-mode details.
Note 5:Not production tested. Guaranteed by design.
Note 6:See the ADC/DAC Referencessection.
Note 7:Fast automated test, excludes self-heating effects.
Note 8:Specified over the -40°C to +85°C temperature range.
Note 9:REFSEL[1:0] = 00 and when DACs are not powered up.
Note 10:DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11:The DAC buffers are guaranteed by design to be stable with a 500pF load.
Note 12:Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13:All DAC dynamic specifications are valid for a load of 1nF and 10kΩ.
Note 14:Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15:All digital inputs at either VDVDDor DGND. VDVDDshould not exceed VAVDD.
Note 16:See the Reset Registersection and Table 9 for details on programming the SLOW bit.
Note 17:Clock mode 11 only.
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO PortsANALOG SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1020 toc01
SUPPLY VOLTAGE (V)
ANALOG SHUTDOWN CURRENT (
MAX1020/MAX1022/MAX1058
ANALOG SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX1020 toc02
SUPPLY VOLTAGE (V)
MAX1057
ANALOG SHUTDOWN CURRENT (
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
ANALOG SHUTDOWN CURRENT (
MAX1020/MAX1022/MAX1058
MAX1057
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1020 toc04
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
MAX1020/MAX1022/MAX1058
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1020 toc05
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
MAX1057
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODEMAX1020 toc06
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
MAX1020/MAX1022/MAX1058
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODEMAX1020 toc07
DIFFERENTIAL NONLINEARITY (LSB)
MAX1057
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc08
OFFSET ERROR (LSB)
MAX1020/MAX1022/MAX1058
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc09
MAX1057
OFFSET ERROR (LSB)
Typical Operating Characteristics(VAVDD= VDVDD= 3V (MAX1057), external VREF= 2.5V (MAX1057), VAVDD= VDVDD= 5V (MAX1020/MAX1022/MAX1058), external
VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capaci-
tor at REF, TA= +25°C, unless otherwise noted.)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO PortsADC OFFSET ERROR
vs. TEMPERATURE
MAX1020 toc10
OFFSET ERROR (LSB)
MAX1020/MAX1022/MAX1058
MAX1057
TEMPERATURE (°C)
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc11
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
MAX1020/MAX1022/MAX1058
ADC GAIN ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc12
SUPPLY VOLTAGE (V)
GAIN ERROR (LSB)
ADC GAIN ERROR
vs. TEMPERATURE
MAX1020 toc13
TEMPERATURE (°C)
GAIN ERROR (LSB)
MAX1020/MAX1022/MAX1058
MAX1057
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATEMAX1020 toc14
SAMPLING RATE (ksps)
ADC EXTERNAL REFERENCE INPUT CURRENT (
MAX1020/MAX1022/MAX1058
MAX1057
ANALOG SUPPLY CURRENT
vs. SAMPLING RATEMAX1020 toc15
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT (mA)
MAX1020/MAX1022/MAX1058
MAX1057
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc16
SUPPLY CURRENT (mA)
MAX1020/MAX1022/MAX1058
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc17
MAX1057
SUPPLY CURRENT (mA)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1020 toc18
ANALOG SUPPLY CURRENT (mA)
MAX1020/MAX1022/MAX1058
MAX1057
ypical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1057), external VREF= 2.5V (MAX1057), VAVDD= VDVDD= 5V (MAX1020/MAX1022/MAX1058), external
VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capaci-
tor at REF, TA= +25°C, unless otherwise noted.)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1020 toc19
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
MAX1020/MAX1022/MAX1058
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODEMAX1020 toc20
OUTPUT CODE
INTEGRAL NONLINEARITY (LSB)
MAX1057
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODEOUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
MAX1020/MAX1022/MAX1058
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODEMAX1020 toc22
OUTPUT CODE
DIFFERENTIAL NONLINEARITY (LSB)
MAX1057
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc23
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
MAX1020/MAX1022/MAX1058
EXTERNAL REFERENCE = 4.096V
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc24
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
MAX1057
EXTERNAL REFERENCE = 2.5V
DAC FULL-SCALE ERROR
vs. TEMPERATURE
MAX1020 toc25
DAC FULL-SCALE ERROR (LSB)-153560
EXTERNAL REFERENCE = 4.096V
MAX1020/MAX1022/MAX1058
INTERNAL REFERENCE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
MAX1020 toc26
DAC FULL-SCALE ERROR (LSB)-153560
EXTERNAL REFERENCE = 2.5V
MAX1057
INTERNAL REFERENCE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGEMAX1020 toc27
DAC FULL-SCALE ERROR (LSB)312
MAX1020/MAX1022/MAX1058
ypical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1057), external VREF= 2.5V (MAX1057), VAVDD= VDVDD= 5V (MAX1020/MAX1022/MAX1058), external
VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capaci-
tor at REF, TA= +25°C, unless otherwise noted.)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGEMAX1020 toc28
REFERENCE VOLTAGE (V)
DAC FULL-SCALE ERROR (LSB)
MAX1057
DAC FULL-SCALE ERROR
vs. LOAD CURRENTMAX1020 toc29
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR (LSB)2015105
MAX1020/MAX1022/MAX1058
DAC FULL-SCALE ERROR
vs. LOAD CURRENTMAX1020 toc30
LOAD CURRENT (mA)
DAC FULL-SCALE ERROR (LSB)
MAX1057
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1020 toc31
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
MAX1020/MAX1022/MAX1058
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1020 toc32
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE (V)
MAX1057
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc33
SUPPLY VOLTAGE (V)
ADC REFERENCE SUPPLY CURRENT (
MAX1020/MAX1022/MAX1058
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1020 toc34
ADC REFERENCE SUPPLY CURRENT (
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
MAX1020 toc35
ADC REFERENCE SUPPLY CURRENT (
MAX1020/MAX1022/MAX1058,
EXTERNAL REFERENCE = 4.096V
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
MAX1020 toc36
ADC REFERENCE SUPPLY CURRENT (
MAX1057, EXTERNAL REFERENCE = 2.5V
ypical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1057), external VREF= 2.5V (MAX1057), VAVDD= VDVDD= 5V (MAX1020/MAX1022/MAX1058), external
VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capaci-
tor at REF, TA= +25°C, unless otherwise noted.)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
ADC FFT PLOTMAX1020 toc37
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fSAMPLE = 32.768kHz
fANALOG_)N = 10.080kHz
fCLK = 5.24288MHz
SINAD = 61.21dBc
SNR = 61.21dBc
THD = 73.32dBc
SFDR = 81.25dBc
ADC IMD PLOTMAX1020 toc38
ANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fCLK = 5.24288MHz
fIN1 = 9.0kHz
fIN2 = 11.0kHz
AIN = -6dBFS
IMD = 78.0dBc
ADC CROSSTALK PLOTANALOG INPUT FREQUENCY (kHz)
AMPLITUDE (dB)
fCLK = 5.24288MHz
fIN1 = 10.080kHz
fIN2 = 8.0801kHz
SNR = 61.11dBc
THD = 73.32dBc
ENOB = 9.86 BITS
SFDR = 86.34dBc
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENTMAX1020 toc40
OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)300
DAC OUTPUT = MIDSCALE
MAX1020/MAX1022/MAX1058
SINKING
SOURCING
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENTMAX1020 toc41
OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE (V)100-20-10
DAC OUTPUT = MIDSCALE
MAX1057
SINKING
SOURCING
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENTMAX1020 toc42
SOURCE CURRENT (mA)
GPIO OUTPUT VOLTAGE (V)604020
MAX1020/MAX1022/MAX1058
GPIOA0–A3 OUTPUTS
GPIOB0–B3,
C0–C3 OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENTMAX1020 toc43
GPIO OUTPUT VOLTAGE (V)604020
MAX1057
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SINK CURRENTMAX1020 toc44
GPIO OUTPUT VOLTAGE (mV)604020
MAX1020/MAX1022/MAX1058
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
GPIO OUTPUT VOLTAGE
vs. SINK CURRENTMAX1020 toc45
GPIO OUTPUT VOLTAGE (mV)50302010
MAX1057
GPIOA0–A3 OUTPUTS
GPIOB0–B3, C0–C3
OUTPUTS
ypical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1057), external VREF= 2.5V (MAX1057), VAVDD= VDVDD= 5V (MAX1020/MAX1022/MAX1058), external
VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capaci-
tor at REF, TA= +25°C, unless otherwise noted.)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
TEMPERATURE SENSOR ERROR
vs. TEMPERATUREMAX1020 toc46
TEMPERATURE (°C)
TEMPERATURE SENSOR ERROR (35-1510
DAC-TO-DAC CROSSTALK
RLOAD = 10kΩ, CLOAD = 100pF
MAX1020 toc47
100μs
VOUTA
1V/div
VOUTB
10mV/div
AC-COUPLED
MAX1057
DAC-TO-DAC CROSSTALK
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc48
100μs
VOUTA
2V/div
VOUTB
10mV/div
AC-COUPLED
MAX1020/MAX1022/MAX1058
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc49
1μs
VOUT
1V/div
1V/div
MAX1057
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc50
1μs
VOUT
2V/div
2V/div
MAX1020/MAX1022/MAX1058
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc51
1μs
VOUT
1V/div
1V/div
MAX1057
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc52
VOUT
2V/div
2V/div
MAX1020/MAX1022/MAX1058
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc53
VOUT
10mV/div
AC-COUPLED
1V/div
MAX1057
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc54
VOUT
20mV/div
AC-COUPLED
2V/div
MAX1020/MAX1022/MAX1058
ypical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1057), external VREF= 2.5V (MAX1057), VAVDD= VDVDD= 5V (MAX1020/MAX1022/MAX1058), external
VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capaci-
tor at REF, TA= +25°C, unless otherwise noted.)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
DAC DIGITAL FEEDTHROUGH (RLOAD = 10kΩ,
CLOAD = 100pF, CS = HIGH, DIN = LOW)MAX1020 toc55
200ns
VOUT
100mV/div
AC-COUPLED
SCLK
1V/div
MAX1057
DAC DIGITAL FEEDTHROUGH (RLOAD = 10kΩ,
CLOAD = 100pF, CS = HIGH, DIN = LOW)MAX1020 toc56
200ns
VOUT
100mV/div
AC-COUPLED
SCLK
2V/div
MAX1020/MAX1022/MAX1058
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc57
1μs
VOUT
1V/div
MAX1057
VLDAC
1V/div
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc58
2μs
VOUT_
2V/div
MAX1020/MAX1022/MAX1058
VLDAC
2V/div
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc59
1μs
VOUT_
1V/div
MAX1057
VLDAC
1V/div
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc60
1μs
VOUT_
2V/div
MAX1020/MAX1022/MAX1058
VLDAC
2V/div
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc61
VDAC-OUT
10mV/div
AC-COUPLED
MAX1057
VREF2
1V/div
ADC REFERENCE SWITCHING
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pFMAX1020 toc62
VDAC-OUT
2mV/div
AC-COUPLEDMAX1020/MAX1022/MAX1058
VREF2
2V/div
ADC REFERENCE SWITCHING
ypical Operating Characteristics (continued)(VAVDD= VDVDD= 3V (MAX1057), external VREF= 2.5V (MAX1057), VAVDD= VDVDD= 5V (MAX1020/MAX1022/MAX1058), external
VREF= 4.096V (MAX1020/MAX1022/MAX1058), fCLK = 3.6MHz (50% duty cycle), fSAMPLE= 225ksps, CLOAD= 50pF, 0.1µF capaci-
tor at REF, TA= +25°C, unless otherwise noted.)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Pin Description
MAX1020MAX1022MAX1057/
MAX1058NAMEFUNCTION1, 2——GP IOA0, G P IOA1General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.4EOCActive-Low End-of-Conversion Output. Data is valid after the falling edge
of EOC.47DVDDDigital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF
capacitor.58DGNDDigital Ground. Connect DGND to AGND.69DOUT
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.710SCLK
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%.) See Table 5 for details on programming the
clock mode.811DINSerial-Data Input. DIN data is latched into the serial interface on the
falling edge of SCLK.
9–12,
9–12,
12–15,
22–25OUT0–OUT7DAC Outputs1318AVDDPositive Analog Power Input. Bypass AVDD to AGND with a 0.1µF
capacitor.1419AGNDAnalog Ground
15, 23, 32,
2, 15, 24, 32—N.C.No Connection. Not internally connected.2026LDAC
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.2127CSActive-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.2228RES_SEL
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to
wake up the DAC outputs with a 100kΩ resistor to VREF. Set RES_SEL
high to power up the DAC input register to FFFh. Set RES_SEL low to
power up the DAC input register to 000h.
24, 25——GP IOC 0, G P IOC 1G ener al - P ur p ose I/O C 0, C 1. G P IO C 0, C 1 can si nk 4m A and sour ce 2m A.
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Pin Description (continued)
MAX1020MAX1022MAX1057/
MAX1058NAMEFUNCTION2635REF1
Reference 1 Input. Reference voltage; leave unconnected to use the
internal reference (2.5V for the MAX1057 or 4.096V for the
MAX1020/MAX1022/MAX1058). REF1 is the positive reference in ADC
external differential reference mode. Bypass REF1 to AGND with a 0.1µF
capacitor in external reference mode only. See the ADC/DAC References
section.
27–31, 34——AIN0–AIN5Analog Inputs——REF2/AIN6
Reference 2 Input/Analog-Input Channel 6. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference.——CNVST/AIN7Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details
on programming the setup register.—CNVST/AIN11Active-Low Conversion-Start Input/Analog Input 11. See Table 5 for
details on programming the setup register.
23, 25,
27–31,
33, 34, 35AIN0–AIN9Analog Inputs36—REF2/AIN10
Reference 2 Input/Analog-Input Channel 10. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference.1CNVST/AIN15Active-Low Conversion-Start Input/Analog Input 15. See Table 5 for
details on programming the setup register.2, 3, 5, 6GPIOA0–GPIOA3Gener al - P ur p ose I/O A0–A3. GP IOA0–GP IOA3 can si nk and sour ce 15m A.16, 17,
20, 21GPIOB0–GPIOB3General-Purpose I/O B0–B3. GPIOB0–GPIOB3 can sink 4mA and
source 2mA.—29–32GP IOC 0–GP IOC 3General-Purpose I/O C0–C3. GPIOC0–GPIOC3 can sink 4mA and
source 2mA.33, 34,
36–47AIN0–AIN13Analog Inputs—48REF2/AIN14
Reference 2 Input/Analog-Input Channel 14. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference.—EPExposed Paddle. Must be externally connected to AGND. Do not use as
a ground connect.
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Detailed DescriptionThe MAX1020/MAX1022/MAX1057/MAX1058 integrate
a multichannel, 10-bit ADC and an octal, 10-bit DAC in
a single IC. These devices also include a temperature
sensor and configurable GPIOs with a 25MHz SPI-/
QSPI-/MICROWIRE-compatible serial interface. The
ADC is available in 8/12/16 input-channel versions. The
octal DAC outputs settle within 2.0µs, and the ADC has
a 225ksps conversion rate.
All devices include an internal reference (2.5V or
4.096V) providing a well-regulated, low-noise reference
for both the ADC and DAC. Programmable reference
modes for the ADC and DAC allow the use of an inter-
nal reference, an external reference, or a combination
of both. Features such as an internal ±1°C accurate
temperature sensor, FIFO, scan modes, programmable
internal or external clock modes, data averaging, and
AutoShutdown allow users to minimize both power con-
sumption and processor requirements. The low glitch
energy (4nV•s) and low digital feedthrough (0.5nV•s) of
the integrated octal DACs make these devices ideal for
digital control of fast-response closed-loop systems.
The devices are guaranteed to operate with a supply
voltage from +2.7V to +3.6V (MAX1057) and from
+4.5V to +5.5V (MAX1020/MAX1022/MAX1058), they
consume 25mA at 225ksps throughput, only 22µA at
1ksps throughput, and under 0.2µA in the shutdown
mode. The MAX1057/MAX1058 feature 12 GPIOs, while
the MAX1020 offers four GPIOs that can be configured
as inputs or outputs.
Figure 1 shows the MAX1057/MAX1058 functional dia-
gram. The MAX1020 only includes the GPIOA0, GPIOA1
and GPIOC0, GPIOC1 block. The MAX1022 excludes
the GPIOs. The output-conditioning circuitry takes the
internal parallel data bus and converts it to a serial data
format at DOUT, with the appropriate wake-up timing.
The arithmetic logic unit (ALU) performs the averaging
function.
SPI-Compatible Serial InterfaceThe MAX1020/MAX1022/MAX1057/MAX1058 feature a
serial interface that is compatible with SPI and
MICROWIRE devices. For SPI, ensure the SPI bus mas-
ter (typically a microcontroller (µC)) runs in master
mode so that it generates the serial clock signal. Select
the SCLK frequency of 25MHz or less, and set the
clock polarity (CPOL) and phase (CPHA) in the µC con-
trol registers to the same value. The MAX1020/
MAX1022/MAX1057/MAX1058 operate with SCLK idling
high or low, and thus operate with CPOL = CPHA = 0 or
CPOL = CPHA = 1. Set CSlow to latch any input data
at DIN on the falling edge of SCLK. Output data at
DOUT is updated on the falling edge of SCLK in clock
modes 00, 01, and 10. Output data at DOUT is updated
on the rising edge of SCLK in clock mode 11. See
Figures 6–11. Bipolar true-differential results and tem-
perature-sensor results are available in two’s comple-
ment format, while all other results are in binary.
A high-to-low transition on CSinitiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fast-
interface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
The conversion register controls ADC channel selec-
tion, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC con-
figuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolar-
mode registers. Hold CSlow between the command
byte and the second and third byte. The ADC averag-
ing register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the com-
mand byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interfacesection
and Tables 10, 20, and 21.
Write to the GPIOs (if applicable) by issuing a com-
mand byte to the appropriate register. Writing to the
MAX1020 GPIOs requires 1 additional byte following
the command byte. Writing to the MAX1057/
MAX1058 requires 2 additional bytes following the com-
mand byte. See Tables 12–19 for details on GPIO con-
figuration, writes, and reads. See the GPIO Command
section. Command bytes written to the GPIOs on
devices without GPIOs are ignored.
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO PortsDOUT
EOC
ADDRESS
AIN0
AIN13
REF2/
AIN14
CNVST/
AIN15
REF1
DIN
SCLK
GPIOA0–
GPIOA3
GPIOB0–
GPIOB3
GPIOC0–
GPIOC3
AVDD
SPI
PORT
GPIO
CONTROL
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
10-BIT
DACBUFFER
USER-PROGRAMMABLE
I/O
OSCILLATOROUT0
OUT1
OUT2
OUT4
OUT5
OUT6
MAX1057
MAX1058
10-BIT
SAR
ADC
LOGIC
CONTROL
TEMPERATURE
SENSOR
FIFO AND
ALU
LDACRES_SELAGND
T/H
REF2
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
10-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
10-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
10-BIT
DACBUFFER
INPUT
REGISTER
INTERNAL
REFERENCE
DAC
REGISTER
OUTPUT
CONDITIONING
10-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
10-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
10-BIT
DACBUFFER
INPUT
REGISTER
DAC
REGISTER
OUTPUT
CONDITIONING
10-BIT
DACBUFFER
OUT3
OUT7
DGND
DVDD
CNVST
Figure 1. MAX1057/MAX1058 Functional Diagram
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Table 1. Command Byte (MSB First)
REGISTER NAMEBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0Conversion1CHSEL3CHSEL2CHSEL1CHSEL0SCAN1SCAN0TEMP
Setup01CKSEL1CKSEL0REFSEL1REFSEL0DIFFSEL1DIFFSEL0
ADC Averaging001AVGONNAVG1NAVG0NSCAN1NSCAN0
DAC Select0001XXXX
Reset00001RESETSLOWFBGON
GPIO Configure*00000011
GPIO Write*00000010
GPIO Read*00000001
No Operation00000000
X = Don’t care.
*Only applicable on the MAX1020/MAX1057/MAX1058.
Power-Up Default StateThe MAX1020/MAX1022/MAX1057/MAX1058 power up
with all blocks in shutdown (including the reference). All
registers power up in state 00000000, except for the
setup register and the DAC input register. The setup
register powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
3FFh when RES_SEL is high and it powers up to 000h
when RES_SEL is low.
10-Bit ADCThe MAX1020/MAX1022/MAX1057/MAX1058 ADCs use
a fully differential successive-approximation register
(SAR) conversion technique and on-chip track-and-
hold (T/H) circuitry to convert temperature and voltage
signals into 10-bit digital results. The analog inputs
accept both single-ended and differential input signals.
Single-ended signals are converted using a unipolar
transfer function, and differential signals are converted
using a selectable bipolar or unipolar transfer function.
See the ADC Transfer Functionssection for more data.
ADC Clock ModesWhen addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request internally timed conver-
sions, without tying up the serial bus. In clock mode 01,
use CNVSTto request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writ-
ing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOCgoes low when the ADC completes the last
requested operation and is waiting for the next com-
mand byte. EOCgoes high when CSor CNVSTgo low.
EOCis always high in clock mode 11.
Single-Ended or Differential ConversionsThe MAX1020/MAX1022/MAX1057/MAX1058 use a fully
differential ADC for all conversions. When a pair of
inputs are connected as a differential pair, each input is
connected to the ADC. When configured in single-
ended mode, the positive input is the single-ended
channel and the negative input is referred to AGND.
See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
AIN14/AIN15. AIN0–AIN7 are available on all devices.
AIN0–AIN11 are available on the MAX1022.
AIN0–AIN15 are available on the MAX1057/MAX1058.
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO Ports
Unipolar or Bipolar ConversionsAddress the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to VREF1.A nega-
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to ±VREF1 / 2. The digital
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
In single-ended mode, the MAX1020/MAX1022/
MAX1057/MAX1058 always operate in unipolar mode.
The analog inputs are internally referenced to AGND
with a full-scale input range from 0 to the selected refer-
ence voltage.
Analog Input (T/H)The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1020/MAX1022/MAX1057/
MAX1058. In track mode, a positive input capacitor is
connected to AIN0–AIN15 in single-ended mode and
AIN0, AIN2, and AIN4–AIN14 (only positive inputs) in
differential mode. A negative input capacitor is con-
nected to AGND in single-ended mode or AIN1, AIN3,
and AIN5–AIN15 (only negative inputs) in differential
mode. For external T/H timing, use clock mode 01. After
the T/H enters hold mode, the difference between the
sampled positive and negative input voltages is con-
verted. The input capacitance charging rate determines
the time required for the T/H to acquire an input signal.
If the input signal’s source impedance is high, the
required acquisition time lengthens.
Any source impedance below 300Ωdoes not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening tACQ (only in clock mode 01) or by placing
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
Input BandwidthThe ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, making it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band of interest.
Analog-Input ProtectionInternal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDD and AGND, allowing
the inputs to swing from (VAGND- 0.3V) to (VAVDD+
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed VAVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
Internal FIFOThe MAX1020/MAX1022/MAX1057/MAX1058 contain a
first-in/first-out (FIFO) buffer that holds up to 16 ADC
results plus one temperature result. The internal FIFO
allows the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros and the LSB followed by 2 sub-bits. After
each falling edge of CS, the oldest available pair of
bytes of data is available at DOUT, MSB first. When the
FIFO is empty, DOUT is zero.
AIN0–AIN15
(SINGLE-ENDED),
AIN0, AIN2,
AIN4–AIN14
(DIFFERENTIAL)
COMPARATOR
HOLDACQ
ACQ
HOLD
ACQ
HOLD
AVDD/2
REF1
AGND
CIN+
CIN-
DAC
AGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5–AIN15
(DIFFERENTIAL)
MAX1020/MAX1022/MAX1057/MAX1058
10-Bit, Multichannel ADCs/DACs with FIFO,emperature Sensing, and GPIO PortsThe first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measure-
ment is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the Temperature
Measurementssection for details on converting the dig-
ital code to a temperature.
10-Bit DACIn addition to the 10-bit ADC, the MAX1020/MAX1022/
MAX1057/MAX1058 also include eight voltage-output,
10-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential nonlin-
earity error. Each DAC has a 2µs settling time and ultra-
low glitch energy (4nV•s). The 10-bit DAC code is
unipolar binary with 1 LSB = VREF / 4096.
DAC Digital InterfaceFigure 1 shows the functional diagram of the MAX1057/
MAX1058. The shift register converts a serial 16-bit word
to parallel data for each input register operating with a
clock rate up to 25MHz. The SPI-compatible digital inter-
face to the shift register consists of CS, SCLK, DIN, and
DOUT. Serial data at DIN is loaded on the falling edge
of SCLK. Pull CSlow to begin a write sequence. Begin a
write to the DAC by writing 0001XXXX as a command
byte. The last 4 bits of the DAC select register are don’t-
care bits. See Table 10. Write another 2 bytes to the
DAC interface register following the command byte to
select the appropriate DAC and the data to be written to
it. See Tables 20 and 21.
The eight double-buffered DACs include an input and a
DAC register. The input registers are directly connect-
ed to the shift register and hold the result of the most
recent write operation. The eight 10-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAClow or by writing the
appropriate DAC command sequence at DIN. See
Table 20. The outputs of the DACs are buffered through
eight rail-to-rail op amps.
The MAX1020/MAX1022/MAX1057/MAX1058 DAC out-
put-voltage range is based on the internal reference or
an external reference. Write to the setup register (see
Table 5) to program the reference. If using an external
voltage reference, bypass REF1 with a 0.1µF capacitor
to AGND. The MAX1057 internal reference is 2.5V. The
MAX1020/MAX1022/MAX1058 internal reference is
4.096V. When using an external reference on any of
these devices, the voltage range is 0.7V to VAVDD.
DAC Transfer FunctionSee Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up ModesThe state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AVDD
or AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩinternal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AVDD to wake up all DAC outputs
at 3FFh. While RES_SEL is high, the 100kΩpullup
resistor pulls the DAC outputs to VREF1and the output
buffers are powered down.
DAC Power-Up ModesSee Table 21 for a description of the DAC power-up
and power-down modes.
GPIOsIn addition to the internal ADC and DAC, the
MAX1057/MAX1058 also provide 12 general-purpose
input/output channels, GPIOA0–GPIOA3, GPIOB0–
GPIOB3, and GPIOC0–GPIOC3. The MAX1020 includes
four GPIO channels (GPIOA0, GPIOA1, GPIOC0,
Table 2. DAC Output Code Table
DAC CONTENTS
MSBLSBANALOG OUTPUT1111111100000001000000000111011100000001⎛⎜⎞⎟VREF1023
1024⎛⎜⎞⎟=+⎛⎜⎞⎟VV
REF
REF512
10242⎛⎜⎞⎟VREF511
1024⎛⎜⎞⎟VREF1
1024⎛⎜⎞⎟VREF513
1024
