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M93C46STN/a27avai16K/8K/4K/2K/1K/256 (X8/X16) SERIAL MICROWIRE BUS EEPROM
M93C46STMicroelectronicsN/a957avai16K/8K/4K/2K/1K/256 (X8/X16) SERIAL MICROWIRE BUS EEPROM
M93C66N/a3000avai16K/8K/4K/2K/1K/256 (X8/X16) SERIAL MICROWIRE BUS EEPROM
M93C86CSI ?N/a4865avai16KBIT, 8KBIT, 4KBIT, 2KBIT, 1KBIT AND 256BIT (X8/X16) SERIAL MICROWIRE BUS EEPROM


M93C86 ,16KBIT, 8KBIT, 4KBIT, 2KBIT, 1KBIT AND 256BIT (X8/X16) SERIAL MICROWIRE BUS EEPROMM93C86, M93C76, M93C66M93C56, M93C46, M93C0616Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or ..
M93C86-BN6 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMFEATURES SUMMARY Industry Standard MICROWIRE Bus Figure 1. Packages Single Supply Voltage:– 4.5 t ..
M93C86-MN3 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMFEATURES SUMMARY Industry Standard MICROWIRE Bus Figure 1. Packages Single Supply Voltage:– 4.5 t ..
M93C86-MN6T ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMFEATURES SUMMARY Industry Standard MICROWIRE Bus Figure 1. Packages Single Supply Voltage:– 4.5 t ..
M93C86-WBN6 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMLogic Diagram . . 4Table 2. Signal Names . . 4Table 3. Memory Size versus Organizatio ..
M93C86-WDW6T ,16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or 16-bit wide) MICROWIRE Serial Access EEPROMLogic Diagram . . 4Table 2. Signal Names . . 4Table 3. Memory Size versus Organizatio ..
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M93C46-M93C66-M93C86
16KBIT, 8KBIT, 4KBIT, 2KBIT, 1KBIT AND 256BIT (X8/X16) SERIAL MICROWIRE BUS EEPROM
1/27February 2003
M93C86, M93C76, M93C66
M93C56, M93C46, M93C06

16Kbit, 8Kbit, 4Kbit, 2Kbit, 1Kbit and 256bit (8-bit or 16-bit wide)
MICROWIRE Serial Access EEPROM
FEATURES SUMMARY
Industry Standard MICROWIRE Bus Single Supply Voltage: 4.5V to 5.5V for M93Cx6 2.5V to 5.5V for M93Cx6-W 1.8V to 5.5V for M93Cx6-R Dual Organization: by Word (x16) or Byte (x8) Programming Instructions that work on: Byte,
Word or Entire Memory Self-timed Programming Cycle with Auto-Erase Ready/Busy Signal During Programming Speed: 1MHz Clock Rate, 10ms Write Time (Current
product, identified by process identification
letter F or M) 2MHz Clock Rate, 5ms Write Time (New
Product, identified by process identification
letter W) Sequential Read Operation Enhanced ESD/Latch-Up Behaviour More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
M93C06 IS “NOT FOR NEW DESIGN”

The M93C06 is still in production, but is not recom-
mended for new designs. Please refer to AN1571
on how to replace the M93C06 by the M93C46 in
your application.
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
SUMMARY DESCRIPTION

These electrically erasable programmable memo-
ry (EEPROM) devices are accessed through a Se-
rial Data Input (D) and Serial Data Output (Q)
using the MICROWIRE bus protocol.
Figure 2. Logic Diagram
Table 1. Signal Names

The memory array organization may be divided
into either bytes (x8) or words (x16) which may be
selected by a signal applied on Organization Se-
lect (ORG). The bit, byte and word sizes of the
memories are as shown in Table 2.
Table 2. Memory Size versus Organization

Note:1. Not for New Design
The M93Cx6 is accessed by a set of instructions,
as summarized in Table 3, and in more detail in
Table 4 to Table 6).
Table 3. Instruction Set for the M93Cx6

A Read Data from Memory (READ) instruction
loads the address of the first byte or word to be
read in an internal address register. The data at
this address is then clocked out serially. The ad-
dress register is automatically incremented after
the data is output and, if Chip Select Input (S) is
held High, the M93Cx6 can output a sequential
stream of data bytes or words. In this way, the
memory can be read as a data stream from eight
to 16384 bits long (in the case of the M93C86), or
continuously (the address counter automatically
rolls over to 00h when the highest address is
reached).
Programming is internally self-timed (the external
clock signal on Serial Clock (C) may be stopped or
left running after the start of a Write cycle) and
does not require an Erase cycle prior to the Write
instruction. The Write instruction writes 8 or 16 bits
at a time into one of the byte or word locations of
the M93Cx6. After the start of the programming cy-
3/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06

cle, a Busy/Ready signal is available on Serial
Data Output (Q) when Chip Select Input (S) is driv-
en High.
An internal Power-on Data Protection mechanism
in the M93Cx6 inhibits the device when the supply
is too low.
Figure 3. DIP, SO and TSSOP Connections

Note:1. See page 21 (onwards) for package dimensions, and how
to identify pin-1. DU = Don’t Use.
Figure 4. 90° Turned-SO Connections

Note:1. See page 24 for package dimensions, and how to identify
pin-1. DU = Don’t Use.
The DU (Don’t Use) pin does not contribute to the
normal operation of the device. It is reserved for
use by STMicroelectronics during test sequences.
The pin may be left unconnected or may be con-
nected to VCC or VSS. Direct connection of DU to
VSS is recommended for the lowest stand-by pow-
er consumption.
MEMORY ORGANIZATION

The M93Cx6 memory is organized either as bytes
(x8) or as words (x16). If Organization Select
(ORG) is left unconnected (or connected to VCC)
the x16 organization is selected; when Organiza-
tion Select (ORG) is connected to Ground (VSS)
the x8 organization is selected. When the M93Cx6
is in stand-by mode, Organization Select (ORG)
should be set either to VSS or VCC for minimum
power consumption. Any voltage between VSS
and VCC applied to Organization Select (ORG)
may increase the stand-by current.
POWER-ON DATA PROTECTION

To prevent data corruption and inadvertent write
operations during power-up, a Power-On Reset
(POR) circuit resets all internal programming cir-
cuitry, and sets the device in the Write Disable
mode. At Power-up and Power-down, the device must
not be selected (that is, Chip Select Input (S)
must be driven Low) until the supply voltage
reaches the operating value VCC specified in
Table 8 to Table 10. When VCC reaches its valid level, the device is
properly reset (in the Write Disable mode) and
is ready to decode and execute incoming in-
structions.
For the M93Cx6 devices (5V range) the POR
threshold voltage is around 3V. For the M93Cx6-
W (3V range) and M93Cx6-R (2V range) the POR
threshold voltage is around 1.5V.
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
INSTRUCTIONS

The instruction set of the M93Cx6 devices con-
tains seven instructions, as summarized in Table 4
to Table 6. Each instruction consists of the follow-
ing parts, as shown in Figure 5: Each instruction is preceded by a rising edge on
Chip Select Input (S) with Serial Clock (C) being
held Low. A start bit, which is the first ‘1’ read on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Two op-code bits, read on Serial Data Input (D)
during the rising edge of Serial Clock (C).
(Some instructions also use the first two bits of
the address to define the op-code). The address bits of the byte or word that is to be
accessed. For the M93C46, the address is
made up of 6 bits for the x16 organization or 7
bits for the x8 organization (see Table 4). For
the M93C56 and M93C66, the address is made
up of 8 bits for the x16 organization or 9 bits for
the x8 organization (see Table 5). For the
M93C76 and M93C86, the address is made up
of 10 bits for the x16 organization or 11 bits for
the x8 organization (see Table 6).
The M93Cx6 devices are fabricated in CMOS
technology and are therefore able to run as slow
as 0 Hz (static input signals) or as fast as the max-
imum ratings specified in Table 19 to Table 22.
Table 4. Instruction Set for the M93C46 and M93C06

Note:1. X = Don’t Care bit. Address bits A6 and A5 are not decoded by the M93C06. Address bits A5 and A4 are not decoded by the M93C06.
5/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 5. Instruction Set for the M93C56 and M93C66

Note:1. X = Don’t Care bit. Address bit A8 is not decoded by the M93C56. Address bit A7 is not decoded by the M93C56.
Table 6. Instruction Set for the M93C76 and M93C86

Note:1. X = Don’t Care bit. Address bit A10 is not decoded by the M93C76. Address bit A9 is not decoded by the M93C76.
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 5. READ, WRITE, EWEN, EWDS Sequences

Note: For the meanings of An, Xn, Qn and Dn, see Table 4, Table 5 and Table 6.
Read

The Read Data from Memory (READ) instruction
outputs serial data on Serial Data Output (Q).
When the instruction is received, the op-code and
address are decoded, and the data from the mem-
ory is transferred to an output shift register. A dum-
my 0 bit is output first, followed by the 8-bit byte or
the 16-bit word, with the most significant bit first.
Output data changes are triggered by the rising
edge of Serial Clock (C). The M93Cx6 automati-
cally increments the internal address register and
clocks out the next byte (or word) as long as the
Chip Select Input (S) is held High. In this case, the
dummy 0 bit is not output between bytes (or
words) and a continuous stream of data can be
read.
Erase/Write Enable and Disable

The Erase/Write Enable (EWEN) instruction en-
ables the future execution of erase or write instruc-
tions, and the Erase/Write Disable (EWDS)
instruction disables it. When power is first applied,
the M93Cx6 initializes itself so that erase and write
instructions are disabled. After an Erase/Write En-
able (EWEN) instruction has been executed, eras-
ing and writing remains enabled until an Erase/
Write Disable (EWDS) instruction is executed, or
until VCC falls below the power-on reset threshold
voltage. To protect the memory contents from ac-
cidental corruption, it is advisable to issue the
Erase/Write Disable (EWDS) instruction after ev-
ery write cycle. The Read Data from Memory
(READ) instruction is not affected by the Erase/
Write Enable (EWEN) or Erase/Write Disable
(EWDS) instructions.
7/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 6. ERASE, ERAL Sequences

Note: For the meanings of An and Xn, please see Table 4, Table 5 and Table 6.
Erase

The Erase Byte or Word (ERASE) instruction sets
the bits of the addressed memory byte (or word) to
1. Once the address has been correctly decoded,
the falling edge of the Chip Select Input (S) starts
the self-timed Erase cycle. The completion of the
cycle can be detected by monitoring the Ready/
Busy line, as described on page 7.
Write

For the Write Data to Memory (WRITE) instruction,
8 or 16 data bits follow the op-code and address
bits. These form the byte or word that is to be writ-
ten. As with the other bits, Serial Data Input (D) is
sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed. The completion of the cycle can be
detected by monitoring the Ready/Busy line, as
described later in this document.
Once the Write cycle has been started, it is inter-
nally self-timed (the external clock signal on Serial
Clock (C) may be stopped or left running after the
start of a Write cycle). The cycle is automatically
preceded by an Erase cycle, so it is unnecessary
to execute an explicit erase instruction before a
Write Data to Memory (WRITE) instruction.
Erase All

The Erase All Memory (ERAL) instruction erases
the whole memory (all memory bits are set to 1).
The format of the instruction requires that a dum-
my address be provided. The Erase cycle is con-
ducted in the same way as the Erase instruction
(ERASE). The completion of the cycle can be de-
tected by monitoring the Ready/Busy line, as de-
scribed on page 7.
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Figure 7. WRAL Sequence

Note: For the meanings of Xn and Dn, please see Table 4, Table 5 and Table 6.
Write All

As with the Erase All Memory (ERAL) instruction,
the format of the Write All Memory with same Data
(WRAL) instruction requires that a dummy ad-
dress be provided. As with the Write Data to Mem-
ory (WRITE) instruction, the format of the Write All
Memory with same Data (WRAL) instruction re-
quires that an 8-bit data byte, or 16-bit data word,
be provided. This value is written to all the ad-
dresses of the memory device. The completion of
the cycle can be detected by monitoring the
Ready/Busy line, as described next.
READY/BUSY STATUS

While the Write or Erase cycle is underway, for a
WRITE, ERASE, WRAL or ERAL instruction, the
Busy signal (Q=0) is returned whenever Chip Se-
lect Input (S) is driven High. (Please note, though,
that there is an initial delay, of tSLSH, before this
status information becomes available). In this
state, the M93Cx6 ignores any data on the bus.
When the Write cycle is completed, and Chip Se-
lect Input (S) is driven High, the Ready signal
(Q=1) indicates that the M93Cx6 is ready to re-
ceive the next instruction. Serial Data Output (Q)
remains set to 1 until the Chip Select Input (S) is
brought Low or until a new start bit is decoded.
COMMON I/O OPERATION

Serial Data Output (Q) and Serial Data Input (D)
can be connected together, through a current lim-
iting resistor, to form a common, single-wire data
bus. Some precautions must be taken when oper-
ating the memory in this way, mostly to prevent a
short circuit current from flowing when the last ad-
dress bit (A0) clashes with the first data bit on Se-
rial Data Output (Q). Please see the application
note AN394 for details.
9/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
CLOCK PULSE COUNTER

In a noisy environment, the number of pulses re-
ceived on Serial Clock (C) may be greater than the
number delivered by the master (the microcontrol-
ler). This can lead to a misalignment of the instruc-
tion of one or more bits (as shown in Figure 8) and
may lead to the writing of erroneous data at an er-
roneous address.
To combat this problem, the M93Cx6 has an on-
chip counter that counts the clock pulses from the
start bit until the falling edge of the Chip Select In-
put (S). If the number of clock pulses received is
not the number expected, the WRITE, ERASE,
ERAL or WRAL instruction is aborted, and the
contents of the memory are not modified.
The number of clock cycles expected for each in-
struction, and for each member of the M93Cx6
family, are summarized in Table 4 to Table 6. For
example, a Write Data to Memory (WRITE) in-
struction on the M93C56 (or M93C66) expects 20
clock cycles (for the x8 organization) from the start
bit to the falling edge of Chip Select Input (S). That
is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
MAXIMUM RATING

Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings

Note:1. IPC/JEDEC J-STD-020A JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
11/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
DC AND AC PARAMETERS

This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 8. Operating Conditions (M93Cx6)
Table 9. Operating Conditions (M93Cx6-W)
Table 10. Operating Conditions (M93Cx6-R)
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 11. AC Measurement Conditions (M93Cx6)

Note:1. Output Hi-Z is defined as the point where data out is no longer driven.
Table 12. AC Measurement Conditions (M93Cx6-W and M93Cx6-R)

Note:1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 9. AC Testing Input Output Waveforms
Table 13. Capacitance

Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 1 MHz.
13/27
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 14. DC Characteristics (M93Cx6, temperature range 6)

Note:1. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W.
Table 15. DC Characteristics (M93Cx6, temperature range 3)

Note:1. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W.
M93C86, M93C76, M93C66, M93C56, M93C46, M93C06
Table 16. DC Characteristics (M93Cx6-W, temperature range 6)

Note:1. Current product: identified by Process Identification letter F or M. New product: identified by Process Identification letter W.
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