M76DW63000A70Z ,64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 8Mbit/4Mbit SRAM, 3V Supply, Multiple Memory ProductLogic Diagram 17SRAM OPERATIONS . . . 18Read . . . . . 18Write . . . . ..
M80C51 , CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
M80C86-2 , 16-BIT CHMOS MICROPROCESSOR
M81049SP , OCTAL D-TYPE FLIP-FLOP DRIVER WITH CLEAR
M81713FP , HVIC High Voltage Half-Bridge Driver 600 Volts/±500mA
M81713FP , HVIC High Voltage Half-Bridge Driver 600 Volts/±500mA
MAX1616EUK+ ,High-Voltage, Low-Power Linear Regulators for Notebook ComputersELECTRICAL CHARACTERISTICS (continued)(V = 15V, SHDN = V , I = 5μA, T = T to T , unless otherwise n ..
MAX1616EUK+T ,High-Voltage, Low-Power Linear Regulators for Notebook ComputersFeaturesThe MAX1615/MAX1616 are micropower, SOT23-5 lin-♦ 4V to 28V Input Rangeear regulators that ..
MAX1616EUK-T ,High-Voltage / Low-Power Linear Regulators for Notebook ComputersELECTRICAL CHARACTERISTICS(V = 15V, SHDN = V , I = 5µA, T = T to T , unless otherwise noted. Typica ..
MAX1617 ,Remote/Local Temperature Sensor with SMBus Serial InterfaceFeaturesThe MAX1617 is a precise digital thermometer that♦ Two Channels: Measures Both Remote and L ..
MAX1617AMEE ,Remote/Local Temperature Sensor with SMBus Serial InterfaceFeaturesThe MAX1617A (patents pending) is a precise digital ther-' Two Channels: Measures Both Remo ..
MAX1617AMEE+ ,Remote/Local Temperature Sensor with SMBus Serial InterfaceFeaturesThe MAX1617A is a precise digital thermometer that♦ Two Channels: Measures Both Remote and ..
M76DW63000A70Z
64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 8Mbit/4Mbit SRAM, 3V Supply, Multiple Memory Product
1/27
PRELIMINARY DATASeptember 2003
M76DW63000A
M76DW62000A64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and
8Mbit/4Mbit SRAM, 3V Supply, Multiple Memory Product
FEATURES SUMMARY MULTIPLE MEMORY PRODUCT 64 Mbit (8Mb x8 or 4Mb x16), Multiple Bank,
Page, Boot Block, Flash Memory SRAM: 8Mbit (512K x 16) for
M76DW63000A, or 4Mbit (256K x 16) for
M76DW62000A SUPPLY VOLTAGE
–VCCF = VCCS = 2.7V to 3.3V
–VPPF = 12V for Fast Program (optional) ACCESS TIME: 70, 90ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 227Eh + 2202h + 2201h
FLASH MEMORY ASYNCHRONOUS PAGE READ MODE Page Width: 4 Words Page Access: 25, 30ns Random Access: 70, 90ns PROGRAMMING TIME 10µs per Byte/Word typical 4 Words/ 8 Bytes at-a-time Program MEMORY BLOCKS Quadruple Bank Memory Array:
8Mbits+ 24Mbits + 24Mbits + 8Mbits Parameter Blocks (at both Top and Bottom) DUAL OPERATIONS While Program or Erase in a group of banks
(from 1 to 3), Read in any of the other banks PROGRAM/ERASE SUSPEND and RESUME
MODES Read from any Block during Program
Suspend Read and Program another Block during
Erase Suspend UNLOCK BYPASS PROGRAM COMMAND Faster Production/Batch Programming
Figure 1. Package VPP/WP PIN for FAST PROGRAM and WRITE
PROTECT TEMPORARY BLOCK UNPROTECTION
MODE COMMON FLASH INTERFACE 64 bit Security Code EXTENDED MEMORY BLOCK Extra block used as security block or to store
additional information 100,000 PROGRAM/ERASE CYCLES per
BLOCK
SRAM 8Mbit (512K x 16) or 4Mbit (256K x 16) ACCESS TIME: 70ns LOW VCCS DATA RETENTION: 1.5V POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
M76DW63000A, M76DW62000A2/27
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. LFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Flash Chip Enable (EF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Reset/Block Temporary Unprotect (RPF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SRAM Chip Enable (E1S, E2S). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SRAM Upper Byte Enable (UBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SRAM Lower Byte Enable (LBS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VCCF Supply Voltage (2.7V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VCCS Supply Voltage (2.7V to 3.3V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. Main Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6. Flash Memory DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7. SRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline14
Table 8. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Package Mechanical Data. . .15
M76DW63000A, M76DW62000A
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 9. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
SRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
SRAM SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 8. SRAM Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
SRAM OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Standby/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 9. SRAM Read Mode AC Waveforms, Address Controlled . . . . . . . . . . . . . . . . . . . . . .19
Figure 10. SRAM Read AC Waveforms, G Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 11. SRAM Standby AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 10. SRAM Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 12. SRAM Write AC Waveforms, W Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 13. SRAM Write AC Waveforms, E1S Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 14. SRAM Write AC Waveforms, W Controlled with G Low. . . . . . . . . . . . . . . . . . . . . .23
Figure 15. SRAM Write Cycle Waveform, UBS and LBS Controlled, G Low . . . . . . . . . . . . . .23
Table 11. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 16. SRAM Low VCCS Data Retention AC Waveforms, E1S or UBS / LBS Controlled . .25
Table 12. SRAM Low VCCS Data Retention Characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . .25
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
M76DW63000A, M76DW62000A4/27
SUMMARY DESCRIPTION
Table 1. Signal NamesNote:1. A21-A19 are not connected to the SRAM component of
the M76DW63000A, and A21-A18 are not connected to
the SRAM component of the M76DW62000A.
M76DW63000A, M76DW62000A
M76DW63000A, M76DW62000A6/27
SIGNAL DESCRIPTIONSee Figure 2 Logic Diagram and Table 1,Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). Addresses A0-A18
(for M76DW63000A), or A0-A17 (for
M76DW62000A), are common inputs for the Flash
Memory and the SRAM components. The other
lines (A19-A21, or A18-21, respectively) are inputs
for the Flash Memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the
internal state machine. The Flash memory is ac-
cessed through the Chip Enable (EF) and Write
Enable (W) signals, while the SRAM is accessed
through two Chip Enable signals (E1S and E2S)
and the Write Enable signal (W).
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–
1). When BYTE is High, VIH, this pin behaves as
a Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Flash Chip Enable (EF). The Chip Enable input
activates the memory, allowing Bus Read and Bus
Write operations to be performed. When Chip En-
able is High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the device.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the device.
VPP/Write Protect (VPP/WP). The VPP/Write
Protect pin provides two functions. The VPP func-
tion allows the Flash memory to use an external
high voltage power supply to reduce the time re-
quired for Program operations. This is achieved
by bypassing the unlock cycles and/or using the
multiple Word (2 or 4 at-a-time) or multiple Byte
Program (2, 4 or 8 at-a-time) commands. The
Write Protect function provides a hardware meth-
od of protecting the four outermost boot blocks
(two at the top, and two at the bottom of the ad-
dress space).
When VPP/Write Protect is Low, VIL, the memory
protects the four outermost boot blocks; Program
and Erase operations in these blocks are ignored
while VPP/Write Protect is Low, even when RPF is
at VID.
When VPP/Write Protect is High, VIH, the memory
reverts to the previous protection status of the four
outermost boot blocks (two at the top, and two at
the bottom of the address space). Program and
Erase operations can now modify the data in these
blocks unless the blocks are protected using Block
Protection.
When VPP/Write Protect is raised to VPP the mem-
ory automatically enters the Unlock Bypass mode.
When VPP/Write Protect returns to VIH or VIL nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
VIH to VPP and from VPP to VIH must be slower
than tVHVPP. See the M29DW640D datasheet for
more details.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1µF capacitor should be connected be-
tween the VPP/Write Protect pin and the VSS
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, IPP.
Reset/Block Temporary Unprotect (RPF). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if VPP/WP is at VIL, then the two outer-
most boot blocks will remain protected even if RPF
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the
M29DW640D datasheet for more details.
M76DW63000A, M76DW62000AHolding RPF at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the Flash memory is performing a Program
or Erase operation. During Program or Erase op-
erations Ready/Busy is Low, VOL. Ready/Busy is
high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
Flash memory. When Byte/Word Organization Se-
lect is Low, VIL, the Flash memory is in x8 mode,
when it is High, VIH, the Flash memory is in x16
mode.
SRAM Chip Enable (E1S, E2S). The Chip En-
able inputs activate the SRAM memory control
logic, input buffers and decoders. E1S at VIH or
E2S at VIL deselects the memory and reduces the
power consumption to the standby level. E1S and
E2S can also be used to control writing to the
SRAM memory array, while W remains at VIL. It is
not allowed to set EF at VIL, E1S at VIL and E2S at
VIH at the same time.
SRAM Upper Byte Enable (UBS). The Upper
Byte Enable enables the upper bytes for SRAM
(DQ8-DQ15). UBS is active low.
SRAM Lower Byte Enable (LBS). The Lower
Byte Enable enables the lower bytes for SRAM
(DQ0-DQ7). LBS is active low.
VCCF Supply Voltage (2.7V to 3.3V). VCCF pro-
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the
VCCF Supply Voltage is less than the Lockout Volt-
age, VLKO. This prevents Bus Write operations
from accidentally damaging the data during power
up, power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCCF Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, ICC3.
VCCS Supply Voltage (2.7V to 3.3V). VCCS pro-
vides the power supply for the SRAM control pins.
VSS Ground. VSS is the ground reference for all
voltage measurements in the Flash and SRAM
chips. The device features two VSS pins both of
which must be connected to the system ground.
M76DW63000A, M76DW62000A8/27
FUNCTIONAL DESCRIPTIONThe Flash and SRAM components have separate
power supplies. They are distinguished by three
chip enable inputs: EF for the Flash memory and,
E1S and E2S for the SRAM.
Recommended operating conditions do not allow
both the Flash and the SRAM to be in active mode
at the same time. The most common example is
simultaneous read operations on the Flash and
the SRAM which would result in a data bus con-
tention. Therefore it is recommended to put the
SRAM in the high impedance state when reading
the Flash and vice versa (see Table 2 Main Oper-
ation Modes for details).
Figure 4. Functional Block DiagramNote: Where n=19 and m=18 for M76DW63000A, and n=18 and m=17 for M76DW62000A.
M76DW63000A, M76DW62000A
Table 2. Main Operation ModesNote:1. X = Don’t Care = VIL or VIH. This table is valid when BYTE = VIH. This table is also valid when BYTE = VIL, with the only difference that DQ15-DQ8 are always
high impedance when the Flash Memory component is being accessed. For the Block Protect and Unprotect features, refer to the M29DW640D datasheet. Only the In-System Technique is available in
the stacked product. To read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Block indicator bit, refer to the
“Auto Select Command” in the M29DW640D datasheet.
M76DW63000A, M76DW62000A10/27
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum RatingsNote:1. Depends on range.
M76DW63000A, M76DW62000A
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 4,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
The operating and AC measurement parameters
given in this section (see Table 4 below) corre-
spond to those of the stand-alone Flash and
SRAM devices. For compatibility purposes, the
M29DW640D voltage range is restricted to VCCS
in the stacked product.
Table 4. Operating and AC Measurement Conditions
Figure 5. AC Measurement I/O Waveform
Table 5. Device CapacitanceNote: Sampled only, not 100% tested.
M76DW63000A, M76DW62000A12/27
Table 6. Flash Memory DC CharacteristicsNote:1. Sampled only, not 100% tested. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).
M76DW63000A, M76DW62000A
Table 7. SRAM DC CharacteristicsNote:1. Sampled only, not 100% tested. A0-A18 for the M76DW63000A, A0-A17 for the M76DW62000A.
M76DW63000A, M76DW62000A14/27
PACKAGE MECHANICAL
Figure 7. Stacked LFBGA73 8x11.6mm, 10x12 array, 0.8mm pitch, Bottom View Package Outline Note: Drawing is not to scale.
