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M74HCT164M1R-M74HCT164RM13TR
8 BIT SIPO SHIFT REGISTER
1/11July 2001 HIGH SPEED:
tPD = 24 ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS :
VIH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN) PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 164
DESCRIPTIONThe M74HCT164 is an high speed CMOS 8 BIT
SIPO SHIFT REGISTER fabricated with silicon
gate C2 MOS technology.
The 74HCT164 is an 8 bit shift register with serial
data entry and an output from each of the eight
stages. Data is entered serially through one of two
inputs (A or B), either of these inputs can be used
as an active high enable for data entry through the
other input. An unused input must be high, or both
inputs connected together. Each low-to-high
transition on the clock inputs shifts data one place
to the right and enters into QA, the logic NAND of
the two data inputs (A x B), the data that existed
before the rising clock edge. A low level on the
clear input overrides all other inputs and clears the
register asynchronously, forcing all Q outputs low.
The M74HCT164 is designed to directly interface
HSC2 MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT1648 BIT SIPO SHIFT REGISTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HCT1642/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE X : Don’t Care
QAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clock
LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays
M74HCT1643/11
TIMING CHART
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
M74HCT1644/11
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
M74HCT1645/11
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
M74HCT1646/11
TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : MINIMUM PULSE WIDTH (CLEAR) AND REMOVAL TIME( CLEAR TO CLOCK) (f=1MHz; 50% duty cycle)
