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M74HC652RM13TR
OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
1/14August 2001 HIGH SPEED:
fMAX = 79 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC = 4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 652
DESCRIPTIONThe M74HC652 is an advanced high-speed
CMOS OCTAL BUS TRANSCEIVER AND
REGISTER (3-STATE) fabricated with silicon gate2 MOS technology.
This device consists of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal storage registers.
Enable GAB and GBA are provided to control the
transceiver functions. Select AB (SAB) and select
BA (SBA) control pins are provided to select
whether real-time or stored data is transferred. A
low input level selects real-time data, and a high
selects stored data.
Data on the A or B bus, or both, can be stored in
the internal D flip-flops by low-to-high transition at
the appropriate clock pins (CLOCK AB or CLOCK
BA) regardless of the select or enable control pins.
When select AB and select BA are in the real time
transfer mode, it is also possible to store data
without using the internal D type flip-flops by
simultaneously enabling GAB and GBA. In this
configuration each output reinforces its input.
Thus, when all other data sources to the two sets
of bus lines are at high impedance, each set of
bus lines will remain at its last state.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC652OCTAL BUS TRANSCEIVER/REGISTER
WITH 3 STATE OUTPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC6522/14
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
M74HC6523/14
X : Don’t Care
Z : High Impedance
Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
LOGIC DIAGRAM
TIMING CHART
M74HC6524/14
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC6525/14
DC SPECIFICATIONS
M74HC6526/14
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
M74HC6527/14
CAPACITIVE CHARACTERISTICS 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per
channel)
TEST CIRCUIT CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
