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M74HC165B1R-M74HC165M1R-M74HC165RM13TR
8 BIT PISO SHIFT REGISTER
1/12July 2001 HIGH SPEED :
tPD = 15ns (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC =4μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 165
DESCRIPTION

The M74HC165 is an high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated with silicon
gate C2 MOS technology.
This device contains eight clocked master slave
RS flip-flops connected as a shift register, with
auxiliary gating to provide over-riding
asynchronous parallel entry. Parallel data enters
when the shift/load input is low. The parallel data
can change while shift/load is low, provided that
the recommended set-up and hold times are
observed. For clocked operation, shift/load must
be high. The two clock input perform identically;
one can be used as a clock inhibit by applying a
high signal; to permit this operation clocking is
accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit
signal should only go high while the clock is high.
Otherwise the rising inhibit signal will cause the
same response as rising clock edge.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC165

8 BIT PISO SHIFT REGISTER
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC165
2/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE

a........h : The level of steady input voltage at inputs a through respectively
QAn - QGn : The level of QA - QG, respectively. before the most-recent transition of the clock
LOGIC DIAGRAM
M74HC165
3/12
TIMING CHART
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
M74HC165
4/12
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
M74HC165
5/12
AC ELECTRICAL CHARACTERISTICS (C
L = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
M74HC165
6/12
TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: SERIAL MODE PROPAGATION DELAY (f=1MHz; 50% duty cycle)
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