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M74HC109B1RSTN/a12850avaiDUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M74HC109M1RSTMN/a4000avaiDUAL J-K FLIP FLOP WITH PRESET AND CLEAR
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M74HC109RM13TRSTN/a16696avaiDUAL J-K FLIP FLOP WITH PRESET AND CLEAR


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M74HC109B1R-M74HC109M1R-M74HC109RM13TR
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
1/12July 2001 HIGH SPEED :
fMAX = 67MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION:
ICC =2μA(MAX.) at TA=25°C HIGH NOISE IMMUNITY:NIH = VNIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:OH | = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: PLH ≅ t PHL WIDE OPERATING VOLTAGE RANGE:CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 109
DESCRIPTION

The M74HC109 is an high speed CMOS DUAL
J-K FLIP FLOP WITH PRESET AND CLEAR
fabricated with silicon gate C2 MOS technology. In
accordance with the logic level on the J and K
input this device changes state on positive going
transition of the clock pulse. CLEAR and PRESET
are independent of the clock and are
accomplished by a logic low on the corresponding
input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC109

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
M74HC109
2/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE

X : Don’t Care
LOGIC DIAGRAM

This logic diagram has not be used to estimate propagation delays
M74HC109
3/12
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
RECOMMENDED OPERATING CONDITIONS
M74HC109
4/12
DC SPECIFICATIONS
M74HC109
5/12
AC ELECTRICAL CHARACTERISTICS (C
L = 50 pF, Input tr = tf = 6ns)
CAPACITIVE CHARACTERISTICS

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/
FLOP)
M74HC109
6/12
TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1: PROPAGATION DELAY TIMES, SETUP AND HOLD TIMES, MINIMUM PULSE WIDTH
(CK) (f=1MHz; 50% duty cycle)
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