M69AR048BL70ZB8 ,32 MBIT (2M X16) 1.8V SUPPLY, ASYNCHRONOUS PSRAMfeatures several Power-Down modes,random access memory cells, to minimize the cellmaking of power s ..
M69AW024BE60ZB8F , 16 Mbit (1M x16) 3V Asynchronous PSRAM
M69AW024BE60ZB8F , 16 Mbit (1M x16) 3V Asynchronous PSRAM
M69AW024BL60ZB8T ,16 MBIT (1M X16) 3V SUPPLY, ASYNCHRONOUS PSRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 4. Operating and ..
M6M80011L , 1024 BIT ELECTRICALLY ERASABLE AND PROGRAMMABLE ROM
M6M80021 , 2048 BIT ELECTRICALLY ERASABLE AND RPOGRAMMABLE ROM
MAX1132BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with Referenceapplications. The MAX1132 accepts input signals of 0to +12V (unipolar) or ±12V (bipolar), while the ..
MAX1132BEAP ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX1132BEAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceApplicationsOrdering Information continued at end of data sheet.Industrial Process ControlIndustria ..
MAX1132BEAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceELECTRICAL CHARACTERISTICS(AV = DV = +5V ±5%, f = 4.8MHz, external clock (50% duty cycle), 24 clock ..
MAX1133BCAP ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceELECTRICAL CHARACTERISTICS(AV = DV = +5V ±5%, f = 4.8MHz, external clock (50% duty cycle), 24 clock ..
MAX1133BCAP+ ,16-Bit ADC, 200ksps, 5V Single-Supply with ReferenceFeaturesThe MAX1132/MAX1133 are 200ksps, 16-bit ADCs.♦ 200ksps (Bipolar) and 150ksps (Unipolar) The ..
M69AR048BL70ZB8
32 MBIT (2M X16) 1.8V SUPPLY, ASYNCHRONOUS PSRAM
1/29
PRELIMINARY DATAApril 2004
M69AR048B32 Mbit (2Mb x16) 1.8V Asynchronous PSRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 1.65 to 1.95V ACCESS TIMES: 70ns, 80ns, 85ns LOW STANDBY CURRENT: 100µA DEEP POWER-DOWN CURRENT: 10µA BYTE CONTROL: UB/LB PROGRAMMABLE PARTIAL ARRAY COMPATIBLE WITH STANDARD LPSRAM TRI-STATE COMMON I/O 8 WORD PAGE ACCESS CAPABILITY: 25ns WIDE OPERATING TEMPERATURE
–TA = –30 to +85°C PARTIAL POWER-DOWN MODES Deep Power-Down 4 Mbit Partial Power-Down 8 Mbit Partial Power-Down 16 Mbit Partial Power-Down
Figure 1. Package
M69AR048B
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Upper Byte Enable (UB).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. Power-Down Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 6. Power-Down Configuration Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 5. AC Measurement Load Circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 6. AC Measurement Load Circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3/29
M69AR048BTable 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 10. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 11. Read Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 9. Address and Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . .15
Figure 10.UB/LB Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 11.Page Address and Chip Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . .16
Figure 12.Random and Page Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . .17
Table 12. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 13.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 14.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 15.Write Enable and UB/LB Controlled, Write AC Waveforms 1 . . . . . . . . . . . . . . . . . . . . .20
Figure 16.Write Enable and UB/LB Controlled, Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . .20
Figure 17.Write Enable and UB/LB Controlled, Write AC Waveforms 3 . . . . . . . . . . . . . . . . . . . . .21
Figure 18.Write Enable and UB/LB Controlled, Write AC Waveforms 4 . . . . . . . . . . . . . . . . . . . . .21
Figure 19.Chip Enable Controlled, Read and Write Mode AC Waveforms . . . . . . . . . . . . . . . . . . .22
Figure 20.Chip Enable, Write Enable, Output Enable Controlled, Read/Write AC Waveforms. . . .22
Figure 21.Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms . . .23
Figure 22.Output Enable, Write Enable and UB/LB Controlled, Read/Write AC Waveforms . . . . .23
Table 13. Standby Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 23.Power-Down Programming AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 24.Power-Down Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 25.Power-Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 26.Standby Mode Entry AC Waveforms, After Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 27.TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View . . . .26
Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . .26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
M69AR048B
SUMMARY DESCRIPTIONThe M69AR048B is a 32 Mbit (33,554,432 bit)
CMOS memory, organized as 2,097,152 words by
16 bits, and is supplied by a single 1.65V to 1.95V
supply voltage range.
M69AR048B is a member of STMicroelectronics
1T/1C (one transistor per cell) memory family.
These devices are manufactured using dynamic
random access memory cells, to minimize the cell
size, and maximize the amount of memory that
can be implemented in a given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AR048B han-
dles the periodic refresh cycle, automatically, and
without user involvement.
Write cycles can be performed on a single Byte by
using Upper Byte Enable (UB) and Lower Byte En-
able (LB).
The device can be put into standby mode using
Chip Enable (E1) or in Power-Down mode by us-
ing Chip Enable (E2).
The device features several Power-Down modes,
making of power saving a user configurable op-
tion: Partial Power-Down (4 Mbits, 8 Mbits or 16
Mbits) performs a limited refresh of the part of
the PSRAM array that contains essential data. Deep Power-Down achieves a very low
current consumption by halting all the internal
activities. Since the refresh circuitry is halted,
the duration of the power-down should be less
than the maximum period for refresh.
Table 1. Signal Names
5/29
M69AR048B
M69AR048B
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Read and Write operations.
Data Inputs/Outputs (DQ8-DQ15). The Upper
Byte Data Inputs/Outputs carry the data to or from
the upper part of the selected address during a
Write or Read operation, when Upper Byte Enable
(UB) is driven Low.
Data Inputs/Outputs (DQ0-DQ7). The Lower
Byte Data Inputs/Outputs carry the data to or from
the lower part of the selected address during a
Write or Read operation, when Lower Byte Enable
(LB) is driven Low.
Chip Enable (E1). When asserted (Low), the
Chip Enable, E1, activates the memory state ma-
chine, address buffers and decoders, allowing
Read and Write operations to be performed. When
de-asserted (High), all other pins are ignored, and
the device is put, automatically, in low-power
Standby mode.
Chip Enable (E2). The Chip Enable, E2, puts the
device in Power-down mode (Deep Power-Down
or a Partial Power-Down mode ) when it is driven
Low. Deep Power-down mode is the lowest power
mode.
Output Enable (G). The Output Enable, G, pro-
vides a high speed tri-state control, allowing fast
read/write cycles to be achieved with the common
I/O data bus.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the device.
Upper Byte Enable (UB). The Upper Byte En-
able, UB, gates the data on the Upper Byte Data
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB). The Lower Byte En-
able, LB, gates the data on the Lower Byte Data
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Write,
etc.) and for driving the refresh logic, even when
the device is not being accessed.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
7/29
M69AR048B
M69AR048B
OPERATION
Operational modes are determined by device con-
trol inputs W, E1, E2, LB and UB as summarized
in the Operating Modes table (see Table 2).
Power Up Sequence
Because the internal control logic of the
M69AR048B needs to be initialized, the following
power-up procedure must be followed before the
memory is used (see Figure 25., Power-Up Mode
AC Waveforms): Apply power and wait for VCC to stabilize Wait 300µs while driving both Chip Enable
signals (E1 and E2) High
Read Mode
The device is in Read mode when: Write Enable (W) is High and Output Enable (G) is Low and the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The time taken to enter Read mode (tELQV, tGLQV
or tBLQV) depends on which of the above signals
was the last to reach the appropriate level.
Data out (DQ15-DQ0) may be indeterminate
during tELQX, tGLQX and tBLQX, but data will always
be valid during tAVQV. See Figures 8, 9, 10, 11 and
12 and Table 11., Read Mode AC Characteristics,
for details of when the outputs become valid.
Write Mode
The device is in Write mode when Write Enable (W) is Low and at least one of Upper Byte Enable (UB)
and Lower Byte Enable (LB) is Low the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The Write cycle begins just after the event (the fall-
ing edge) that causes the last of these conditions
to become true (tAVWL or tAVEL or tAVBL).
The Write cycle is terminated by the rising edge of
Write Enable (W) or Chip Enable (E1), whichever
occurs first.
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte En-
able (UB) and/or Lower Byte Enable (LB) is Low),
then Write Enable (W) will return the outputs to
high impedance within tWHDZ of its rising edge.
Care must be taken to avoid bus contention in this
type of operation. Data input must be valid for tD-
VWH before the rising edge of Write Enable (W), orfor tDVEH before the rising edge of Chip Enable
(E1), whichever occurs first, and remain valid for
tWHDZ, tBHDZ or tEHDZ.
See Figures 13, 14, 15, 16, 17 and 18, and Table
12., Write Mode AC Characteristics, for details of
the timing requirements. Figures 19, 20, 21 and 22
show Read and Write mode AC waveforms.
Standby Mode
The device is in Standby mode when: Chip Enable (E1)is High and Chip Enable (E2)is High
The input/output buffers and the decoding/control
logic are switched off, but the dynamic array con-
tinues to be refreshed. In this mode, the memory
current consumption, ISB, is reduced, and the data
remains valid.
See Figure 26., Standby Mode Entry AC Wave-
forms, After Read and Table 13., Standby Mode
AC Characteristics for details.
Power-Down Modes
Description. The M69AR048B has four Power-
down modes, Deep Power-down, 4Mbit Partial
Power-Down, 8Mbit Partial Power-Down, and
16Mbit Partial Power-Down (see Table 3).
These can be entered using a series of read and
write operations. Each mode has the following fea-
tures. The default state is Deep Power-Down and
it is the lowest power consumption but all data will
be lost once E2 is brought Low for Power-down.
No sequence is required to put the device in Deep
Power-down mode after Power-up.
The device is in one of the Power-Down modes
when: Chip Enable (E2)is Low
All the device logic is switched off and all internal
operations are suspended. This gives the lowest
power consumption. In this operating mode, no re-
fresh is performed, and data is lost if the duration
is longer than 10ns. This mode is useful for those
applications where the data contents are no longer
needed, and can be lost, but where reduced cur-
rent consumption is of major importance.
See Figure 24., Power-Down Mode AC Wave-
forms and Table 13., Standby Mode AC Charac-
teristics for details.
Power-Down Program Sequence. The Power-
Down Program sequence is used to program the
Power-Down Configuration. It requires a total of six
read and write operations, with specific addresses
and data. Between each read or write operation
the device must be in Standby mode.
Table 4 and Figure 23. show the sequence. In the
first cycle, the Byte at the highest memory address
(MSB) is read. In the second and third cycles, the
data (RDa) read by first cycle are written back. If
the third cycle is written into a different address, the
sequence is aborted, and the data written by the
third cycle is valid as in a normal write operation. In
the fourth and fifth cycles, the Power-Down Config-
9/29
M69AR048B
uration data is written. The data of the fourth cycle
must be all 0s, and the data of the fifth cycle is the
Power-Down Configuration data (see Table
5., Power-Down Configuration Data). If the fourth
cycle is written into a different address, the se-
quence is aborted. In the last cycle, a read is made
from the specific Power-Down Configuration ad-
dress (see Table 6., Power-Down Configuration
Addresses). The Power-Down Configuration data
and address must correspond, otherwise the se-
quence is aborted.
When this sequence is performed to take the de-
vice from one Partial Power-Down mode to anoth-
er, the write data may be lost. So, if a Partial
Power-Down mode is used, this sequence should
be performed prior to any normal read or write op-
erations.
Table 2. Operating Modes
Note: X = VIH or VIL. Should not be kept in this logic condition for a period longer than 1µs. Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data re-
tention depend on the selection of the Power-Down programming. G can be VIL during the Write operation if the following conditions are satisfied:
a. Write pulse is initiated by E1 (E1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied;
b. G stays VIL during the entire Write cycle.
Table 3. Power-Down Modes
M69AR048B
Table 4. Power-Down Program Sequence
Note:1. PDC Power-Down Configuration.
Table 5. Power-Down Configuration Data
Table 6. Power-Down Configuration Addresses
11/29
M69AR048B
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
M69AR048B
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 8, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 8. Operating and AC Measurement Conditions
Note:1. All voltages are referenced to VSS. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 8.
Figure 5. AC Measurement Load Circuit 1
Table 9. Capacitance
13/29
M69AR048B
Table 10. DC Characteristics
Note:1. Maximum DC voltage on input and I/O pins is VCC +0.2V.
During voltage transitions, input may overshoot to VCC+ 1.0V for a period of up to 5ns. Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may undershoot to VSS− 1.0V for a period of up to 5ns. Partial stands for Partial Power-Down.
M69AR048B
Table 11. Read Mode AC Characteristics
Note:1. Maximum value is applicable if E1 is kept Low without change of address input of A3 to A20. If needed by system operation, please
contact your local ST representative for relaxation of the 1000ns limitation. Address should not be changed within minimum Read Cycle Time. The output load 5pF without any other load. Applicable to A3 to A20 when E1 is kept Low. Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page
Read Cycle must be closed within 4µs. Applicable when at least two of address inputs among applicable are switched from previous state. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied. Values obtained with AC Measurement Load Circuit 1 (see Figure 5). If the test conditions correspond to AC Measurement Load
Circuit 2 (see Figure 6), 10ns must be added to the times given in the above table.
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M69AR048B
Figure 8. Address Controlled, Read Mode AC Waveforms
Note: E2 = High, W = High.
Figure 9. Address and Output Enable Controlled, Read Mode AC Waveforms
Note: Write Enable (W) = High, E2 = High.
