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M616Z08-20MH3 |M616Z0820MH3STN/a365avai128 Kbit (8 Kbit X 16) SRAM with Output Enable
M616Z08-20MH3TR |M616Z0820MH3TRSTMN/a2298avai128 Kbit (8 Kbit X 16) SRAM with Output Enable


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M616Z08-20MH3-M616Z08-20MH3TR
128 Kbit (8 Kbit X 16) SRAM with Output Enable
1/15March 2004
M616Z08

128 Kbit (8 Kbit x16) SRAM with Output Enable
FEATURES SUMMARY
OPERATION VOLTAGE: 2.34V TO 3.6V 8 Kbit x16 SRAM EQUAL CYCLE and ACCESS TIMES: AS
FAST AS 20ns TRI-STATE COMMON I/O TWO WRITE ENABLE PINS ALLOW
WRITING TO UPPER AND LOWER BYTES Table 1. Signal Names
Note: TO Pin should be connected to VCC.
M616Z08
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1. 44-pin, Hatless SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3. 44-pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Figure 4. Address Controlled, READ Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms . . . . . . . . . . . . .5
Table 2. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
“Operational” Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Table 4. WE(0,1) States during Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 5. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 7. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8. AC Testing Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 9. SO44 – 44-Lead, Plastic, Hatless, Small Package Outline . . . . . . . . . . . . . . . . . . . . . . .13
Table 10. SO44 – 44-lead, Plastic, Hatless, Small Package Mechanical Data . . . . . . . . . . . . . . . .13
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 11. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/15
M616Z08
DESCRIPTION

The M616Z08 is a 128 Kbit (131,072 bit) CMOS
SRAM, organized by 16 bits. The device features
fully static operation requiring no external clocks or
timing strobes, with equal address access and cy-
cle times. It requires a single 2.6V ± 10% or
3.3V± 10% supply, and all inputs and outputs are
TTL compatible.
The M616Z08 is available in a 44-lead SOIC pack-
age.
Figure 3. 44-pin Connections

Note: TO Pin should be connected to VCC.
M616Z08
OPERATION
READ Mode

The M616Z08 is in the READ Mode whenever
WRITE Enable (WE0 or WE1) is High with Output
Enable (OE) Low, and Chip Enable (CE) is assert-
ed. This provides access to data from sixteen of
the 131,072 locations in the static memory array,
specified by the 13 address inputs. Valid data will
be available at the sixteen output pins within tAVQV
after the last stable address, providing OE is Low
and CE is Low. If Chip Enable or Output Enable
access times are not met, data access will be
measured from the limiting parameter (tELQV or
tGLQV) rather than the address. Data out may be
indeterminate at tELQX and tGLQX, but data lines
will always be valid at tAVQV.
5/15
M616Z08
Table 2. READ Mode AC Characteristics

Note:1. Valid for Ambient Operating Temperature: TA = –40 to 125°C (except where noted). CL = 5pF.
M616Z08
WRITE Mode

The M616Z08 is in the WRITE mode whenever the
WE0 (low memory addresses) or WE1 (high mem-
ory addresses) and CE pins are low (see Table
4., page 8). Either the Chip Enable input (CE) or
the WRITE Enable input (WE0 or WE1) must be
de-asserted during Address transitions for subse-
quent WRITE cycles. WRITE begins with the con-
currence of Chip Enable being active with WE0 or
WE1 low. Therefore, address setup time is refer-
enced to WRITE Enable and Chip Enable as tAVWL
and tAVEH respectively, and is determined by the
latter occurring edge.
The WRITE cycle can be terminated by the earlier
rising edge of CE, or WE0/WE1.
if the Output is enabled (CE = Low and OE = Low),
then WE0 or WE1 will return the outputs to high
impedance within tWLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for tDVWH
before the rising edge of WRITE Enable, or for tD-
VEH before the rising edge of CE, whichever oc-curs first, and remain valid for tWHDX or tEHDX.
Note: When using MCP555 with TO Pin high, re-

laxed WRITE timing (CSNT = 1 in the chip select
configuration register) should be selected.
Figure 6. WRITE Enable Controlled, WRITE Mode AC Waveforms
Figure 7. Chip Enable Controlled, WRITE Mode AC Waveforms

Note:1. Output Enable (OE) = High. If CE goes High with WE0 or WE1 high, the output remains in a high-impedance state.
7/15
M616Z08
Table 3. WRITE Mode AC Characteristics

Note:1. Valid for Ambient Operating Temperature: TA = –40 to 125°C (except where noted). CL = 5pF At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device.
M616Z08
“Operational” Mode

The M616Z08 has a Chip Enable power down fea-
ture which invokes an automatic standby mode
whenever Chip Enable is de-asserted (CE = High).
An Output Enable (OE) signal provides a high
speed tri-state control, allowing fast READ/WRITE
cycles to be achieved with the common I/O data
bus. Operational modes are determined by device
control inputs WE0 or WE1 and CE as summa-
rized in “Operating Modes” (see Tables 4 and 5).
Noise Immunity

When designing with high speed memory, proper
power trace layout and capacitive decoupling
must be maintained to ensure proper system oper-
ation. Power and ground line inductance should be
reduced by providing separate power planes. The
impedance of the decoupling path from the power
pin through the decoupling capacitor should also
be kept to a minimum. Small decoupling capaci-
tors (10nF) should be located as close to the de-
vice pins as possible to limit the high frequency
noise. Larger capacitor values (10uF and 1uF) are
recommended to reduce low frequency noise and
should be placed next to the power entry point of
the board. Proper line termination should also be
employed to minimize signal reflection.
See Motorola Semiconductor Application Note
AN2127/D for additional Electromagnetic Compat-
ibility (EMC) system design guidelines.
Table 4. WE(0,1) States during Access
Table 5. Operating Modes

Note:1. X = '1' or '0'
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