IC Phoenix
 
Home ›  MM12 > M59PW016-M59PW016-100M1,16 MBIT (1MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORY
M59PW016-M59PW016-100M1 Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
M59PW016STN/a131avai16 MBIT (1MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORY
M59PW016-100M1 |M59PW016100M1STN/a20000avai16 MBIT (1MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORY


M59PW016-100M1 ,16 MBIT (1MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORYLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. PDIP and SDIP Connections ..
M59PW064 ,64 MBIT (4MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORYfeatures an innovative command,ROM pin-out compatible, non-volatile LightFlash Multiple Word Progra ..
M59PW064-100M1 ,64 MBIT (4MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORYLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SO Connections . 5Figur ..
M59PW1282-100M1 ,128Mbit (two 64Mb, x16, Uniform Block, LightFlash™)3V Supply, Multiple Memory ProductLogic Diagram . . 4Table 1. Signal Names . . . 4Figure 3. SO Connections . 5Ta ..
M5K4164AL-15 , 65 536 BIT DYNAMIC RAM
M5L2764K-2 , 65536-BIT (8192-WORD BY 8-BIT) ERASABLE AND ELECTRICALLT REPROGRAMMABLE ROM
M-991-01SMTR , Call Progress Tone Generator
MA02303GJ-R7 ,2200-2600 MHz, RF power amplifier IC for 2.4 GHz ISM
MA100L , UART-to- USB Bridge Controller
MA10100 ,Small-signal deviceElectrical Characteristics T = 25°C ± 3°CaParameter Symbol Conditions Min Typ Max UnitReverse curr ..
MA10701 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..
MA10702 ,Small-signal deviceElectrical Characteristics T = 25°CaParameter Symbol Conditions Min Typ Max UnitReverse current (D ..


M59PW016-M59PW016-100M1
16 MBIT (1MB X16, UNIFORM BLOCK) 3V SUPPLY LIGHTFLASH™ MEMORY
1/26January 2004
M59PW016

16 Mbit (1Mb x16, Uniform Block)
3V Supply LightFlash™ Memory
FEATURES SUMMARY
MASK-ROM PIN-OUT COMPATIBLE SUPPLY VOLTAGE
–VCC = 2.7 to 3.6V for Read
–VPP = 11.4 to 12.6V for Program ACCESS TIME
–80ns at VCC = 3.0 to 3.6V 100, 110ns at VCC = 2.7 to 3.6V PROGRAMMING TIME 9µs per Word typical Multiple Word Programming Option
(2s typical Chip Program) SUITABLE FOR ON-BOARD
PROGRAMMING ERASE TIME 11s typical Chip Erase UNIFORM BLOCKS 8 blocks of 2 Mbits PROGRAM/ERASE CONTROLLER Embedded Word Program algorithms 10,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code: 88ADh
Figure 1. Packages
M59PW016
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. PDIP and SDIP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Setup Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Program Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . .11
3/26
M59PW016

Figure 6. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
VPP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Status Register Bit DQ1 is reserved.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 7. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 8. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11.Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 12.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 13. Chip Enable Controlled, Write AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 13.SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . .20
Table 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data.20
Figure 14.TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Outline . . . . . . . . . .21
Table 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12x20mm, Package Mechanical Data . .21
Figure 15.PDIP42 - 42 pin Plastic DIP, 600 mils width, Bottom View Package Outline . . . . . . . . .22
Table 16. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data . . . . . . . . . . . .22
Figure 16.SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . .23
Table 17. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, Package Mechanical Data. . . . . . .23
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 19. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
M59PW016
SUMMARY DESCRIPTION

The M59PW016 is a 16Mbit (1Mbx16), Mask-
ROM pin-out compatible, non-volatile LightFlash
memory, that can be read, erased and
reprogrammed. Read operations can be
performed using a single low voltage (2.7 to 3.6V)
supply. Program and Erase operations require an
additional VPP (11.4 to 12.6V) power supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into 8 uniform blocks that
can be erased independently so it is possible to
preserve valid data while old data is erased (see
Table 2, Block Addresses). Program and Erase
commands are written to the Command Interface
of the memory. An on-chip Program/Erase Con-
troller (P/E.C.) simplifies the process of program-
ming or erasing the memory by taking care of all of
the special operations that are required to update
the memory contents.
The M59PW016 features an innovative command,
Multiple Word Program, that is used to program
large streams of data. It greatly reduces the total
programming time when a large number of Words
are written to the memory at any one time. Using
this command the entire memory can be pro-
grammed in 2s, compared to 9s using the stan-
dard Word Program.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
Chip Enable and Output Enable signals control the
bus operation of the memory. They allow simple
connection to most microprocessors, often without
additional logic.
The memory is offered in SO44, TSOP48
(12x20mm), PDIP42 and SDIP42 packages. The
memory is supplied with all the bits erased (set to
’1’).
Figure 2. Logic Diagram Table 1. Signal Names
5/26
M59PW016
Figure 3. PDIP and SDIP Connections Figure 4. SO Connections
M59PW016
Figure 5. TSOP Connections Table 2. Block Addresses
7/26
M59PW016
SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19).
The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program Controller.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the command
sent to the Command Interface of the Program
Controller. When reading the Status Register they
report the status of the ongoing algorithm.
Data Inputs/Outputs (DQ8-DQ15).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing Bus Read operations to be
performed. It also controls the Bus Write opera-
tions, when VPP is in the VHH range.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operations of the memory. It
also allows Bus Write operations, when VPP is in
the VHH range.
VCC Supply Voltage.
The VCC Supply Voltage
supplies the power for Read operations.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program opera-
tions, ICC3.
VPP Program Supply Voltage.
VPP is both a
power supply and Write Protect pin. The two func-
tions are selected by the voltage range applied to
the pin.
When the VPP is in the VHH range (see Table 11,
DC Characteristic, for the relevant values) the Pro-
gram/Erase operation is enabled. During such op-
erations the VPP must be stable in the VHH range.
If the VPP is kept under the VHH range, particularly
in the voltage range 0 to 3.6V, any Program/Erase
operation is disabled or stopped.
Note that VPP must not be left floating or uncon-
nected as the device may become unreliable.
Vss Ground.
The VSS Ground is the reference
for all voltage measurements.
M59PW016
BUS OPERATIONS

There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 3, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs and applying a Low signal, VIL, to Chip En-
able and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 11, Read AC
Waveforms, and Table 12, Read AC Characteris-
tics, for details of when the output becomes valid.
Bus Write.
Bus Write operations write to the
Command Interface. Bus Write is enabled only
when VPP is set to VHH. A valid Bus Write opera-
tion begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Enable. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure
12, Write AC Waveforms, and Table 13, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby.
When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 11, DC Characteristics.
During program operation the memory will contin-
ue to use the Program Supply Current, ICC3, for
Program operation until the operation completes.
Automatic Standby.
If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature.
The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3, Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Table 3. Bus Operations

Note:1. X = VIL or VIH. XX = VIL, VIH or VHH When reading Status Register during Program/Erase algorithm execution VPP must be kept at VHH.
9/26
M59PW016
COMMAND INTERFACE

All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Tables 4 and 5, for a summary of the com-
mands.
Read/Reset Command.

The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
VPP must be set to VHH during the Read/Reset
command. If VPP is set to either VIL or VIH the com-
mand will be ignored. The command can be is-
sued, between Bus Write cycles before the start of
a program operation, to return the device to read
mode. Once the program operation has started the
Read/Reset command is no longer accepted.
Auto Select Command.

The Auto Select command is used to read the
Manufacturer Code and the Device Code. VPP
must be set to VHH during the Auto Select com-
mand. If VPP is set to either VIL or VIH the com-
mand will be ignored. Three consecutive Bus
Write operations are required to issue the Auto Se-
lect command. Once the Auto Select command is
issued the memory remains in Auto Select mode
until a Read/Reset command is issued, all other
commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH.
Word Program Command.

The Word Program command can be used to pro-
gram a Word to the memory array. VPP must be
set to VHH during Word Program. If VPP is set to ei-
ther VIL or VIH the command will be ignored, the
data will remain unchanged and the device will re-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the P/E.C.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’.
Multiple Word Program Command

The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written in the memory at
once. VPP must be set to VHH during Multiple Word
Program. If VPP is set either VIL or VIH the com-
mand will be ignored, the data will remain un-
changed and the device will revert to Read mode.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
Setup Phase.
The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 4, Multiple Word
Program Command and Figure 8, Multiple Word
Program Flowchart).
The Status Register must be read in order to
check that the P/E.C. has started (see Table 7 and
Figure 7).
Program Phase.
The Program Phase requires
n+1 Bus Write operations, where n is the number
of Words, to execute the programming phase (re-
fer to Table 5, Multiple Word Program and Figure
6, Multiple Word Program Flowchart).
Before any Bus Write operation of the Program
Phase, the Status Register must be read in order
to check that the P/E.C. is ready to accept the op-
eration (see Table 7 and Figure 7).
The Program Phase is executed in three different
sub-phases: The first Bus Write operation of the Program
Phase (the 4th of the command) latches the
Start Address and the first Word to be
programmed. Each subsequent Bus Write operation latches
the next Word to be programmed and
automatically increments the internal Address
Bus. It is not necessary to provide the address
of the location to be programmed but only a
Continue Address, CA (A17 to A19 equal to
M59PW016
the Start Address), that indicates to the PC
that the Program Phase has to continue. A0 to
A16 are ‘don’t care’. Finally, after all Words have been
programmed, a Bus Write operation (the
(n+1)th ) with a Final Address, FA (A17 or a
higher address pin different from the Start
Address), ends the Program Phase.
The memory is now set to enter the Verify Phase.
Verify Phase.
The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the P/E.C. is ready for the next oper-
ation or if the reprogram of the location has failed
(see Table 7 and Figure 7).
Three successive steps are required to execute
the Verify Phase of the command: The first Bus Write operation of the Verify
Phase latches the Start Address and the Word
to be verified. Each subsequent Bus Write operation latches
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
but only a Continue Address, CA (A17 to A19
equal to the Start Address). Finally, after all Words have been verified, a
Bus Write cycle with a Final Address, FA (A17
or a higher address pin different from the Start
Address) ends the Verify Phase.
Exit Phase.
After the Verify Phase ends, the Sta-
tus Register must be read to check if the command
has successfully completed or not (see Table 7
and Figure 7).
If the Verify Phase accomplishes successfully, the
memory returns to the Read mode and DQ6 stops
toggling.
On the contrary, if the P/E.C. fails to reprogram a
given location, the Verify Phase terminates, DQ6
continues toggling and error bit DQ5 is set in the
Status Register. If the error is due to a VPP failure
DQ4 is also set.
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the oper-
ation. Typical program times are given in Table 6.
Bus Read operations during the program opera-
tion will output the Status Register on the Data In-
puts/Outputs. See the section on the Status
Register for more details.
Note that the Multiple Word Program command
cannot change a bit set at ’0’ back to ’1’.
Block Erase Command.

The Block Erase command can be used to erase
a block. It sets all of the bits in the block to ’1’. All
previous data in the block is lost.
VPP must be set to VHH during Block Erase. If VPP
is set to either VIL or VIH the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode.
Six Bus Write operations are required to select the
block . The Block Erase operation starts the P/E.C.
after the last Bus Write operation. The Status Reg-
ister can be read after the sixth Bus Write opera-
tion. See the Status Register for details on how to
identify if the P/E.C. has started the Block Erase
operation.
During the Block Erase operation the memory will
ignore all commands. Typical block erase times
are given in Table 6. All Bus Read operations dur-
ing the Block Erase operation will output the Sta-
tus Register on the Data Inputs/Outputs. See the
section on the Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Chip Erase Command.

The Chip Erase command can be used to erase
the entire memory. It sets all of the bits in the mem-
ory to ’1’. All previous data in the memory is lost.
VPP must be set to VHH during Chip Erase. If VPP
is set to either VIL or VIH the command will be ig-
nored, the data will remain unchanged and the de-
vice will revert to Read/Reset mode. Six Bus Write
operations are required to issue the Chip Erase
Command and start the P/E.C.
During the erase operation the memory will ignore
all commands. It is not possible to issue any com-
mand to abort the operation. Typical chip erase
times are given in Table 6. All Bus Read opera-
tions during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
11/26
M59PW016
Table 4. Standard Commands

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The
Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ15 are Don’t Care.
Table 5. Multiple Word Program Command

Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don’t
Care, n = number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles

Note:1. TA = 25°C, VPP = 12V.
M59PW016
Figure 6. Multiple Word Program Flowchart
13/26
M59PW016
STATUS REGISTER

Bus Read operations from any address always
read the Status Register during Program and
Erase operations. The bits in the Status Register
are summarized in Table 7, Status Register Bits.
Data Polling Bit (DQ7).
The Data Polling Bit can
be used to identify whether the P/E.C. has suc-
cessfully completed its operation. The Data Poll-
ing Bit is output on DQ7 when the Status Register
is read.
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
Figure 7, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6).
The Toggle Bit can be used to
identify whether the P/E.C. has successfully com-
pleted its operation. The Toggle Bit is output on
DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
Figure 8, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5).
The Error Bit can be used to
identify errors detected by the P/E.C. The Error Bit
is set to ’1’ when a Program, Block Erase or Chip
Erase operation fails to write the correct data to
the memory. If the Error Bit is set a Read/Reset
command must be issued before other commands
are issued. The Error bit is output on DQ5 when
the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
VPP Status Bit (DQ4).
The VPP Status Bit can be
used to identify if any Program or Erase operation
has failed due to a VPP error. If VPP falls below VHH
during any Program or Erase operation, the oper-
ation aborts and DQ4 is set to ‘1’. If VPP remains at
VHH throughout the Program or Erase operation,
the operation completes and DQ4 is set to ‘0’.
Erase Timer Bit (DQ3).
The Erase Timer Bit can
be used to identify the start of P/E.C. operation
during a Block Erase command. Once the P/E.C.
starts erasing the Erase Timer Bit is set to ’1’. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2).
The Alternative
Toggle Bit can be used to monitor the P/E.C. dur-
ing Block Erase operations. The Alternative Tog-
gle Bit is output on DQ2 when the Status Register
is read.
During Block Erase operations the Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc., with successive
Bus Read operations from addresses within the
block being erased. Once the operation completes
the memory returns to Read mode.
After an Erase operation that causes the Error Bit
to be set, the Alternative Toggle Bit can be used to
identify where the error occurred. The Alternative
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read Operations from addresses
within a block that has not erased correctly. The
Alternative Toggle Bit does not change if the ad-
dressed block has erased correctly.
Multiple Word Program Bit (DQ0).
The Multiple
Word Program Bit can be used to indicate whether
the P/E.C. is active or inactive during Multiple
Word Program. When the P/E.C. has written one
Word and is ready to accept the next Word, the bit
is set to ‘0’.
Status Register Bit DQ1 is reserved.
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED