M54HC541K1 ,RAD-HARD OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)M54HC541RAD-HARD OCTAL BUS BUFFERWITH 3 STATE OUTPUTS (NON INVERTED)
M54HC541K1
RAD-HARD OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED)
1/11May 2004 HIGH SPEED:
tPD= 9ns (TYP.)at VCC =6V LOW POWER DISSIPATION:CC =4μA(MAX.)atTA =25°C HIGH NOISE IMMUNITY:NIH =VNIL= 28%VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL =6mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH≅ tPHL WIDE OPERATING VOLTAGE RANGE:CC (OPR)= 2Vto 6V PIN AND FUNCTION COMPATIBLE WITH SERIES 541 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION DEVICE FULLY COMPLIANT WITH
SCC-9401-047
DESCRIPTIONThe 54HC541is an advanced high-speed CMOS
OCTAL BUS BUFFER (3-STATE) fabricated with
silicon gateC2 MOS technology. The M54HC541a non inverting buffer.
The 3-STATE control gate operatesasa two input
AND such thatif either G1 and G2 are high,all
eight output arein the high impedance state.In
orderto enhance PC board layout the M54HC541
offera pinout having inputs and outputs on
opposite sidesof the package.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M54HC541RAD-HARD OCTAL BUS BUFFER
WITH3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION
ORDER CODESRev.1
M54HC5412/11
Figure1: IEC Logic Symbols
Figure2: Input And Output Equivalent Circuit Table1: Pin Description
Table2: Truth Table: Don’t Care: High Impedance
M54HC5413/11
Table3: Absolute Maximum RatingsAbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not implied
Table4: Recommended Operating Conditions
M54HC5414/11
Table5: DC Specifications
M54HC5415/11
Table6: AC Electrical Characteristics(CL=50 pF, Inputtr=tf= 6ns)
Table7: Capacitive Characteristics CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load.(Refer toTestCircuit). Averageoperating current canbeobtainedbythe followingequation. ICC(opr) =CPD xVCCxfIN+ICC/8(percircuit)
M54HC5416/11
Figure3: Test Circuit= 50pF/150pFor equivalent (includesjigand probe capacitance) =1KΩor equivalent =ZOUTof pulse generator (typically 50Ω)
Figure4: Waveform- Propagation Delay Times (f=1MHz; 50% duty cycle)
