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M54HC125D1STN/a6avaiRAD-HARD QUAD BUS BUFFER (3-STATE)


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M54HC125D1
RAD-HARD QUAD BUS BUFFER (3-STATE)
1/9March 2004 HIGH SPEED:
tPD= 8ns (TYP.)at VCC =6V LOW POWER DISSIPATION:CC =4μA(MAX.)atTA =25°C HIGH NOISE IMMUNITY:NIH =VNIL= 28%VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|= IOL =6mA (MIN) BALANCED PROPAGATION DELAYS:
tPLH≅ tPHL WIDE OPERATING VOLTAGE RANGE:CC (OPR)= 2Vto 6V PIN AND FUNCTION COMPATIBLE WITH SERIES 125 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION DEVICE FULLY COMPLIANT WITH
SCC-9401-039
DESCRIPTION

The M54HC125is an high speed CMOS QUAD
BUFFER (3-STATE) fabricated with silicon gate2 MOS technology.
The device requires the 3-STATE control inputG be set highto place the output into the high
impedance state.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M54HC125

RAD-HARD QUAD BUS BUFFER (3-STATE)
PIN CONNECTION
ORDER CODES
M54HC125
2/9
IEC LOGIC SYMBOLS
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS

AbsoluteMaximum Ratingsare those values beyond which damagetothe device mayoccur.Functional operation under these conditionsis
not implied
M54HC125
3/9
RECOMMENDED OPERATING CONDITIONS SPECIFICATIONS
M54HC125
4/9 ELECTRICAL CHARACTERISTICS (Inputtr=tf =6ns)
CAPACITIVE CHARACTERISTICS
CPD isdefinedasthe valueofthe IC’s internal equivalent capacitance whichis calculatedfrom theoperating current consumption without
load.(Referto Test Circuit). Average operatingcurrentcanbe obtainedbythe following equation.ICC(opr) =CPDxVCC xfIN +ICC/4 (perbuffer)
M54HC125
5/9
TEST CIRCUIT
= 50pF/150pFor equivalent (includesjigand probe capacitance) =1KΩor equivalent =ZOUTof pulse generator (typically 50Ω))
WAVEFORM1: PROPAGATION DELAY TIMES
(f=1MHz; 50% duty cycle)
M54HC125
6/9
WAVEFORM2: OUTPUT ENABLE AND DISABLE TIMES
(f=1MHz; 50% duty cycle)
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