M48T559Y-MH1TR ,64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXEDLogic Diagram■ WRITE PROTECT VOLTAGE(V = Power-fail Deselect Voltage):PFD– M48T559Y: 4.2V ≤ V ≤ 4.5 ..
M48T58-70MH1 ,5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAMAbsolute Maximum Ratings" may cause permanent damage to the device. This is astress rating only and ..
M48T58-70PC1 ,64 KBIT (8KB X 8) TIMEKEEPER SRAMLogic Diagram Table 1. Signal NamesV A0-A12 Address InputsCCDQ0-DQ7 Data Inputs / Outputs13 8Freque ..
M48T58Y-70 MH1TR ,64 KBIT (8KB X 8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 28-pin PCDIP, CAPHAT™ Package . 1Figure 2. 28-pin ..
M48T58Y-70MH1 ,64 KBIT (8KB X 8) TIMEKEEPER SRAMFEATURES SUMMARY■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. 28-pin PCDIP, CAPHAT™ PackageREAL TIM ..
M48T58Y-70MH1E ,64 KBIT (8KB X 8) TIMEKEEPER SRAMBlock Diagram . . 5OPERATION MODES . . . . . . . 6Table 2. Operating Modes 6RE ..
M-614T , DC Line Fileters
M-614T , DC Line Fileters
M61511FP , AUDIO SIGNAL PROCESSOR
M61511FP , AUDIO SIGNAL PROCESSOR
M61512FP , 5.1ch Electronic Volume
M61512FP , 5.1ch Electronic Volume
M48T559Y-MH1-M48T559Y-MH1TR
64 Kbit 8Kb x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED
1/18February 2000
M48T559Y64 Kbit (8Kb x8) TIMEKEEPER® SRAM
with ADDRESS/DATA MULTIPLEXED SOFTWARE and HARDWARE RESET for
WATCHDOG TIMER REGISTER COMPATIBLE with M48T59
TIMEKEEPER SRAM ADDRESS/DATA MULTIPLEXED I/O PINS WATCHDOG TIMER - MONITORS OUT of
CONTROL PROCESSOR or HUNG BUS ALARM with WAKE-UP in BATTERY MODE INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY FREQUENCY TEST OUTPUT for REAL TIME
CLOCK AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION WRITE PROTECT VOLTAGE
(VPFD = Power-fail Deselect Voltage): M48T559Y: 4.2V ≤ VPFD ≤ 4.5V PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP
CONTAINS the BATTERY and CRYSTAL MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACK-UP MODE
DESCRIPTIONThe M48T559Y TIMEKEEPER® RAM is an 8K x 8
non-volatile static RAM and real time clock. The
monolithic chip is available in the SNAPHAT pack-
age to provide a highly integrated battery backed-
up memory and real time clock solution.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
M48T559Y
Table 2. Absolute Maximum RatingsNote: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability.
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 1. Signal NamesInsertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is "M4T28-BR12SH1".
Caution: Do not place the SNAPHAT battery/crys-tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T559Y are integrated on one silicon chip. The
two circuits are interconnected at the upper eight
memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations
contain the year, month, date, day, hour, minute,
and second in 24 hour BCD format. Corrections for
28, 29 (leap year), 30, and 31 day months are
made automatically. Byte 1FF8h is the clock con-
trol register. This byte controls user access to the
clock information and also stores the clock calibra-
tion setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ read/write memory cells.
The M48T559Y includes a clock control circuit
which updates the clock bytes with current infor-
3/18
M48T559Ymation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
The M48T559Y also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion.
Table 3. Operating Modes (1)Note:1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. See Table 7 for details. AD0-AD7, AS0, AS1 active when E is high and VCC > VPFD.
When VCC is out of tolerance, the circuit write pro-
tects the SRAM, providing a high degree of data
security in the midst of unpredictable system oper-
ation brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects
the battery which maintains data and clock opera-
tion until valid power returns.
M48T559Y
Table 5. Capacitance (1, 2) (TA = 25 °C, f = 1 MHz)
Note:1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70 °C; VCC = 4.5V to 5.5V)
Note:1. Outputs deselected. Input leakage current on input RESET pins. AD0-AD7, AS0, AS1 active when E is high and VCC > VPFD. Negative spikes of –1V allowed for up to 10ns once per cycle. The IRQ pins is Open Drain. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0'.
Table 4. AC Measurement ConditionsNote that Output Hi-Z is defined as the point where data is no longer
driven.
5/18
M48T559Y
Table 7. Power Down/Up Trip Points DC Characteristics (1)(TA = 0 to 70 °C)
Note:1. All voltages referenced to VSS. At 25°C.
Table 8. Power Down/Up AC Characteristics (TA = 0 to 70 °C)
Note:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200μs after VCC pass-
es VPFD (min). VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
M48T559Y
Table 9. AC Characteristics (TA = 0 to 70 °C; VCC = 4.5V to 5.5V)
RAM OPERATIONFour control signals, AS0, AS1, R and W, are used
to access the M48T559Y. The address latches are
loaded from the address/data bus in response to
rising edge signals applied to the Address Strobe
0 (AS0) and Address Strobe 1 (AS1) signals. AS0
is used to latch the lower 8 bits of address, and
AS1 is used to latch the upper 5 bits of address.
It is not however necessary to follow any particular
order. The inputs are in parallel for the two ad-
dress bytes (upper and lower) and can be latched
in any order as long as the correct strobe is used.
It is necessary to meet the set-up and hold times
given in the AC specifications with valid address
information in order to properly latch the address.
If the upper and/or lower order addresses are cor-
rect from a prior cycle, it is not necessary to repeat
the address latching sequence.
A write operation requires valid data to be placed
on the bus (AD0-AD7), followed by the activation
of the Write Enable (W) line. Data on the bus will
be written to the RAM, provided that the write tim-
ing specifications are met. During a read cycle, the
Read Enable (R) signal is driven active. Data from
the RAM will become valid on the bus provided
that the RAM read access timing specifications are
met.
The W and R signals should never be active at the
same time. In addition, E must be active before
any control line is recognized (except for AD0-AD7
and AS0, AS1).
RESET INPUTThe M48T559Y provides two debounced inputs
which can generate an output Reset. The duration
and function of the Reset output is identical to a
Reset generated by a power cycle. Pulses shorter
than tR1 and tR2 will not generate a Reset condi-
tion (see Table 12 and Figure 13).
DATA RETENTION MODEShould the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as "don't care."
Note: A power failure during a write cycle may cor-rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below VPFD (min), the user can be as-
sured the memory will be in a write protected state,
provided the VCC fall time is not less than tF.
7/18
M48T559Y
M48T559Y
Table 10. Register MapKeys: S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to zero
Y = ’1’ or ’0’
Z = ’0’ and are Read only
AF = Alarm Flag
BL = Battery Low
WDS = Watchdog Steering Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
The M48T559Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. There-
fore, decoupling of the power supply lines is rec-
ommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T559Y for
an accumulated period of at least 7 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is discon-
nected, and the power supply is switched to exter-
nal VCC. Write protection continues until VCC
reaches VPFD (max) plus tREC. For more informa-
tion on Battery Storage Life refer to the Application
Note AN1012.
POWER-ON RESETThe M48T559Y continuously monitors VCC. When
VCC falls to the power fail detect trip point, the RST
pulls low (open drain) and remains low on power-
up for 40ms to 200ms after VCC passes VPFD. An
external pull-up resistor to VCC is required (1kΩ re-
sistor is recommended). The reset pulse remains
active with VCC at VSS.
9/18
M48T559Y
Stopping and Starting the OscillatorThe oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to ’1’ stops the oscillator. The M48T559Y is
shipped from STMicroelectronics with the STOP
bit set to a ’1’. When reset to a ’0’, the M48T559Y
oscillator starts within one second.
Calibrating the ClockThe M48T559Y is driven by a quartz controlled os-
cillator with a nominal frequency of 32,768Hz. The
devices are tested not to exceed 35 ppm (parts per
million) oscillator frequency error at 25°C, which
equates to about ±1.53 minutes per month. With
the calibration bits properly set, the accuracy of
each M48T559Y improves to better than ±4 ppm
at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T559Y design, however, employs period-
ic counter correction. The calibration circuit adds
or subtracts counts from the oscillator divider cir-
cuit at the divide by 256 stage, as shown in Figure
9. The number of times pulses are blanked (sub-
tracted, negative calibration) or split (added, posi-
tive calibration) depends upon the value loaded
into the five bit Calibration byte found in the Con-
trol Register. Adding counts speeds the clock up,
subtracting counts slows the clock down.
CLOCK OPERATIONS
Reading the ClockUpdates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a '1' is written to the
READ bit, D6 in the Control register (1FF8h). As
long as a '1' remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0'.
Setting the ClockBit D7 of the Control register (1FF8h) is the
WRITE bit. Setting the WRITE bit to a '1', like the
READ bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 9). Resetting the WRITE bit to a
'0' then transfers the values of all time registers
(1FF9h-1FFFh) to the actual TIMEKEEPER
counters and allows normal operation to resume.
After the WRITE bit is reset, the next clock update
will occur in one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
