M48T201V ,3.3V-5V TIMEKEEPER CONTROLLERAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....7DC AND AC ..
M48T201V85MH1 ,3.3V-5V TIMEKEEPER SupervisorAbsolute Maximum Ratings . . . . . . . 24DC AND AC PARAMETERS . 25Table 11. DC and AC Mea ..
M48T201V85MH1 ,3.3V-5V TIMEKEEPER SupervisorFEATURES SUMMARY . . . . . 1Figure 1. Package . . . . . . . 1DESCRIPTION . . . ..
M48T201V-85MH1 ,3.3V-5V TIMEKEEPER SupervisorLogic Diagram . . 4Table 1. Signal Names . . 4Figure 3. SOIC Connections . . . . ..
M48T201V-85MH1E ,3.3V-5V TIMEKEEPER SupervisorFEATURES SUMMARY■ CONVERTS LOW POWER SRAM INTO Figure 1. PackageNVRAMs■ YEAR 2000 COMPLIANTSNAPHAT ..
M48T201V-85MH1F ,3.3V-5V TIMEKEEPER SupervisorM48T201YM48T201V®5.0 or 3.3V TIMEKEEPER Supervisor
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M48T201V
3.3V-5V TIMEKEEPER CONTROLLER
1/32July 2002
M48T201Y
M48T201V5.0 or 3.3V TIMEKEEPER® SUPERVISOR
FEATURES SUMMARY CONVERTS LOW POWER SRAM INTO
NVRAMs YEAR 2000 COMPLIANT BATTERY LOW FLAG INTEGRATED REAL TIME CLOCK, POWER-
FAIL CONTROL CIRCUIT, BATTERY and
CRYSTAL WATCHDOG TIMER CHOICE OF WRITE PROTECT VOLTAGES
(VPFD= Power-fail Deselect Voltage): M48T201Y: VCC= 4.5to 5.5V
4.1V ≤ VPFD ≤ 4.5V M48T201V: VCC= 3.0to 3.6V
2.7V ≤ VPFD ≤ 3.0V MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE THE BATTERY BACKED-UP MODE PACKAGINGINCLUDESA 44-LEAD SOIC and
SNAPHAT® TOP(tobe ordered separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION FORA SNAPHAT® TOP
WHICH CONTAINS THE BATTERY and
CRYSTAL
M48T201Y, M48T201V2/32
TABLE OF CONTENTS
DESCRIPTION ...... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....4Logic Diagram (Figure 2.). ...... ....... ...... ....... ...... ....... ...... ...... .....4
Signal Names (Table1.).. ...... ....... ...... ....... ...... ....... ...... ...... .....4
SOIC Connections (Figure3.) .... ....... ...... ....... ...... ....... ...... ...... .....5
Hardware Hookup (Figure 4.) .... ....... ...... ....... ...... ....... ...... ...... .....6
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....7Absolute Maximum Ratings (Table2.) .... ...... ....... ...... ....... ...... ...... .....7
AND AC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... .....8 and AC Measurement Conditions (Table3.)... ....... ...... ....... ...... ...... .....8 Testing Load Circuit (Figure 5.)....... ...... ....... ...... ....... ...... ...... .....8
Capacitance (Table4.)... ...... ....... ...... ....... ...... ....... ...... ...... .....8 Characteristics (Table5.) .... ....... ...... ....... ...... ....... ...... ...... .....9
OPERATION. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10Address Decoding. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Operating Modes (Table 6.)...... ....... ...... ....... ...... ....... ...... ...... ....10
READ Mode...... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
GCON Timing When Switching Between RTC and External SRAM (Figure6.) ...... ...... ....11
READ Cycle Timing: RTC and External RAM Control Signals (Figure7.)... ...... ...... ....12
READ Mode AC Characteristics(Table 7.). ...... ....... ...... ....... ...... ...... ....13
WRITEMode ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....14
WRITE Cycle Timing: RTC& External RAM Control Signals (Figure8.) .... ...... ...... ....14
WRITEMode AC Characteristics (Table8.) ...... ....... ...... ....... ...... ...... ....15
Data Retention Mode..... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Power Down/Up Mode AC Waveforms (Figure9.). ....... ...... ....... ...... ...... ....16
Power Down/Up Mode AC Characteristics(Table 9.) ...... ...... ....... ...... ...... ....17
3/32
M48T201Y, M48T201V
CLOCKOPERATION. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....17TIMEKEEPER® Registers. ...... ....... ...... ....... ...... ....... ...... ...... ....17
Reading the Clock. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....17
Setting the Clock.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....17
Stopping and Starting the Oscillator ...... ...... ....... ...... ....... ...... ...... ....17
TIMEKEEPER® Register Map (Table 10.). ...... ....... ...... ....... ...... ...... ....18
Setting the Alarm Clock... ...... ....... ...... ....... ...... ....... ...... ...... ....19
Alarm Interrupt ResetWaveforms (Figure 10.) .... ....... ...... ....... ...... ...... ....19
Alarm Repeat Modes (Table 11.). ....... ...... ....... ...... ....... ...... ...... ....19
Back-up Mode Alarm Waveforms (Figure 11.) .... ....... ...... ....... ...... ...... ....20
Watchdog Timer.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....20
Square Wave Output..... ...... ....... ...... ....... ...... ....... ...... ...... ....21
Square Wave Output Frequency (Table 12.)...... ....... ...... ....... ...... ...... ....21
Power-on Reset... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....22
ResetInputs (RSTIN1& RSTIN2). ....... ...... ....... ...... ....... ...... ...... ....22
RSTIN1 and RSTIN2 Timing Waveforms (Figure 12.) ..... ...... ....... ...... ...... ....22
ResetACCharacteristics (Table 13.) ..... ...... ....... ...... ....... ...... ...... ....22
Calibrating the Clock ..... ...... ....... ...... ....... ...... ....... ...... ...... ....23
Battery Low Warning ..... ...... ....... ...... ....... ...... ....... ...... ...... ....24
Initial Power-on Defaults.. ...... ....... ...... ....... ...... ....... ...... ...... ....24
DefaultValues (Table 14.). ...... ....... ...... ....... ...... ....... ...... ...... ....24
Crystal Accuracy Across Temperature (Figure 13.) ....... ...... ....... ...... ...... ....25
Calibration Waveform (Figure 14.) ....... ...... ....... ...... ....... ...... ...... ....25
VCC Noise And Negative Going Transients. ...... ....... ...... ....... ...... ...... ....26
Supply Voltage Protection (Figure 15.) .... ...... ....... ...... ....... ...... ...... ....26
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....27SNAPHAT®Battery Table (Table 16.) .... ...... ....... ...... ....... ...... ...... ....27
PACKAGE MECHANICAL INFORMATION... ...... ....... ...... ....... ...... ...... ....28
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....31
M48T201Y, M48T201V4/32
DESCRIPTIONThe M48T201Y/V are self-contained devices that
includea real time clock (RTC), programmable
alarms,a watchdog timer, anda square wave out-
put which provides controlofupto 512Kx8of ex-
ternal low-power static RAM. Accessto all RTC
functions and the external RAMis the same as
conventional bytewide SRAM. The 16 TIME-
KEEPER® registers offer year, month, date, day,
hour, minute, second, calibration, alarm, century,
watchdog, and square wave output data. External- attached static RAMs are controlled by the
M48T201Y/V via the GCON and ECON signals.
The 44-pin, 330mil SOIC provides sockets with
gold plated contactsat both ends for direct con-
nectiontoa separate SNAPHAT® housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on topof the SOIC package after the
completionof the surface mount process.
Insertionof the SNAPHAT housing after reflow
prevents potential battery damage dueto the high
temperatures required for device surface-mount-
ing. The SNAPHAT housingis keyedto prevent
reverse insertion. The SOIC and battery packages
are shipped separatelyin plastic anti-static tubesin Tape& Reel form. For the 44-lead SOIC, the
battery/crystal package (e.g., SNAPHAT) part
numberis “M4Txx-BR12SH” (see Table 16, page
27).
Caution: Do not place the SNAPHAT battery/crys-
tal topin conductive foamas this will drain the lith-
ium button-cell battery.
Table1. Signal Names
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M48T201Y, M48T201V
M48T201Y, M48T201V
6/32
Figure4. Hardware Hookup
Note:1.Ifthe second chip enablepin (E2)is unused,it shouldbetiedto VOUT.
7/32
M48T201Y, M48T201V
MAXIMUM RATING
Stressing the deviceabove therating listedinthe
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operationof the deviceat
theseor any other conditions above those indicat-in the Operating sectionsof this specificationis
not implied. Exposureto Absolute Maximum Rat-
ing conditionsfor extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table2. Absolute Maximum Ratings
Note:1. Reflowat peak temperatureof 215°Cto 225°Cfor<60 seconds (total thermal budgetnotto exceed 180°Cfor between90to120
seconds).
CAUTION: Negative undershoots below –0.3Varenot allowedonanypin whileinthe Battery Back-up mode.
CAUTION:Do NOT wave solder SOICto avoid damaging SNAPHAT sockets.
M48T201Y, M48T201V
8/32 AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristicsof the device. The parametersin
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listedin the relevant tables. De-
signers should check that the operating conditions their projects match the measurement condi-
tions when using the quoted parameters.
Table3. DC and AC Measurement Conditions
Note: Output HighZis definedasthe point where dataisno longer driven.
Table4. Capacitance
Note:1. Effective capacitance measured with power supplyat5V; sampled only,not 100% tested.At 25°C;f= 1MHz. Outputs deselected.
9/32
M48T201Y, M48T201V
Table5. DC Characteristics
Note:1. Validfor Ambient Operating Temperature:TA=0to 70°Cor –40to 85°C; VCC=4.5to 5.5Vor3.0to 3.6V (except where noted). RSTIN1and RSTIN2internally pulled-upto VCCthrough100KΩresistor.WDI internallypulled-downto VSS through 100KΩ resistor. Outputs deselected. IBAT (OSC ON)= Industrial Temperature Range- Grade6 device. For IRQ/FT& RST pins (Open Drain). Conditioned outputs(ECON -GCON)can only sustain CMOS leakage currents inthe batteryback-up mode. Higher leakage currents
will reduce batterylife. External SRAM must match TIMEKEEPER SUPERVISOR chip VCC specification.
M48T201Y, M48T201V
10/32
OPERATION
Automatic backup and write protection for an ex-
ternal SRAMis provided through VOUT,ECON, and
GCON pins. (Users are urgedto insure that voltage
specifications, for both the SUPERVISOR chip
and external SRAM chosen, are similar.) The
SNAPHAT® containing the lithium energy source usedto retain the RTC and RAM datain the ab-
senceof VCC power through the VOUT pin. The
chip enable outputto RAM (ECON) and the output
enable outputto RAM (GCON) are controlled dur-
ing power transientsto prevent data corruption.
The dateis automatically adjusted for months with
less than31 days and correctsfor leap years (valid
until 2100). The internal watchdog timer provides
programmable alarm windows.
The nine clock bytes (7FFFFh-7FFF9h and
7FFF1h) are not the actual clock counters, they
are memory locations consisting of BiPORT™
READ/WRITE memory cells within the static RAM
array. Clock circuitry updates the clock bytes with
current information once per second. The informa-
tion canbeaccessedby the userin thesameman-
ner as any other locationin the static memory
array. Byte 7FFF8his the clock control register.
This byte controls user accessto the clock infor-
mation and also stores the clock calibration set-
ting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate eithera resetor interrupt, dependingon the stateof the Watch-
dog Steering Bit (WDS). Bytes 7FFF6h-7FFF2h
include bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and secondsof the clock
registers. Byte 7FFF1h contains century informa-
tion. Byte 7FFF0h contains additional flag informa-
tion pertainingto the watchdog timer, the alarm
condition, the battery status and square wave out-
put operation.4 bits are included within this regis-
ter (RS0-RS3) that are used to program the
Square Wave Output Frequency (see Table 12,
page 21). The M48T201Y/V also hasits own Pow-
er-Fail Detect circuit. This control circuitry con-
stantly monitors the supply voltage for an outof
tolerance condition. When VCCis outof tolerance,
the circuit write protects the TIMEKEEPER® regis-
ter data and external SRAM, providing data secu-
rityin the midstof unpredictable system operation. VCC falls below the Battery Back-up Switchover
Voltage (VSO), the control circuitry automatically
switchesto the battery, maintaining data and clock
operation until valid poweris restored.
Address Decoding
The M48T201Y/V accommodates 19 address
lines (A0-A18) which allow direct connectionofup 512K bytesof static RAM. Regardlessof SRAM
density used, timekeeping, watchdog, alarm, cen-
tury, flag, and control registers are locatedin the
upper RAM locations.All TIMEKEEPER registers
residein the upper RAM locations without conflict inhibiting the GCON (output enable RAM) signal
during clock access. The RAM's physical locations
are transparentto the user and the memory map
looks continuous from the first clock addressto the
upper most attached RAM addresses.
Table6. Operating Modes
Note:X=VIHor VIL;VSO= Battery Back-up Switchover Voltage See Table9, page17for details.
11/32
M48T201Y, M48T201V
READ Mode
The M48T201Y/V executesa READ Cycle when-
everW (WRITE Enable)is high andE (Chip En-
able)is low. The unique address specifiedby the
address inputs (A0-A18) defines which oneof the
on-chip TIMEKEEPER® registers or external
SRAM locationsistobe accessed. When the ad-
dress presentedto the M48T201Y/Visin the
rangeof 7FFFFh-7FFF0h, oneof the on-board
TIMEKEEPER registersis accessed and valid
data willbe availableto the eight data output driv-
ers within tAVQV after the address input signalis
stable, providing that theE andG access times
are also satisfied.If they are not, then data access
mustbe measured from the latter occurring signalorG) and the limiting parameteris either tELQV
forEor tGLQVforG rather than the address access
time. When oneof the on-chip TIMEKEEPER reg-
istersis selected for READ, the GCON signal will
remain inactive throughout the READ Cycle.
When the address value presented to the
M48T201Y/Vis outside the rangeof TIMEKEEP- registers, an external SRAM location will be
selected.In this case theG signal will be passed the GCON pin, with the specified delay timesof
tAOELor tOERL.
M48T201Y, M48T201V
12/32
13/32
M48T201Y, M48T201V
Table7. READ Mode AC Characteristics
Note:1. Validfor Ambient Operating Temperature:TA=0to 70°Cor –40to 85°C; VCC=4.5to 5.5Vor3.0to 3.6V (except where noted).CL= 5pF.
M48T201Y, M48T201V
14/32
WRITE Mode
The M48T201Y/Visin the WRITE Mode whenever (WRITE Enable) andE (Chip Enable) are low
state after the address inputs are stable. The starta WRITEis referenced from the latter occurring
falling edgeofWorE.A WRITEis terminatedby
the earlier rising edgeofWorE. The addresses
must be held valid throughout the cycle.EorW
must return highfora minimumof tEHAX from Chip
Enableor tWHAX from WRITE Enable priorto the
initiationof another READor WRITE Cycle. Data- mustbe valid tDVWH priorto the endof WRITE
and remain validfor tWHDX afterward.G shouldbe
kept high during WRITE Cyclesto avoid bus con-
tention; although,if the output bus has been acti-
vatedbya low onE andGa lowonW will disable
the outputs tWLQZ afterW falls.
When the address value presented to the
M48T201Y/V during the WRITEisin the rangeof
7FFFFh-7FFF0h, one of the on-board TIME-
KEEPER® registers will be selected and data will written into the device. When the address value
presentedto M48T201Y/Vis outside the rangeof
TIMEKEEPER registers, an external SRAM loca-
tionis selected.
Figure8. WRITE Cycle Timing: RTC& External RAM Control Signals
15/32
M48T201Y, M48T201V
Table8. WRITE Mode AC Characteristics
Note:1. Validfor Ambient Operating Temperature:TA=0to 70°Cor –40to 85°C; VCC=4.5to 5.5Vor3.0to 3.6V (except where noted).CL= 5pFIfE goeslow simultaneously withW going low,the outputs remaininthe high impedance state.
M48T201Y, M48T201V
16/32
Data Retention Mode
With valid VCC applied, the M48T201Y/V can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M48T201Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
Thisis accomplished by internally inhibiting ac-
cessto the clock registers via theE signal.At this
time,the Resetpin (RST)is driven active and will
remain active until VCC returnsto nominal levels.
External RAM accessis inhibitedina similar man-
nerby forcing ECONtoa high level. This levelis
within 0.2Vof the VBAT.ECON will remainat this
level as long as VCC remainsat an out-of-toler-
ance condition. When VCC falls below the levelof
the battery (VBAT), power inputis switched from
the VCC pinto the SNAPHAT® battery and the
clock registers are maintained from the attached
battery supply. External RAMis also poweredby
the SNAPHAT battery. All outputs except GCON,
ECON,RST,IRQ/FT and VOUT, become high im-
pedance. The VOUT pinis capableof supplying
100μAof currentto the attached memory with less
than 0.3V drop under this condition. On power up,
when VCC returnstoa nominal value, write protec-
tion continuesfor 200ms (max)by inhibiting ECON.
The RST signal also remains active during this
time (see Figure9).
Note: Most low power SRAMs on the market to-
day can be used with the M48T201Y/V TIME-
KEEPER® SUPERVISOR. There are, however
some criteria which shouldbe usedin making the
final choiceof anSRAM touse.
The SRAM must be designedina way where the
chip enable input disablesall other inputsto the
SRAM. This allows inputsto the M48T201Y/V and
SRAMsto be “Don't care” once VCC falls below
VPFD (min). The SRAM should also guarantee
data retention downto VCC= 2.0V. The chip en-
able access time must be sufficientto meet the
system needs with the chip enable (and output en-
able) output propagation delays included.
