M41T81SMY6F ,Serial real-time clock (RTC) with alarmapplications)■ V = 2.7 to 5.5 VCC■ 2.5 V ≤ V ≤ 2.7 VPFD ■ Power-down time-stamp (HT bit) wh ..
M41T83RMY6E , Serial I2C bus RTC with battery switchover
M41T83RMY6F ,Serial I2C bus real-time clock (RTC) with battery switch-overM41T82, M41T832Serial I C bus real-time clock (RTC) with battery switchoverDatasheet - production d ..
M41T83RQA6F ,Serial I2C bus real-time clock (RTC) with battery switch-overlogic diagram . . . . . 7Figure 3. SO8 (M) connections (M41T82) . . . . . .9Figure 4. QF ..
M41T83ZMY6E , Serial I2C bus RTC with battery switchover
M41T83ZMY6F ,Serial I2C bus real-time clock (RTC) with battery switch-overFeatures RoHS compliance: lead-free components are Ultra-low battery supply current of 365 nAcom ..
M5M5V216ATP-55HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ATP-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ATP-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216AWG-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V408BFP-85HI , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V408BKV-85H , 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
M41T81SMY6F
Serial real-time clock (RTC) with alarm
May 2012 Doc ID 10773 Rev 7 1/32
M41T81SSerial access real-time clock (RTC) with alarms
Datasheet − production data
Features Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century 32 KHz crystal oscillator with integrated load
capacitance (12.5 pf) which provides
exceptional oscillator stability and high crystal
series resistance operation) Oscillator stop detection (monitors clock
operation) Serial interface supports I2 C bus (400 kHz
protocol) Ultra-low battery supply current of 0.6 µA (typ) 2.0 to 5.5 V clock operating voltage Automatic switchover and deselect circuitry
(fixed reference) which provides full operation
in 3.0 V applications) VCC = 2.7 to 5.5 V 2.5 V ≤ VPFD ≤ 2.7 V Power-down time-stamp (HT bit) which allows
determination of time elapsed in battery
backup Battery low flag Programmable alarm and interrupt function
(valid even during battery backup mode) Accurate programmable watchdog timer (from
62.5 ms to 128 s) Software clock calibration (to compensate for
crystal deviation due to temperature) Operating temperature of –40 to 85 °C Package options include an 8-lead SOIC or
18-lead embedded crystal SOIC
Contents M41T81S2/32 Doc ID 10773 Rev 7
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting alarm clock registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Century bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Battery low warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M41T81S Contents
Doc ID 10773 Rev 7 3/32
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of tables M41T81S
4/32 Doc ID 10773 Rev 7
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. SO8 – 8-lead plastic small outline (150 mils body width), package mechanical data. . . . . 28
Table 15. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
M41T81S List of figures
Doc ID 10773 Rev 7 5/32
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. 18-pin, 300 mil SOIC (MY) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Backup mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline . . . . . . . . . . . 29
Description M41T81S
6/32 Doc ID 10773 Rev 7
1 Description
The M41T81S is a low-power serial real-time clock (RTC) with a built-in 32.768 kHz
oscillator (external crystal controlled). Eight bytes of the SRAM are used for the
clock/calendar function and are configured in binary-coded decimal (BCD) format. An
additional 12 bytes of SRAM provide status/control of alarm, watchdog and square wave
functions. Addresses and data are transferred serially via a two line, bidirectional I2C
interface. The built-in address register is incremented automatically after each WRITE or
READ data byte.
The M41T81S has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button supply
when a power failure occurs. Functions available to the user include a non-volatile, time-of-
day clock/calendar, alarm interrupts, watchdog timer and programmable square wave
output. The eight clock address locations contain the century, year, month, date, day, hour,
minute, second and tenths/hundredths of a second in 24-hour BCD format. Corrections for
28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically.
The M41T81S is supplied in either an 8-pin SOIC or an 18-pin 300 mil SOIC package which
includes an embedded 32 KHz crystal.
The 18-pin, embedded crystal SOIC requires only a user-supplied battery to provide non-
volatile operation.
Figure 1. Logic diagram For SO8 package only
M41T81S Description
Doc ID 10773 Rev 7 7/32
Table 1. Signal names
Figure 2. 8-pin SOIC (M) connections Open drain output
Figure 3. 18-pin, 300 mil SOIC (MY) connections NC and NF pins should be tied to VSS. Pins 2 and 3 are internally shorted together. Pins 17 and 16 are
internally shorted together. Open drain output For SO8 package only. NC and NF pins should be tied to VSS.
Description M41T81S
8/32 Doc ID 10773 Rev 7
Figure 4. Block diagram Open drain output Square wave function has the highest priority on IRQ/FT/OUT/SQW output.
M41T81S Operation
Doc ID 10773 Rev 7 9/32
2 Operation
The M41T81S clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
1. T enths/hundredths of a second register
2. Seconds register
3. Minutes register
4. Century/hours register
5. Day register
6. Date register
7. Month register
8. Year register
9. Calibration register
10. Watchdog register
11 - 15. Alarm registers
16. Flags register
17 - 19. Reserved
20. Square wave register
The M41T81S clock continually monitors VCC for an out-of-tolerance condition. Should VCC
fall below VPFD, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. Once VCC falls below the
switchover voltage (VSO), the device automatically switches over to the battery and powers
down into an ultra-low current mode of operation to preserve battery life. If VBAT is less than
VPFD, the device power is switched from VCC to VBAT when VCC drops below VBAT . If VBAT is
greater than VPFD, the device power is switched from VCC to VBAT when VCC drops below
VPFD. Upon power-up, the device switches from battery to VCC at VSO. When VCC rises
above VPFD, it will recognize the inputs.
For more information on battery storage life refer to application note AN1012, "Predicting the
battery life and data retention period of NVRAMs and serial RTCs" .
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
Operation M41T81S
10/32 Doc ID 10773 Rev 7
The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
M41T81S Operation
Doc ID 10773 Rev 7 11/32
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 5. Serial bus data transfer sequence
Figure 6. Acknowledgement sequence
READ mode
In this mode the master reads the M41T81S slave after setting the slave address (see
Figure 8 on page 12). Following the WRITE mode control bit (R/W=0) and the acknowledge
bit, the word address 'An' is written to the on-chip address pointer. Next the START condition
and slave address are repeated followed by the READ mode control bit (R/W=1). At this
point the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
clock. The M41T81S slave transmitter will now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges the new byte and the address pointer is
incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-13h).
Operation M41T81S
12/32 Doc ID 10773 Rev 7
Note: This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the
M41T81S slave without first writing to the (volatile) address pointer. The first address that is
read is the last one stored in the pointer (see Figure 9 on page 12).
Figure 7. Slave address location
Figure 8. READ mode sequence
Figure 9. Alternative READ mode sequence
M41T81S Operation
Doc ID 10773 Rev 7 13/32
WRITE mode
In this mode the master transmitter transmits to the M41T81S slave receiver. Bus protocol is
shown in Figure 10 on page 13. Following the START condition and slave address, a logic '0'
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T81S slave receiver
will send an acknowledge clock to the master transmitter after it has received the slave
address see Figure 7 on page 12 and again after it has received the word address and each
data byte.
Data retention mode
With valid VCC applied, the M41T81S can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the power input will be switched from the
VCC pin to the battery when VCC falls below the battery backup switchover voltage (VSO). At
this time the clock registers will be maintained by the attached battery supply. On power-up,
when VCC returns to a nominal value, write protection continues for tREC.
For a further, more detailed review of lifetime calculations, please see application note
AN1012.
Figure 10. WRITE mode sequence
Clock operation M41T81S
14/32 Doc ID 10773 Rev 7
3 Clock operation
The 20-byte register map (see Table 2: Clock register map on page 15) is used to both set
the clock and to read the date and time from the clock, in a binary coded decimal format. enths/hundredths of seconds, seconds, minutes, and hours are contained within the first
four registers.
Note: T enths/hundredths of seconds cannot be written to any value other than “00.”
Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY
ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle,
either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the
day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and
years. The ninth clock register is the calibration register (this is described in the clock
calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1'
will cause the oscillator to stop. If the device is expected to spend a significant amount of
time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0'
the oscillator restarts within one second.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
Power-down time-stamp
When a power failure occurs, the HALT (HT) bit will automatically be set to a '1.' This will
prevent the clock from updating the registers, and will allow the user to read the exact time
of the power-down event. Resetting the HT bit to a '0' will allow the clock to update the
registers with the current time. For more information, please refer to AN1572, “Power-down
time-stamp function in serial real-time clocks (RTCs)”.
Clock registers
The M41T81S offers 20 internal registers which contain clock, alarm, watchdog, flags,
square wave and calibration data. These registers are memory locations which contain
external (user accessible) and internal copies of the data (usually referred to as BiPORT™
cells). The external copies are independent of internal functions except that they are
updated periodically by the simultaneous transfer of the incremented internal copy. The
internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock
address.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a stop condition or when
the pointer increments to any non-clock address (08h-13h).
Clock and alarm registers store data in BCD. Calibration, watchdog and square wave
registers store data in binary format.
M41T81S Clock operation
Doc ID 10773 Rev 7 15/32
Table 2. Clock register map
0 = Must be set to '0'
ABE = Alarm in battery backup mode enable bit
AF = Alarm flag (read only)
AFE = Alarm flag enable flag
BL = Battery low bit
BMB0-BMB4 = Watchdog multiplier bits
CB = Century bit
CEB = Century enable bit
FT = Frequency test bit
HT = Halt update bit
OF = Oscillator fail flag
OFIE = Oscillator fail interrupt enable
OUT = Output level
RB0-RB1 = Watchdog resolution bits
RPT1-RPT5 = Alarm repeat mode bits
RS0-RS3 = SQW frequency
S = Sign bit
SQWE = Square wave enable
ST = Stop bit
WDF = Watchdog flag (read only)
Clock operation M41T81S
16/32 Doc ID 10773 Rev 7
Calibrating the clock
The M41T81S is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator
frequency error at 25o C, which equates to about +1.9 to –1.1 minutes per month (see
Figure 11 on page 17). When the calibration circuit is properly employed, accuracy improves
to better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature. The M41T81S design employs
periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage, as shown in Figure 12 on page 17. The
number of times pulses which are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
calibration register. Adding counts speeds the clock up, subtracting counts slows the clock
down.
The calibration bits occupy the five lower order bits (D4-D0) in the calibration register 08h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register (see Figure 12 on page 17).
Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35 seconds per month which corresponds to a
total range of +5.5 or –2.75 minutes per month. wo methods are available for ascertaining how much calibration a given M41T81S may
require.
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in application
note AN934, “TIMEKEEPER® calibration.” This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the IRQ/FT/OUT/SQW pin. The pin will toggle at 512 Hz, when the stop bit (ST, D7 of
01h) is '0,' the frequency test bit (FT, D6 of 08h) is '1,' the alarm flag enable bit (AFE, D7 of
0Ah) is '0,' and the square wave enable bit (SQWE, D6 of 0Ah) is '0' and the watchdog
register (09h = 0) is reset.
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
