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M41T80M6STN/a1660avaiSerial Access RTC with Alarms
M41T80M6EPb-freeN/a215avaiSerial Access RTC with Alarms
M41T80M6FSTMicroelectronicsN/a164950avaiSerial Access RTC with Alarms
M41T80M6FSTN/a5200avaiSerial Access RTC with Alarms
M41T80M6TRSTMN/a550avaiSerial Access RTC with Alarms


M41T80M6F ,Serial Access RTC with AlarmsAbsolute Maximum Ratings . . . . . . . 14DC AND AC PARAMETERS . 152/20M41T80Table 8. Oper ..
M41T80M6F ,Serial Access RTC with AlarmsFEATURES SUMMARY■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE Figure 2. Package■ COUNTERS FOR TENTHS/HUNDRE ..
M41T80M6TR ,Serial Access RTC with AlarmsFEATURES SUMMARY . . . . . 1Figure 1.
M41T81 ,512 BIT (64 BIT SERIAL ACCESS RTC SRAM WITH ALARMSElectrical Characteristics (Table 6.) . . . . 8OPERATION . . . . . . 92-Wire Bus Charac ..
M41T81 ,512 BIT (64 BIT SERIAL ACCESS RTC SRAM WITH ALARMSLogic Diagram Table 1. Signal Names(1)(1)Oscillator InputV VXICC BAT(1)Oscillator OutputXOIRQ/OUT/ ..
M41T81M6 ,Serial Access Real-Time Clock with AlarmsBlock Diagram . . 6OPERATION . . . . . . 72-Wire Bus Characteristics . . . . . ..
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208KV-10LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V208KV-12LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V216ATP-55HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ATP-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM


M41T80M6-M41T80M6E-M41T80M6F-M41T80M6TR
Serial Access RTC with Alarms
1/20June 2004
M41T80

Serial Access RTC with Alarms
FEATURES SUMMARY
M41T80
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 3. 8-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 5. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 6. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 7. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 2. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 8. Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 9. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 10.Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 11.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 3. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 12.Alarm Interrupt Reset Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 4. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 5. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Full-time 32kHz Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Preferred Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 6. Preferred Power-on Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/20
M41T80

Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 13.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 11. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 14.SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing17
Table 12. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . .17
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
M41T80
SUMMARY DESCRIPTION

The M41T80 Serial Access TIMEKEEPER®
SRAM is a low power Serial RTC with a built-in
32.768kHz oscillator (external crystal controlled).
Eight registers (see Table 3., page 11) are used
for the clock/calendar function and are configured
in binary coded decimal (BCD) format. An addi-
tional 12 registers provide status/control of Alarm,
32kHz output, and Square Wave functions. Ad-
dresses and data are transferred serially via a two
line, bi-directional I2 C interface. The built-in ad-
dress register is incremented automatically after
each WRITE or READ data byte.
Functions available to the user include a time-of-
day clock/calendar, Alarm interrupts, 32kHz out-
put, and programmable Square Wave output. The
eight clock address locations contain the century,
year, month, date, day, hour, minute, second and
tenths/hundredths of a second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
year 2100), 30 and 31 day months are made auto-
matically.
The M41T80 is supplied in an 8-pin SOIC.
Figure 4. Block Diagram

Note:1. Open Drain output
5/20
M41T80
OPERATION

The M41T80 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 20 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. 32kE Bit
11 - 16. Alarm Registers
17 - 19. Reserved
20 - Square Wave Register
2-Wire Bus Characteristics

The bus is intended for communication between
different IC’s. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the
bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy.
Both data and clock lines remain
High.
Start data transfer.
A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer.
A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid.
The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge.
Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T80
Figure 5. Serial Bus Data Transfer Sequence
Figure 6. Acknowledgement Sequence
7/20
M41T80
Figure 7. Bus Timing Requirements Sequence
Table 2. AC Characteristics

Note:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
M41T80
READ Mode

In this mode the master reads the M41T80 slave
after setting the slave address (Figure 9., page8).
Following the WRITE Mode Control Bit (R/W=0)
and the Acknowledge Bit, the word address 'An' is
written to the on-chip address pointer. Next the
START condition and slave address are repeated
followed by the READ Mode Control Bit (R/W=1).
At this point the master transmitter becomes the
master receiver. The data byte which was ad-
dressed will be transmitted and the master receiv-
er will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Clock. The
M41T80 slave transmitter will now place the data
byte at address An+1 on the bus, the master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-13h).
Note: This is true both in READ Mode and WRITE

Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T80 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 10., page9).
9/20
M41T80
Figure 10. Alternative READ Mode Sequence
WRITE Mode

In this mode the master transmitter transmits to
the M41T80 slave receiver. Bus protocol is shown
in Figure 11., page 9. Following the START condi-
tion and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T80 slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 8., page 8 and again after it has re-
ceived the word address and each data byte.
M41T80
CLOCK OPERATION

The M41T80 is driven by a quartz-controlled oscil-
lator with a nominal frequency of 32,768Hz. The
accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the
time-base for the RTC.
The 20-byte Register Map (see Table 3., page 11)
is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal
format. Tenths/Hundredths of Seconds, Seconds,
Minutes, and Hours are contained within the first
four registers.
Note: A WRITE to any clock register will result in

the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register. Bit D7 of Register 01h contains
the STOP Bit (ST). Setting this bit to a '1' will cause
the oscillator to stop. If the device is expected to
spend a significant amount of time on the shelf, the
oscillator may be stopped to reduce current drain.
When reset to a '0' the oscillator restarts within
four seconds (typically one second).
The eight Clock Registers may be read one byte at
a time, or in a sequential block. Provision has been
made to assure that a clock update does not occur
while any of the eight clock addresses are being
read. If a clock address is being read, an update of
the clock registers will be halted. This will prevent
a transition of data during the READ.
TIMEKEEPER® Registers

The M41T80 offers 20 internal registers which
contain Clock, Alarm, 32kHz, Flag, Square Wave,
and Control data. These registers are memory lo-
cations which contain external (user accessible)
and internal copies of the data (usually referred to
as BiPORT™ TIMEKEEPER cells). The external
copies are independent of internal functions ex-
cept that they are updated periodically by the si-
multaneous transfer of the incremented internal
copy. The internal divider (or clock) chain will be
reset upon the completion of a WRITE to any clock
address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to any non-clock address (08h-13h).
TIMEKEEPER and Alarm Registers store data in
BCD. Control, 32kHz, and Square Wave Registers
store data in Binary Format.
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