M41T80 ,SERIAL ACCESS RTC WITH ALARMSElectrical Characteristics (Table 6.) . . . . 6OPERATION . . . . . . 72-Wire Bus Charac ..
M41T80M6 ,Serial Access RTC with AlarmsLogic DiagramV Table 1. Signal NamesCCXI Oscillator InputXO Oscillator OutputXIIRQ/OUT/ Interrupt / ..
M41T80M6E ,Serial Access RTC with AlarmsLogic Diagram . . 1Figure 2. Package . . . . . . . 1Table 1. Signal Names . . 1 ..
M41T80M6F ,Serial Access RTC with AlarmsAbsolute Maximum Ratings . . . . . . . 14DC AND AC PARAMETERS . 152/20M41T80Table 8. Oper ..
M41T80M6F ,Serial Access RTC with AlarmsFEATURES SUMMARY■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE Figure 2. Package■ COUNTERS FOR TENTHS/HUNDRE ..
M41T80M6TR ,Serial Access RTC with AlarmsFEATURES SUMMARY . . . . . 1Figure 1.
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208AKV-70HI , 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
M5M5V208KV-10LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V208KV-12LL-W , 2097152-BIT (262144-WORD BY 8-BIT) CMOS STATIC RAM
M5M5V216ATP-55HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ATP-70HI , 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M41T80
SERIAL ACCESS RTC WITH ALARMS
1/20October 2002
M41T80SERIAL ACCESS RTC WITH ALARMS
FEATURES SUMMARY 2.0 TO 5.5V CLOCK OPERATING VOLTAGE COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY SERIAL INTERFACE SUPPORTS I2 C BUS
(400KHz) PROGRAMMABLE ALARM and INTERRUPT
FUNCTION LOW OPERATING CURRENT OF 200μA OPERATING TEMPERATURE OF –40 TO
85°C
Figure 1. Logic Diagram
Figure 2. 8-pin SOIC Package
Table 1. Signal Names
M41T80
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38-pin SOIC Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
AC Measurement I/O Waveform (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Crystal Electrical Characteristics (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Serial Bus Data Transfer Sequence (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Acknowledgement Sequence (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Bus Timing Requirements Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Slave Address Location (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
READ Mode Sequence (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Alternative READ Mode Sequence (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
WRITE Mode Sequence (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
TIMEKEEPER® Register Map (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Full-time 32kHz Square Wave Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Alarm Interrupt Reset Waveform (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Alarm Repeat Modes (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Square Wave Output Frequency (Table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Preferred Power-on Default. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Preferred Power-on Default Values (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3/20
M41T80
SUMMARY DESCRIPTIONThe M41T80 Serial Access TIMEKEEPER®
SRAM is a low power Serial RTC with a built-in
32.768 KHz oscillator (external crystal controlled).
Eight registers (see Table 8, page 13) are used for
the clock/calendar function and are configured in
binary coded decimal (BCD) format. An additional
12 registers provide status/control of Alarm, 32kHz
output, and Square Wave functions. Addresses
and data are transferred serially via a two line, bi-
directional I2 C interface. The built-in address reg-
ister is incremented automatically after each
WRITE or READ data byte.
Functions available to the user include a time-of-
day clock/calendar, Alarm interrupts, 32kHz out-
put, and programmable Square Wave output. The
eight clock address locations contain the century,
year, month, date, day, hour, minute, second and
tenths/hundredths of a second in 24 hour BCD for-
mat. Corrections for 28, 29 (leap year - valid until
year 2100), 30 and 31 day months are made auto-
matically.
The M41T80 is supplied in an 8-pin SOIC.
Figure 3. 8-pin SOIC ConnectionsNote:1. Open drain output.
Figure 4. Block DiagramNote:1. Open Drain output
M41T80
MAXIMUM RATINGStressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum RatingsNote:1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
5/20
M41T80
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement ConditionsNote: Output Hi-Z is defined as the point where data is no longer driven.
Figure 5. AC Measurement I/O Waveform
Table 4. CapacitanceNote:1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. At 25°C, f = 1MHz. Outputs deselected.
M41T80
Table 5. DC CharacteristicsNote:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). At 25°C. For IRQ/FT/OUT, RST, and 32kHz pins (Open Drain)
Table 6. Crystal Electrical CharacteristicsNote:1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork
Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be con-
tacted at
[email protected] or http://www.kdsj.co.jp for further information on this crystal type. Load capacitors are integrated within the M41T80. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
7/20
M41T80
OPERATIONThe M41T80 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 20 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. 32kE Bit
11 - 16. Alarm Registers
17 - 19. Reserved
20 - Square Wave Register
2-Wire Bus CharacteristicsThe bus is intended for communication between
different IC’s. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus
is not busy. During data transfer, the data line must remain
stable whenever the clock line is High. Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T80
Figure 6. Serial Bus Data Transfer Sequence
Figure 7. Acknowledgement Sequence
9/20
M41T80
Figure 8. Bus Timing Requirements Sequence
Table 7. AC CharacteristicsNote:1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
M41T80
READ ModeIn this mode the master reads the M41T80 slave
after setting the slave address (see Figure 10,
page 10). Following the WRITE Mode Control Bit
(R/W=0) and the Acknowledge Bit, the word ad-
dress 'An' is written to the on-chip address pointer.
Next the START condition and slave address are
repeated followed by the READ Mode Control Bit
(R/W=1). At this point the master transmitter be-
comes the master receiver. The data byte which
was addressed will be transmitted and the master
receiver will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Clock. The
M41T80 slave transmitter will now place the data
byte at address An+1 on the bus, the master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-13h).
Note: This is true both in READ Mode and WRITEMode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T80 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 11, page 11).
Figure 9. Slave Address Location
Figure 10. READ Mode Sequence
