M40Z300-M40Z300W Fast Delivery |IC PHOENIX CO.,LIMITED

M40Z300 ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMAbsolute Maximum Ratings(Table2.) .... ...... ....... ...... ....... ...... ...... .....6DC AND AC ..
M40Z300AV ,3V NVRAM Supervisor for Up to 8 LPSRAMsAbsolute Maximum Ratings 9DC AND AC PARAMETERS . 10Table 4. DC and AC Measurement Condit ..
M40Z300AVMQ6F ,3V NVRAM Supervisor for Up to 8 LPSRAMsFEATURES SUMMARY■ CONVERTS LOW POWER SRAM INTO Figure 1. 16-pin SOIC PackageNVRAMs■ PRECISION POWER ..
M40Z300MH1 ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMM40Z300M40Z300WNVRAM CONTROLLER for up to EIGHT LPSRAM■ CONVERT LOW POWER SRAMs into NVRAMsSNAPHAT ..
M40Z300W ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMFEATURES SUMMARY■ CONVERTS LOW POWER SRAM INTO Figure 1. 16-pin SOIC PackageNVRAMs■ PRECISION POWER ..
M40Z300WMH1 ,NVRAM CONTROLLER for up to EIGHT LPSRAMLogic DiagramV = 3.0V to 3.6VCCTHS = V 2.8V ≤ V ≤ 3.0VSS PFDV = 2.7V to 3.3VCC(1)V B+CCTHS = V 2.5 ..
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M40Z300-M40Z300W
NVRAM CONTROLLER FOR UP TO EIGHT LPSRAM
1/20May 2002
M40Z300
M40Z300W or 3V NVRAM SUPERVISOR FOR UP TO8 LPSRAMs
FEATURES SUMMARY CONVERTS LOW POWER SRAM INTO
NVRAMs PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION WHEN
VCCIS OUT-OF-TOLERANCE TWO-INPUT DECODER ALLOWS CONTROL
FOR UP TO8 SRAMs (with2 devices activein
parallel) CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES: M40Z300:
VCC =4.5V to5.5V
THS= VSS:4.5V≤ VPFD≤ 4.75V
THS= VOUT:4.2V≤ VPFD≤ 4.5V M40Z300W:
VCC =3.0V to3.6V
THS= VSS:2.8V≤ VPFD≤ 3.0V
VCC =2.7V to3.3V
THS= VOUT:2.5≤ VPFD≤ 2.7V RESET OUTPUT (RST)FOR POWER ON
RESET BATTERY LOW PIN (BL) LESS THAN 12ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device) PACKAGINGINCLUDESA 28-LEAD SOIC and
SNAPHAT® TOP(tobe Ordered Separately),A 16-LEAD SOIC SOIC PACKAGE PROVIDES DIRECT
CONNECTION FORA SNAPHAT TOP WHICH
CONTAINS THE BATTERY
M40Z300, M40Z300W
2/20
TABLE OF CONTENTS
DESCRIPTION ...... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....3
Logic Diagram (Figure 3.). ...... ....... ...... ....... ...... ....... ...... ...... .....3
Signal Names (Table1.).. ...... ....... ...... ....... ...... ....... ...... ...... .....3
28-pin SOIC Connections (Figure4.) ..... ...... ....... ...... ....... ...... ...... .....4
M40Z300 16-pin SOIC Connections (Figure5.)... ....... ...... ....... ...... ...... .....4
M40Z300W 16-pin SOIC Connections (Figure 6.).. ....... ...... ....... ...... ...... .....4
Hardware Hookup (Figure 7.) .... ....... ...... ....... ...... ....... ...... ...... .....5
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....6
Absolute Maximum Ratings (Table2.) .... ...... ....... ...... ....... ...... ...... .....6 AND AC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... .....7 and AC Measurement Conditions (Table3.)... ....... ...... ....... ...... ...... .....7 Testing Load Circuit (Figure 8.)....... ...... ....... ...... ....... ...... ...... .....7
Capacitance (Table4.)... ...... ....... ...... ....... ...... ....... ...... ...... .....7 Characteristics (Table5.) .... ....... ...... ....... ...... ....... ...... ...... .....8
OPERATION. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Twoto Four Decode ..... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Truth Table (Table6.) .... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Address-Decode Time (Figure 9.). ....... ...... ....... ...... ....... ...... ...... ....10
Data Retention Lifetime Calculation ...... ...... ....... ...... ....... ...... ...... ....10
Power Down Timing (Figure 10.).. ....... ...... ....... ...... ....... ...... ...... ....11
Power Up Timing (Figure 11.) .... ....... ...... ....... ...... ....... ...... ...... ....11
Power Down/Up Mode AC Characteristics(Table 7.) ...... ...... ....... ...... ...... ....12
Power-on Reset Output... ...... ....... ...... ....... ...... ....... ...... ...... ....12
Battery Low Pin ... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....12
VCC Noise And Negative Going Transients. ...... ....... ...... ....... ...... ...... ....13
Supply Voltage Protection (Figure 12.) .... ...... ....... ...... ....... ...... ...... ....13
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....14
SNAPHAT®Battery Table (Table 9.) ..... ...... ....... ...... ....... ...... ...... ....14
PACKAGE MECHANICAL INFORMATION... ...... ....... ...... ....... ...... ...... ....15
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....19
3/20
M40Z300, M40Z300W
DESCRIPTION
The M40Z300/W NVRAM SUPERVISORisa self-
contained device which convertsa standard low-
power SRAM intoa non-volatile memory.A preci-
sion voltage reference and comparator monitors
the VCC inputforan out-of-tolerance condition.
Whenan invalid VCC condition occurs, the condi-
tioned chip enable outputs (E1CONto E4CON)are
forced inactiveto write-protect the stored datain
the SRAM. Duringa power failure, the SRAMis
switched from the VCC pinto the lithium cell within
the SNAPHAT®to provide the energy requiredfor
data retention. Ona subsequent power-up, the
SRAM remains write protected untila valid power
condition returns.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts for direct connectiontoa sep-
arate SNAPHAT housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housingis keyedto prevent im-
proper insertion. This unique design allows the
SNAPHAT battery packagetobe mounted on top the SOIC package after the completionof the
surface mount process which greatly reduces the
board manufacturing process complexityof either
directly solderingor insertinga battery intoa sol-
dered holder. Providing non-volatility becomesa
“SNAP.” The 16-pin SOIC provides battery pinsfor external user-supplied battery.
Insertionof the SNAPHAT housing after reflow
prevents potential battery damage dueto the high
temperatures required for device surface-mount-
ing. The SNAPHAT housingis also keyedto pre-
vent reverse insertion.
The 28-pin SOIC and battery packages are
shipped separatelyin plastic anti-static tubesorin
Tape& Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
beris “M4ZXX-BR00SH” (see Table9, page 14).
Caution: Do not place the SNAPHAT battery top conductive foam,as this will drain the lithium
button-cell battery.
Table1. Signal Names
Note:For M40Z300W,B– mustbe connectedtothe negative bat-
tery terminal only (nottoPin8, VSS).
M40Z300, M40Z300W
4/20
Figure4. 28-pin SOIC Connections Figure5. M40Z300 16-pin SOIC Connections
Figure6. M40Z300W 16-pin SOIC Connections
Note:For M40Z300W,B– mustbe connectedtothe negative bat-
tery terminal only (nottoPin8, VSS).
5/20
M40Z300, M40Z300W
Figure7. Hardware Hookup
Note:1.Ifthe second chip enablepin (E2)is unused,it shouldbetiedto VOUT.
M40Z300, M40Z300W
6/20
MAXIMUM RATING
Stressing the deviceabove therating listedinthe
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operationof the deviceat
theseor any other conditions above those indicat-in the Operating sectionsof this specificationis
not implied. Exposureto Absolute Maximum Rat-
ing conditionsfor extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table2. Absolute Maximum Ratings
Note:1. Reflowat peak temperatureof 215°Cto 225°Cfor<60 seconds (total thermal budgetnotto exceed 180°Cfor between90to120
seconds).
CAUTION: Negative undershoots below –0.3Varenot allowedonanypin whileinthe Battery Back-up mode.
CAUTION:Do NOT wave solder SOICto avoid damaging SNAPHAT sockets.
7/20
M40Z300, M40Z300W AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristicsof the device. The parametersin
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listedin the relevant tables. De-
signers should check that the operating conditions their projects match the measurement condi-
tions when using the quoted parameters.
Table3. DC and AC Measurement Conditions
Note: Output HighZis definedasthe point where dataisno longer driven.
Table4. Capacitance
Note:1. Sampled only,not 100% tested.At 25°C,f= 1MHz. Outputs deselected.
M40Z300, M40Z300W
8/20
Table5. DC Characteristics
Note:1. Validfor Ambient Operating Temperature:TA=0to 70°Cor –40to 85°C; VCC=2.7to 3.6Vor4.5to 5.5V(except where noted). Outputs deselected. For RST &BL pins (Open Drain). Chip Enable outputs (E1CON -E4CON)can only sustain CMOS leakage currentsinthe battery back-up mode.
Higher leakage currentswill reduce batterylife. Measured with VOUTand E1CON -E4CON open.
9/20
M40Z300, M40Z300W
OPERATION
The M40Z300/W,as shownin Figure7, page5,
can control upto four (eight,if placedin parallel)
standard low-power SRAMs. These SRAMs must configuredto have the chip enable input dis-
ableall other input signals. Most slow, low-power
SRAMs are configured like this, however many
fast SRAMs are not. During normal operating con-
ditions, the conditioned chip enable (E1CONto
E4CON) output pins follow the chip enable (E) input
pin with timing shownin Figure9, page10 and Ta-
ble7, page 12. An internal switch connects VCCto
VOUT. This switch hasa voltage dropof less than
0.3V (IOUT1).
When VCC degrades duringa power failure,
E1CONto E4CON are forced inactive independentE.In this situation, the SRAMis unconditionally
write protectedas VCC falls belowan out-of-toler-
ance threshold (VPFD). For the M40Z300 the pow- fail detection value associated with VPFDis
selectedby the Threshold Select (THS) pin andis
shownin Table5, page8. For the M40Z300W, the
THS pin selects both the supply voltage and VPFD
(also shownin Table5, page 8).
Note:In either case, THS pin mustbe connected either VSSor VOUT. chip enable accessisin progress duringa power
fail detection, that memory cycle continuesto com-
pletion before the memoryis write protected.If the
memory cycleis not terminated within time tWPT,
E1CONto E4CON are unconditionally driven high,
write protecting the SRAM.A power failure during WRITE cycle may corrupt dataat the currently
addressed location, but does not jeopardize the
restof the SRAM's contents.At voltages below
VPFD (min), the user can be assured the memory
will be write protected within the Write Protect
Time (tWPT) provided the VCC fall time exceedstF
(see Figure9, page 10). VCC continuesto degrade, the internal switch
disconnects VCC and connects the internal battery VOUT. This occursat the switchover voltage
(VSO). Below the VSO, the battery providesa volt-
age VOHBto the SRAM and can supply current
IOUT2 (see Table5, page8).
When VCC rises above VSO,VOUTis switched
backto the supply voltage. Outputs E1CONto
E4CON are held inactive for tCER (120ms maxi-
mum) after the power supply has reached VPFD,
independentof theE input,to allow for processor
stabilization (see Figure 11, page 11).
Twoto Four Decode
The M40Z300/W includesa2 input (A,B) decoder
which allows the controlof upto4 independent
SRAMs. The Truth Tablefor these inputsis shown Table6.
Table6. Truth Table
M40Z300, M40Z300W
10/20
Figure9. Address-Decode Time
Note: During system design, compliance withthe SRAM timing parameters must comprehendthe propagation delay between E1CON-
E4CON.
Data Retention Lifetime Calculation
Most low power SRAMson the market today can used with the M40Z300/W NVRAM SUPERVI-
SOR. There are, however some criteria which
shouldbe usedin making the final choiceof which
SRAMto use. The SRAM mustbe designedina
way where the chip enable input disablesall other
inputsto the SRAM. This allows inputsto the
M40Z300/W and SRAMsto be “Don't Care” once
VCC falls below VPFD(min). The SRAM should also
guarantee data retention downto VCC =2.0V. The
chip enable access time mustbe sufficientto meet
the system needs with the chip enable propaga-
tion delays included.If the SRAM includesa sec-
ond chip enable pin (E2), this pin shouldbe tiedto
VOUT. data retention lifetimeisa critical parameter for
the system,itis importantto review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specifya
data retention currentat 3.0V. Manufacturers gen-
erally specifya typical condition for room temper-
ature along witha worst case condition (generally elevated temperatures). The system level re-
quirements will determine the choiceof which val-to use.
The data retention current valueof the SRAMs can
thenbe addedto the IBAT valueof the M40Z300/to determine the total current requirements for
data retention. The available battery capacity for
the SNAPHAT®of your choice can thenbe divided this currentto determine the amountof datare-
tention available (see Table9, page 14).
CAUTION: Take careto avoid inadvertent dis-
charge through VOUT and E1CON -E4CON after
battery has been attached.
Fora further more detailed reviewof lifetime calcu-
lations, please see Application Note AN1012.

Partno	Mfg	Dc	Qty	Available	Descript
M40Z300	ST	N/a	50	avai	NVRAM CONTROLLER FOR UP TO EIGHT LPSRAM
M40Z300W	ST	N/a	45	avai	NVRAM CONTROLLER FOR UP TO EIGHT LPSRAM