M40Z300MH1 ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMM40Z300M40Z300WNVRAM CONTROLLER for up to EIGHT LPSRAM■ CONVERT LOW POWER SRAMs into NVRAMsSNAPHAT ..
M40Z300W ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMFEATURES SUMMARY■ CONVERTS LOW POWER SRAM INTO Figure 1. 16-pin SOIC PackageNVRAMs■ PRECISION POWER ..
M40Z300WMH1 ,NVRAM CONTROLLER for up to EIGHT LPSRAMLogic DiagramV = 3.0V to 3.6VCCTHS = V 2.8V ≤ V ≤ 3.0VSS PFDV = 2.7V to 3.3VCC(1)V B+CCTHS = V 2.5 ..
M40Z300WMH1 ,NVRAM CONTROLLER for up to EIGHT LPSRAMAbsolute Maximum Ratings Symbol Parameter Value UnitT Ambient Operating Temperature 0 to 70 °CAStor ..
M40Z300WMH6 ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMFEATURES SUMMARY■ CONVERTS LOW POWER SRAM INTO Figure 1. 16-pin SOIC PackageNVRAMs■ PRECISION POWER ..
M40Z300WMH6TR ,NVRAM CONTROLLER FOR UP TO EIGHT LPSRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 4. DC and AC Meas ..
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M40Z300MH1-M40Z300WMH1
NVRAM CONTROLLER for up to EIGHT LPSRAM
1/16March 2000
M40Z300
M40Z300WNVRAM CONTROLLER for up to EIGHT LPSRAM CONVERT LOW POWER SRAMs into
NVRAMs PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION when VCC
is OUT-OF-TOLERANCE TWO INPUT DECODER ALLOWS CONTROL
for up to 8 SRAMs (with 2 devices active in
parallel) CHOICE of SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES: M40Z300:
VCC = 4.5V to 5.5V
THS = VSS 4.5V ≤ VPFD ≤ 4.75V
THS = VOUT 4.2V ≤ VPFD ≤ 4.5V M40Z300W:
VCC = 3.0V to 3.6V
THS = VSS 2.8V ≤ VPFD ≤ 3.0V
VCC = 2.7V to 3.3V
THS = VOUT 2.5 ≤ VPFD ≤ 2.7V RESET OUTPUT (RST) for POWER ON
RESET LESS THAN 12ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device) PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP, or a 16-LEAD SOIC
(to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY BATTERY LOW PIN (BL)
DESCRIPTIONThe M40Z300/W NVRAM Controller is a self-con-
tained device which converts a standard low-pow-
er SRAM into a non-volatile memory. A precision
voltage reference and comparator monitors the
VCC input for an out-of-tolerance condition.
M40Z300, M40Z300WWhen an invalid VCC condition occurs, the condi-
tioned chip enable outputs (E1CON to E4CON ) are
forced inactive to write-protect the stored data in
the SRAM. During a power failure, the SRAM is
switched from the VCC pin to the lithium cell within
the SNAPHAT to provide the energy required for
data retention. On a subsequent power-up, the
SRAM remains write protected until a valid power
condition returns.
The 28 pin, 330 mil SOIC provides sockets with
gold plated contacts for direct connection to a sep-
arate SNAPHAT housing containing the battery.
The SNAPHAT housing has gold plated pins
which mate with the sockets, ensuring reliable
connection. The housing is keyed to prevent im-
proper insertion. This unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process which greatly reduces the
board manufacturing process complexity of either
directly soldering or inserting a battery into a sol-
dered holder. Providing non-volatility becomes a
"SNAP".
The 16 pin SOIC provides battery pins for an ex-
ternal user supplied battery.
Table 1. Signal Names
3/16
M40Z300, M40Z300W
Table 2. Absolute Maximum Ratings (1)Note:1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
OPERATIONThe M40Z300/W, as shown in Figure 4, can con-
trol up to four (eight, if placed in parallel) standard
low-power SRAMs. These SRAMs must be config-
ured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are
configured like this, however many fast SRAMs
are not. During normal operating conditions, the
conditioned chip enable (E1CON to E4CON ) output
pins follow the chip enable (E) input pin with timing
shown in Table 7. An internal switch connects VCC
to VOUT.
This switch has a voltage drop of less than 0.3V
(IOUT1).
When VCC degrades during a power failure,
E1CON to E4CON are forced inactive independent
of E. In this situation, the SRAM is unconditionally
write protected as VCC falls below an out-of-toler-
ance threshold (VPFD). For the M40Z300 the pow-
er fail detection value associated with VPFD is
selected by the Threshold Select (THS) pin and is
shown in Table 6A. For the M40Z300W, the THS
pin selects both the supply voltage and VPFD as
shown in Table 6B.
Note: In either case, THS pin must be connectedto either VSS or VOUT.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time tWPT,
E1CON to E4CON are unconditionally driven high,
write protecting the SRAM. A power failure during
a write cycle may corrupt data at the currently ad-
dressed location, but does not jeopardize the rest
of the SRAM’s contents. At voltages below VPFD
(min), the user can be assured the memory will be
write protected within the Write Protect Time
(tWPT) provided the VCC fall time exceeds tF (See
Table 7).
As VCC continues to degrade, the internal switch
disconnects VCC and connects the internal battery
to VOUT. This occurs at the switchover voltage
(VSO). Below the VSO, the battery provides a volt-
age VOHB to the SRAM and can supply current
IOUT2 (see Table 6A/6B).
When VCC rises above VSO, VOUT is switched
back to the supply voltage. Outputs E1CON to
E4CON are held inactive for tCER (120ms maxi-
mum) after the power supply has reached VPFD,
independent of the E input, to allow for processor
stabilization (see Figure 6).
M40Z300, M40Z300W
DATA RETENTION LIFETIME CALCULATION Most low power SRAMs on the market today can
be used with the M40Z300/W NVRAM Controller.
There are, however some criteria which should be
used in making the final choice of which SRAM to
use. The SRAM must be designed in a way where
the chip enable input disables all other inputs to
the SRAM. This allows inputs to the M40Z300/W
and SRAMs to be Don’t Care once VCC falls below
VPFD (min). The SRAM should also guarantee
data retention down to VCC = 2.0V. The chip en-
able access time must be sufficient to meet the
system needs with the chip enable propagation
delays included. If the SRAM includes a second
Chip Enable pin (E2), this pin should be tied to
VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use. The data retention current value of the
SRAMs can then be added to the ICCDR value of
the M40Z300/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the SNAPHAT of your choice can
then be divided by this current to determine the
amount of data retention available (see Table 8).
CAUTION: Take care to avoid inadvertent dis-
charge through VOUT and E1CON-E4CON after bat-
tery has been attached.
For a further more detailed review of lifetime cal-
culations, please see Application Note AN1012.
Table 3. Truth Table
Table 4. AC Measurement Conditions
5/16
M40Z300, M40Z300W
POWER-ON RESET OUTPUTAll microprocessors have a reset input which forc-
es them to a known state when starting. The
M40Z300/W has a reset output (RST) pin which is
guaranteed to be low within tWPT of VPFD (See Ta-
ble 7). This signal is an open drain configuration.
An appropriate pull-up resistor should be chosen
to control the rise time. This signal will be valid for
all voltage conditions, even when VCC equals VSS.
Once VCC exceeds the power failure detect volt-
age VPFD, an internal timer keeps RST low for
tREC to allow the power supply to stabilize.
TWO TO FOUR DECODEThe M40Z300/W includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in Table 3.
M40Z300, M40Z300W
Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Note:1. Sampled only, not 100% tested. Outputs deselected.
Table 6A. DC Characteristics for M40Z300(TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Note:1. Outputs deselected. For RST & BL pins (Open Drain). Chip Enable outputs (E1CON - E4CON) can only sustain CMOS leakage currents in the battery back-up mode.
Higher leakage currents will reduce battery life. Measured with VOUT and E1CON - E4CON open.
7/16
M40Z300, M40Z300W
Table 6B. DC Characteristics for M40Z300W(TA = 0 to 70°C; VCC = 3V to 3.6V or 2.7V to 3.3V)
Note:1. Outputs deselected. For RST & BL pins (Open Drain). Chip Enable outputs (E1CON - E4CON) can only sustain CMOS leakage currents in the battery back-up mode.
Higher leakage currents will reduce battery life. Measured with VOUT and E1CON - E4CON open.
M40Z300, M40Z300W
Table 7. Power Down/Up AC Characteristics (TA = 0 to 70°C)
Note:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 μs after
VCC passes VPFD (min).. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
BATTERY LOW PINThe M40Z300/W automatically performs battery
voltage monitoring upon power-up, and at factory-
programmed time intervals of at least 24 hours.
The Battery Low (BL) pin will be asserted if the
battery voltage is found to be less than approxi-
mately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subse-
quent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. SNAPHAT top should
be replaced with valid VCC applied to the device.
The M40Z300/W only monitors the battery when a
nominal VCC is applied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique. The BL pin is an open drain output and
an appropriate pull-up resistor to VCC should be
chosen to control the rise time.
