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M34D64-WMN6-M34D64WMN6T-M34D64-WMN6T
64 KBIT SERIAL I²C BUS EEPROM WITH HARDWARE WRITE CONTROL ON TOP QUARTER OF MEMORY
1/21April 2003
M34D64
64 Kbit Serial I²C Bus EEPROM
With Hardware Write Control on Top Quarter of Memory
FEATURES SUMMARYTwo Wire I2C Serial Interface
Supports 400kHz ProtocolSingle Supply Voltage:2.5V to 5.5V for M34D64-W1.8V to 5.5V for M34D64-RHardware Write Control of the top quarter of
memoryBYTE and PAGE WRITE (up to 32 Bytes)RANDOM and SEQUENTIAL READ ModesSelf-Timed Programming CycleAutomatic Address IncrementingEnhanced ESD/Latch-Up BehaviorMore than 1M Erase/Write CyclesMore than 40 Year Data Retention
Figure 1. Packages
M34D64
SUMMARY DESCRIPTION
These I2C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 8192 x8.
Figure 2. Logic Diagram
These devices are compatible with the I2C
memory protocol. This is a two wire serial interface
that uses a bi-directional data bus and serial clock.
The devices carry a built-in 4-bit Device Type
Identifier code (1010) in accordance with the I2C
bus definition.
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are
initiated by a Start condition, generated by the bus
master. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2),
terminated by an acknowledge bit.
When writing data to the memory, the device
inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 1. Signal Names
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until VCC has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when VCC drops from the operating
voltage, below the POR threshold value, all
operations are disabled and the device will not
respond to any command. A stable and valid VCC
must be applied before applying any logic signal.
Figure 3. SO and TSSOP Connections
Note:1.See page 17 (onwards) for package dimensions, and how
to identify pin-1.
3/21
M34D64
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con-
nected from Serial Clock (SCL) to VCC. (Figure 5
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to VCC. (Fig-
ure 5 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to VCC or VSS, to establish the
Device Select Code.
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the top quarter of the memory (as
shown in Figure 4) from inadvertent erase or write.
The Write Control signal is used to enable
(WC=VIL) or disable (WC=VIH) write instructions to
the top quarter of the memory area. When uncon-
nected, the WC input is internally read as VIL, and
write operations are allowed.
Figure 4. Memory Map showing Write Control
Area
M34D64
Figure 6. I2C Bus Protocol
Table 2. Device Select Code
Note:1.The most significant bit, b7, is sent first.E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3. Most Significant ByteTable 4. Least Significant Byte
5/21
M34D64
DEVICE OPERATION
The device supports the I2C protocol. This is
summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter,
and any device that reads the data to be a
receiver. The device that controls the data transfer
is known as the bus master, and the other as the
slave device. A data transfer can only be initiated
by the bus master, which will also provide the
serial clock for synchronization. The M34D64
device is always a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and
driven High. A Stop condition terminates
communication between the device and the bus
master. A Read command that is followed by
NoAck can be followed by a Stop condition to force
the device into the Stand-by mode. A Stop
condition at the end of a Write command triggers
the internal EEPROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a
successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases
Serial Data (SDA) after sending eight bits of data.
During the 9th clock pulse period, the receiver pulls
Serial Data (SDA) Low to acknowledge the receipt
of the eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is
driven Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I2C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received on
Serial Data (SDA), the device only responds if the
Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Table 5. Operating Modes
Note:1.X = VIH or VIL.
M34D64
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
7, and waits for two address bytes. The device re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte(s).
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the contents
of the top quarter of the memory.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 3) is sent first, followed by the Least Significant
Byte (Table 4). Bits b15 to b0 form the address of
the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected (top quarter
of the memory), by Write Control (WC) being driv-
en High, the location is not modified. The bus mas-
ter terminates the transfer by generating a Stop
condition, as shown in Figure 7.
Page Write
The Page Write mode allows up to 32 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits
(b12-b5) are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. This should be avoided, as
7/21
M34D64
data starts to become overwritten in an implemen-
tation dependent way.
The bus master sends from 1 to 32 bytes of data.
If Write Control (WC) is High, the contents of the
addressed top quarter of the memory location are
not modified. After each byte is transferred, the in-
ternal byte address counter (the 5 least significant
address bits only) is incremented. The transfer is
terminated by the bus master generating a Stop
condition.
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device
disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory
cells. The maximum Write time (tw) is shown in
Tables 13 and 14, but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 8, is:Initial condition: a Write cycle is in progress.Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
M34D64
Figure 9. Read Mode Sequences
Note:1.The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
Random Address Read
A dummy Write is performed to load the address
into the address counter (as shown in Figure 9) but
without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats
the Device Select Code, with the RW bit set to 1.
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates
the transfer with a Stop condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device
Select Code with the RW bit set to 1. The device
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master
terminates the transfer with a Stop condition, as
shown in Figure 9, without acknowledging the
byte.
9/21
M34D64
Sequential Read
This operation can be used after a Current
Address Read or a Random Address Read. The
bus master does acknowledge the data byte
output, and sends additional clock pulses so that
the device continues to output the next byte in
sequence. To terminate the stream of bytes, the
bus master must not acknowledge the last byte,
and must generate a Stop condition, as shown in
Figure 9.
The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
After the last memory address, the address
counter ‘rolls-over’, and the device continues to
output data from memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during theth bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device
terminates the data transfer and switches to its
Stand-by mode.
M34D64
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 6. Absolute Maximum Ratings
Note:1.IPC/JEDEC J-STD-020AJEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)
11/21
M34D64
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 7. Operating Conditions (M34D64-W)
Table 8. Operating Conditions (M34D64-R)

Partno	Mfg	Dc	Qty	Available	Descript
M34D64-WMN6 \|M34D64WMN6	ST	N/a	1820	avai	64 KBIT SERIAL I²C BUS EEPROM WITH HARDWARE WRITE CONTROL ON TOP QUARTER OF MEMORY
M34D64WMN6T	STM	N/a	869	avai	64 KBIT SERIAL I²C BUS EEPROM WITH HARDWARE WRITE CONTROL ON TOP QUARTER OF MEMORY
M34D64-WMN6T \|M34D64WMN6T	STM	N/a	2211	avai	64 KBIT SERIAL I²C BUS EEPROM WITH HARDWARE WRITE CONTROL ON TOP QUARTER OF MEMORY