M29W008T-120N5TR ,8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash MemoryLogic Diagram– Read and Program another Block duringErase SuspendLOW POWER CONSUMPTION– Stand-by an ..
M29W010B ,1 MBIT (128KB X8, UNIFORM BLOCK) LOW VOLTAGE SINGLE SUPPLY FLASH MEMORYLogic Diagram, and Table 1, SignalErase Controller is programming or erasing duringNames, for a bri ..
M29W010B45K1 , 1 Mbit 128Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
M29W010B-45K1 , 1 Mbit 128Kb x8, Uniform Block Low Voltage Single Supply Flash Memory
M29W010B45K1T ,1 Mbit 128Kb x8, Uniform Block Low Voltage Single Supply Flash MemoryLogic Diagram, and Table 1, SignalErase Controller is programming or erasing duringNames, for a bri ..
M29W010B-45K1T ,1 Mbit 128Kb x8, Uniform Block Low Voltage Single Supply Flash MemoryLogic Diagram■ LOW POWER CONSUMPTION– Standby and Automatic Standby■ 100,000 PROGRAM/ERASE CYCLES p ..
M50747-161SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50747-2B4SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50747-2B4SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50940-303SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50941-330SP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M50FLW040A ,4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash MemoryLogic Diagram (A/A Mux Interface) . . 7Table 1. Signal Names (FWH/LPC Interface) . 7Table ..
M29W008T-120N5TR
8 Mbit 1Mb x8, Boot Block Low Voltage Single Supply Flash Memory
Figure 1. Logic Diagram
M29W008T
M29W008B8 Mbit (1Mb x8, Boot Block)
Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W008T and M29W008B are replaced
respectively by the M29W008AT and
M29W008AB2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
FAST PROGRAMMING TIME: 10μs typical
PROGRAM/ERASE CONTROLLER (P/E.C.) Program Byte-by-Byte Status Register bits and Ready/Busy Output
MEMORY BLOCKS Boot Block (T op or Bottom location) Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION Defectivity below 1ppm/year
ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code, M29W008T : D2h Device Code, M29W008B: DCh
DESCRIPTIONThe M29W008 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V VCC supply. For
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed in standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
June 1999 1/30
Figure 2. TSOP Pin Connections
Table 1. Signal Names
Warning: NC = Not Connected.the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
cycles of commands to a Command Interface using
standard microprocessor write timings. The device
is offered in TSOP40 (10 x 20mm) package.
OrganisationThe M29W008 is organised as 1Mb x 8. The mem-
ory uses the address inputs A0-A19 and the Data
Input/Outputs DQ0-DQ7. Memory control is pro-
vided by Chip Enable E, Output Enable G and Write
Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at VID) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
DESCRIPTION (Cont’d)
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents. Minimum Voltage may undershoot to –2V during transition and for less than 20ns. Depends on range.
Table 2. Absolute Maximum Ratings (1)
2/30
M29W008T, M29W008B
Memory BlocksThe devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W008T and M29W008B devices have an array
of 19 blocks, one Boot Block of 16 Kbytes, two
Parameter Blocks of 8 Kbytes, one Main Block of
32 Kbytes and fifteen Main Blocks of 64 Kbytes.
The M29W008T has the Boot Block at the top of
the memory address space and the M29W008B
locates the Boot Block starting at the bottom. The
memory maps are showed in Figure 3. Each block
can be erased separately, any combination of
blocks can be specified for multi-block erase or the
entire chip may be erased. The Erase operations
are managed automatically by the P/E.C. The block
erase operation can be suspended in order to read
from or program to any block not being ersased,
and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus OperationsThe following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro- ection, Unprotection, Protection Verify,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables 4 and 5.
Command InterfaceInstructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signature
or Block Protection Status), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations. The Status Register Data Polling, Tog-
gle, Error bits and the RB output may be read at
any time, during programming or erase, to monitor
the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection, the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Program instruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data from
another block or to program data in another block,
and then resumed.
When power is first applied or if Vcc falls below
VLKO, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONSSee Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs forthe memory array are latched during a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. When A9 is raised to VID, either a Read
Electronic Signature Manufacturer or Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A12 and A15.
Data Input/Outputs (DQ0-DQ7). The input is datato be programmed in the memory array or a com-
mand to be written to the C.I. Both are latched on
the rising edge of Chip Enable E or Write Enable
W. The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the T oggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputs are disabled and when RP is at a Low level.
Chip Enable (E). The Chip Enable input activatesthe memory control logic, input buffers, decoders
and sense amplifiers. E High deselects the memory
and reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to VID during the Block Unprotection opera-
tion.
3/30
M29W008T , M29W008B
Figure 3A. Top Boot Block Memory Map and Block Address Table4/30
M29W008T, M29W008B
Figure 3B. Bottom Boot Block Memory Map and Block Address Table5/30
M29W008T , M29W008B
Table 3A. M29W008T Block Address Table
Output Enable (G). The Output Enable gates theoutputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to VID level during
Block Protection and Unprotection operations.
Write Enable (W). This input controls writing to theCommand Register and Address and Data latches.
Ready/Busy Output (RB). Ready/Busy is anopen-drain output and gives the internal state of the
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructions except the Erase Suspend instruction.
When RB is High, the device is ready for any Read,
Program or Erase operation. The RB will also be
High when the memory is put in Erase Suspend or
Standby modes.
Reset/Block Temporary Unprotect Input (RP).The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling RP to
VIL for at least tPLPX. When the reset pulse is given,
if the memory is in Read or Standby modes, it will
be available for new operations in tPHEL after the
rising edge of RP.
6/30
M29W008T, M29W008B
Table 3B. M29W008B Block Address TableIf the memory is in Erase, Erase Suspend or Pro-
gram modes the reset will take tPLYH during which
the RB signal will be held at VIL. The end of the
memory reset will be indicated by the rising edge
of RB. A hardware reset during an Erase or Pro-
gram operation will corrupt the data being pro-
grammed or the sector(s) being erased. See Table
14 and Figure 9.
Temporary block unprotection is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RP from VIH to VID must slower than tPHPHH.
(See Table 15 and Figure 9). When RP is returned
from VID to VIH all blocks temporarily unprotected
will be again protected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltagemeasurements.
7/30
M29W008T , M29W008B
DEVICE OPERATIONSSee Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Write. Write operations are used to give InstructionCommands to the memory or to latch input data to
be programmed. A write operation is initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whichever occurs last.
Commands and Input Data are latched on the rising
edge of W or E whichever occurs first.
Output Disable. The data outputs are high imped-ance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Automatic Standby. After 150ns of bus inactivityand when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to the CMOS
standby value, while outputs still drive the bus.
Electronic Signature. Two codes identifying themanufacturer and the device can be read from the
memory. The manufacturer’s code for STMi-
croelectronics is 20h, the device code is D2h for the
M29W008T (Top Boot ) an d DCh for the
M29W008B (Bottom Boot). These codes allow pro-
gramming equipment or applications to automat-
ically match their interface to the characteristics of
the M29W008. The Electronic Signature is output
by a Read operation when the voltage applied to
A9 is at VID and address inputs A1 is Low. The
manufacturer code is output when the Address
input A0 is Low and the device code when this input
is High. Other Address inputs are ignored. The
Electronic Signature can also be read, without rais-
ing A9 to VID, by giving the memory the Instruction
AS.
Block Protection. Each block can be separatelyprotected against Program or Erase on program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
erase operations. This mode is activated when both
A9 and G are raised to VID and an address in the
block is applied on A13-A19. Block protection is
initiated on the edge of W falling to VIL. Then after
a delay of 100μs, the edge of W rising to VIH ends
the protection operations. Block protection verify is
achieved by bringing G, E, A0 and A6 to VIL and A1
to VIH, while W is at VIH and A9 at VID. Under these
conditions, reading the data output will yield 01h if
the block defined by the inputs on A13-A19 is
protected. Any attempt to program or erase a pro-
tected block will be ignored by the device.
Block Temporary Unprotection. Any previouslyprotected block can be temporarily unprotected in
order to change stored data. The temporary unpro-
tection mode is activated by bringing RP to VID.
During the temporary unprotection mode the pre-
viously protected blocks are unprotected. A block
can be selected and data can be modified by
executing the Erase or Program instruction with the
RP signal held at VID. When RP is returned to VIH,
all the previously protected blocks are again pro-
tected.
Block Unprotection. All protected blocks can beunprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G and E are at
VID and A12, A15 at VIH. Unprotection is initiated
by the edge of W falling to VIL. After a delay of 10ms,
the unprotection operation will end. Unprotection
verify is achieved by bringing G and E to VIL while
A0 is at VIL, A6 and A1 are at VIH and A9 remains
at VID. In these conditions, reading the output data
will yield 00h if the block defined by the inputs
A13-A19 has been succesfully unprotected. Each
block must be separately verified by giving its ad-
dress in order to ensure that it has been unpro-
tected.
8/30
M29W008T, M29W008B
Notes:1. X = VIL or VIH Block Address must be given on A13-A19 bits. See Table 6. Operation performed on programming equipment.
Table 4. User Bus Operations (1)
Table 5. Read Electronic Signature (following AS instruction or with A9 = VID)
Table 6. Read Block Protection with AS Instruction9/30
M29W008T , M29W008B
INSTRUCTIONS AND COMMANDSThe Command Interface latches commands writ-
ten to the memory. Instructions are made up from
one or more commands to perform Read Memory
Array, Read Electronic Signature, Read Block Pro-
tection, Program, Block Erase, Chip Erase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structions require from 1 to 6 cycles, the first or first
three of which are always write operations used to
initiate the instruction. They are followed by either
further write cycles to confirm the first command or
execute the command immediately. Command se-
quencing must be followed exactly. Any invalid
combination of commands will reset the device to
Read Array. The increased number of cycles has
been chosen to assure maximum data security.
Instructions are initialised by two initial Coded cy-
cles which unlock the Command Interface. In addi-
tion, for Erase, instruction confirmation is again
preceded by the two Coded cycles.
Status Register BitsP/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase com-
mand execution will automatically output these five
Status Register bits. The P/E.C. automatically sets
bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits
(DQ0, DQ1 and DQ4) are reserved for future use
and should be masked. See Tables 9 and 10.
Data Polling Bit (DQ7). When Programming op-erations are in progress, this bit outputs the com-
plement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be per-
formed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to ’0’ for about 100μs, and then return to the
previous addressed memory data value. See Fig-
ure 11 for the Data Polling flowchart and Figure 10
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from ’0’ to
’1’ at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an ad-
dress within a block being erased must be pro-
vided. For a Read Operation in Erase Suspend
mode, DQ7 will output ’1’ if the read is attempted
on a block being erased and the data value on other
blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behaviour as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6). When Programming or Erasingoperations are in progress, successive attempts to
read DQ6 will output complementary data. DQ6 will
toggle following toggling of either G, or E when G
is low. The operation is completed when two suc-
cessive reads yield the same output data. The next
read will output the bit last programmed or a ’1’ after
erasing. The toggle bit DQ6 is valid only during
P/E.C. operations, that is after the fourth W pulse
for programming or after the sixth W pulse for
Erase. If the blocks selected for erasure are pro-
tected, DQ6 will toggle for about 100μs and then
return back to Read. DQ6 will be set to ’1’ if a Read
operation is attempted on an Erase Suspend block.
When erase is suspended DQ6 will toggle during
programming operations in a block different to the
block in Erase Suspend. Either E or G toggling will
cause DQ6 to toggle. See Figure 12 for Toggle Bit
flowchart and Figure 13 for Toggle Bit waveforms.
Table 7. Commands10/30
M29W008T, M29W008B
Notes:1. Commands not interpreted in this table will default to read array mode. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode
before starting any new operation. (See Table 14 and Figure 9). X = Don’t Care. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after
the command cycles. Signature Address bits A0, A1 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1 at VIL will output
Device code. Block Protection Address: A0 at VIL, A1 at VIH and A13-A19 within the Block will output the Block Protection status. For Coded cycles address inputs A15-A19 are don’t care. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status
can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered,
read Data Polling or Toggle bit until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
Table 8. Instructions (1)11/30
M29W008T , M29W008B
Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Table 9. Status Register Bits12/30
M29W008T, M29W008B
Toggle Bit (DQ2). This toggle bit, together withDQ6, can be used to determine the device status
during the Erase operations. It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to ’1’ during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to ’1’
during program operation and when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to ’1’, DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block erase
or program, the block in which the error occured or
to which the programmed data belongs, must be
discarded. The DQ5 failure condition will also ap-
pear if a user tries to program a ’1’ to a location that
is previously programmed to ’0’. Other Blocks may
still be used. The error bit resets after a Read/Reset
(RD) instruction. In case of success of Program or
Erase, the error bit will be set to ’0’ .
Erase Timer Bit (DQ3). This bit is set to ’0’ by theP/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50μs to 90μs, DQ3 returns
to ’1’.
Coded CyclesThe two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address 5555h during the
first cycle. During the second cycle the Coded
cycles consist of writing the data 55h at address
2AAAh. A0 to A15 are valid, other address lines are
’don’t care’. The Coded cycles happen on first and
second cycles of the command write or on the
fourth and fifth cycles.
InstructionsSee Table 8.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by the
two Coded cycles. Subsequent read operations will
read the memory array addressed and output the
data read. A wait state of 10μs is necessary after
Read/Reset prior to any valid read if the memory
was in an Erase mode when the RD instruction is
given.
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 555h for
command set-up. A subsequent read will output the
manufacturer code and the device code or the
block protection status depending on the levels of
A0 and A1. The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code, EAh for Top Boot, EBh for Bottom
Boot is output when A0 is High with A1 Low.
The AS instruction also allows access to the block
protection status. After giving the AS instruction, A0
and A6 are set to VIL with A1 at VIH, while A13-A19
define the address of the block to be verified. A read
in these conditions will output a 01h if the block is
protected and a 00h if the block is not protected.
Program (PG) Instruction. This instruction usesfour write cycles. The Program command A0h is
written to address 5555h on the third cycle after two
Coded cycles. A fourth write operation latches the
Address on the falling edge of W or E and the Data
to be written on the rising edge and starts the
P/E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing ’0’ in place of
’1’. Status bits DQ6 and DQ7 determine if program-
ming is on-going and DQ5 allows verification of any
possible error. Programming at an address not in
blocks being erased is also possible during erase
suspend. In this case, DQ2 will toggle at the ad-
dress being programmed.
Note:1. Toggle if the address is within a block being erased.
’1’ if the address is within a block not being erased.
Table 10. Polling and Toggle Bits13/30
M29W008T , M29W008B
Note:1. Sampled only, not 100% tested.
Table 12. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Figure 4. AC Testing Input Output Waveform
Figure 5. AC Testing Load Circuit
Table 11. AC Measurement Conditions
Note:1. Sampled only, not 100% tested.
Table 13. DC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V)
14/30
M29W008T, M29W008B
Notes:1. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. To be considered only if the Reset pulse is given while the memory is in Erase, Erase Suspend or Program mode.
Table 14A. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
15/30
M29W008T , M29W008B
