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M28W800CB90N6STN/a1331avai8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORY
M28W800CT70N6STN/a4032avai8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORY
M28W800CT70ZB6TSTN/a95000avai8 Mbit 512Kb x16, Boot Block 3V Supply Flash Memory
M28W800CT90N6ST ?N/a481avai8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORY
M28W800CT-90N6 |M28W800CT90N6STN/a285avai8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORY


M28W800CT70ZB6T ,8 Mbit 512Kb x16, Boot Block 3V Supply Flash Memoryfeatures an asymmetrical blocked ar- DD DDQ PPchitecture. The M28W800C has an array of 23blocks: 8 ..
M28W800CT90N6 ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYLogic Diagram1.65V. An optional 12V V power supply is pro-PPvided to speed up customer programming. ..
M28W800CT-90N6 ,8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V Core Power SupplyDD–V = 1.65V ..
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M293B1 ,EPM 32 ELECTRONIC PROGRAM MEMORY FOR 32 STATIONS
M29DW128F ,128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash MemoryFeatures summary■ Supply Voltage –V = 2.7V to 3.6V for Program, Erase and CC Read–V = 1.65V to 3.6 ..
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M50427FP , CD PLAYER DIGITAL SIGNAL PROCESSOR
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M50734SP-10 , 8-BIT CMOS MICROCOMPUTER   
M50734SP-10 , 8-BIT CMOS MICROCOMPUTER   


M28W800CB90N6-M28W800CT70N6-M28W800CT70ZB6T-M28W800CT90N6-M28W800CT-90N6
8 MBIT (512KB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORY
1/49May 2002
M28W800CT
M28W800CB
Mbit (512Kb x16, Boot Block) Supply Flash Memory
FEATURES SUMMARY
SUPPLY VOLTAGE
–VDD= 2.7Vto 3.6V Core Power Supply
–VDDQ= 1.65Vto 3.6Vfor Input/Output
–VPP= 12V for fast Program (optional) ACCESS TIME: 70, 85, 90,100ns PROGRAMMING TIME: 10μs typical Double Word Programming Option COMMON FLASH INTERFACE 64bit Security Code MEMORY BLOCKS Parameter Blocks (Topor Bottom location) Main Blocks BLOCK LOCKING All blocks lockedat Power Up Any combinationof blocks canbe locked
–WPfor Block Lock-Down SECURITY 64bit user Programmable OTP cells 64bit unique device identifier One Parameter Block Permanently Lockable AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLES per
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M28W800CT: 88CCh Bottom Device Code, M28W800CB: 88CDh
M28W800CT, M28W800CB
2/49
TABLE OF CONTENTS
SUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... .....5

Figure 2.LogicDiagram.. ...... ....... ...... ....... ...... ....... ...... ...... .....5
Table1. Signal Names... ...... ....... ...... ....... ...... ....... ...... ...... .....5
Figure3. TSOP Connections..... ....... ...... ....... ...... ....... ...... ...... .....6
Figure4. TFBGA Connections (Top view through package). ...... ....... ...... ...... .....7
Figure 5.Block Addresses. ...... ....... ...... ....... ...... ....... ...... ...... .....8
Figure 6.SecurityBlock and Protection Register Memory Map .... ....... ...... ...... .....8
SIGNAL DESCRIPTIONS .... ...... ....... ...... ....... ...... ....... ...... ...... .....9

Address Inputs (A0-A18).. ...... ....... ...... ....... ...... ....... ...... ...... .....9
Data Input/Output (DQ0-DQ15)... ....... ...... ....... ...... ....... ...... ...... .....9
Chip Enable (E)... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Output Enable (G). ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Write Enable (W).. ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Write Protect (WP). ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
Reset(RP). ...... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
VDD Supply Voltage...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
VDDQ Supply Voltage..... ...... ....... ...... ....... ...... ....... ...... ...... .....9
VPP Program Supply Voltage .... ....... ...... ....... ...... ....... ...... ...... .....9
VSS Ground. ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... .....9
BUS OPERATIONS... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10

Read. .... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Write. .... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Output Disable. ... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Standby.. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Automatic Standby. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Reset. ... ....... ...... ...... ....... ...... ....... ...... ....... ...... ... ... ....10
Read Electronic Signature Command ..... ...... ....... ...... ....... ...... ...... ....11
Table 2.Bus Operations.. ...... ....... ...... ....... ...... ....... ...... ...... ....10
COMMANDINTERFACE .... ...... ....... ...... ....... ...... ....... ...... ...... ....11

Read Memory Array Command... ....... ...... ....... ...... ....... ...... ...... ....11
Read Status Register Command.. ....... ...... ....... ...... ....... ...... ...... ....11
Read Electronic Signature Command ..... ...... ....... ...... ....... ...... ...... ....11
Read CFIQueryCommand...... ....... ...... ....... ...... ....... ...... ...... ....11
Block Erase Command ... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Program Command ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Double Word Program Command. ....... ...... ....... ...... ....... ...... ...... ....12
Clear Status Register Command.. ....... ...... ....... ...... ....... ...... ...... ....12
Program/Erase Suspend Command ...... ...... ....... ...... ....... ...... ...... ....12
Program/Erase Resume Command ...... ...... ....... ...... ....... ...... ...... ....12
Protection Register Program Command ... ...... ....... ...... ....... ...... ...... ....12
Block Lock-Down Command ..... ....... ...... ....... ...... ....... ...... ...... ....13
3/49
M28W800CT, M28W800CB

Table 3.Commands ..... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Table 4.Read ElectronicSignature....... ...... ....... ...... ....... ...... ...... ....14
Table5. Read Block Lock Signature ...... ...... ....... ...... ....... ...... ...... ....15
Table 6.Read Protection Register and Lock Register ..... ...... ....... ...... ...... ....15
Table 7.Program,Erase Times and Program/Erase Endurance Cycles .... ...... ...... ....15
BLOCKLOCKING.... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16

Readinga Block’s Lock Status... ....... ...... ....... ...... ....... ...... ...... ....16
Locked State ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Unlocked State ... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Lock-Down State.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Locking Operations During Erase Suspend ...... ....... ...... ....... ...... ...... ....16
Table 8.Block LockStatus ...... ....... ...... ....... ...... ....... ...... ...... ....17
Table 9.Protection Status. ...... ....... ...... ....... ...... ....... ...... ...... ....17
STATUS REGISTER.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....18

Program/Erase Controller Status (Bit7) ... ...... ....... ...... ....... ...... ...... ....18
Erase Suspend Status (Bit6) .... ....... ...... ....... ...... ....... ...... ...... ....18
Erase Status(Bit5) ...... ...... ....... ...... ....... ...... ....... ...... ...... ....18
Program Status (Bit4) .... ...... ....... ...... ....... ...... ....... ...... ...... ....18
VPP Status (Bit 3).. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....18
Program Suspend Status (Bit2).. ....... ...... ....... ...... ....... ...... ...... ....18
Block Protection Status (Bit 1).... ....... ...... ....... ...... ....... ...... ...... ....19
Reserved (Bit 0)... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....19
Table 10. Status Register Bits.... ....... ...... ....... ...... ....... ...... ...... ....19
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....20

Table 11. Absolute Maximum Ratings ..... ...... ....... ...... ....... ...... ...... ....20 and AC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... ....21
Table 12. Operating and AC Measurement Conditions..... ...... ....... ...... ...... ....21
Figure 7.AC Measurement I/O Waveform. ...... ....... ...... ....... ...... ...... ....21
Figure8. AC Measurement Load Circuit... ...... ....... ...... ....... ...... ...... ....21
Table 13. Capacitance.... ...... ....... ...... ....... ...... ....... ...... ...... ....21
Table 14. DC Characteristics..... ....... ...... ....... ...... ....... ...... ...... ....22
Figure 9.Read Mode AC Waveforms ..... ...... ....... ...... ....... ...... ...... ....23
Table 15. Read AC Characteristics ....... ...... ....... ...... ....... ...... ...... ....23
Figure 10. Write AC Waveforms, Write Enable Controlled.. ...... ....... ...... ...... ....24
Table 16. Write AC Characteristics, Write Enable Controlled ...... ....... ...... ...... ....25
Figure 11. Write AC Waveforms, Chip Enable Controlled... ...... ....... ...... ...... ....26
Table 17. Write AC Characteristics, Chip Enable Controlled ...... ....... ...... ...... ....27
Figure 12. Power-Up and Reset AC Waveforms... ....... ...... ....... ...... ...... ....28
Table 18. Power-Up and ResetACCharacteristics ....... ...... ....... ...... ...... ....28
PACKAGE MECHANICAL... ...... ....... ...... ....... ...... ....... ...... ...... ....29
M28W800CT, M28W800CB
4/49
Figure 13. TSOP48-48 lead Plastic Thin Small Outline,12 x20mm, Package Outline .... ....29
Table 19. TSOP48-48 lead Plastic Thin Small Outline,12x 20mm, Package Mechanical Data.29
Figure 14. TFBGA46 6.39x6.37mm- 8x6 ball array, 0.75mm pitch, Bottom View Package Outline30
Table 20. TFBGA46 6.39x6.37mm- 8x6 ball array, 0.75mm pitch,Package Mechanical Data ...30
Figure 15. TFBGA46 Daisy Chain- Package Connections (Top view through package) .... ....31
Figure 16. TFBGA46 Daisy Chain- PCB Connections proposal (Top view through package) ....31
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....32

Table 21. Ordering Information Scheme ... ...... ....... ...... ....... ...... ...... ....32
Table 22. DaisyChain Ordering Scheme.. ...... ....... ...... ....... ...... ...... ....32
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....33

Table 23. Document Revision History ..... ...... ....... ...... ....... ...... ...... ....33
APPENDIXA. BLOCK ADDRESS TABLES.. ...... ....... ...... ....... ...... ...... ....34

Table 24. Top Boot Block Addresses, M28W800CT ....... ...... ....... ...... ...... ....34
Table 25. Bottom Boot Block Addresses, M28W800CB .... ...... ....... ...... ...... ....34
APPENDIXB. COMMONFLASH INTERFACE (CFI). ....... ...... ....... ...... ...... ....35

Table 26. Query Structure Overview ...... ...... ....... ...... ....... ...... ...... ....35
Table 27. CFI Query Identification String.. ...... ....... ...... ....... ...... ...... ....35
Table 28. CFIQuerySystem Interface Information. ....... ...... ....... ...... ...... ....36
Table 29. Device Geometry Definition ..... ...... ....... ...... ....... ...... ...... ....37
Table 30. Primary Algorithm-Specific Extended Query Table ...... ....... ...... ...... ....38
Table 31. Security Code Area .... ....... ...... ....... ...... ....... ...... ...... ....39
APPENDIXC. FLOWCHARTS AND PSEUDO CODES....... ...... ....... ...... ...... ....40

Figure 17. Program Flowchart and Pseudo Code.. ....... ...... ....... ...... ...... ....40
Figure 18. Double Word Program Flowchart and Pseudo Code .... ....... ...... ...... ....41
Figure 19. Program Suspend& Resume Flowchart and Pseudo Code ..... ...... ...... ....42
Figure 20. Erase Flowchart and Pseudo Code .... ....... ...... ....... ...... ...... ....43
Figure 21. Erase Suspend& Resume Flowchart and Pseudo Code. ....... ...... ...... ....44
Figure 22. Locking Operations Flowchart and Pseudo Code ...... ....... ...... ...... ....45
Figure 23. Protection Register Program Flowchart and Pseudo Code ...... ...... ...... ....46
APPENDIXD. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE ... ....47

Table 32. Write State Machine Current/Next, sheet1of 2... ...... ....... ...... ...... ....47
Table 33. Write State Machine Current/Next, sheet2of 2... ...... ....... ...... ...... ....48
5/49
M28W800CT, M28W800CB
SUMMARY DESCRIPTION

The M28W800Cisa8 Mbit (512Kbitx 16) non-vol-
atileFlash memory that canbeerasedelectrically the block level and programmed in-systemona
Word-by-Word basis. These operations can be
performed usinga single low voltage (2.7to 3.6V)
supply. VDDQ allowsto drive the I/O pin downto
1.65V. An optional 12V VPP power supplyis pro-
videdto speedup customer programming.
The device featuresan asymmetrical blocked ar-
chitecture. The M28W800C has an arrayof 23
blocks:8 Parameter Blocksof4 KWord and 15
Main Blocksof 32 KWord. M28W800CT has the
Parameter Blocksat the topof the memory ad-
dress space while the M28W800CB locates the
Parameter Blocks starting from the bottom. The
memory maps are shownin Figure5, Block Ad-
dresses.
The M28W800C features an instant, individual
block locking scheme that allows any blocktobe
lockedor unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levelsof protection. They canbe locked and
locked-down individually preventing any acciden-
tal programmingor erasure. Thereisan additional
hardware protection against program and erase.
When VPP ≤ VPPLKall blocks are protected against
programor erase. All blocks are lockedat power-
up.
Each block canbe erased separately. Erase can suspendedin orderto perform either reador
programin any other block and then resumed.
Program can be suspendedto read datain any
other block and then resumed. Each block canbe
programmed and erased over 100,000 cycles.
The device includesa 128bit Protection Register
anda Security Blockto increase the protectionof system design. The Protection Registeris divid- into two64bit segments, the first one contains unique device number writtenby ST, while the
second oneis one-time-programmableby the us-
er. The user programmable segment canbe per-
manently protected. The Security Block,
parameter block0, canbe permanently protected the user. Figure6, shows the Security Block
and Protection Register Memory Map.
Program and Erase commands are writtento the
Command Interfaceof the memory. An on-chip
Program/Erase Controller takes careof the tim-
ings necessary for program and erase operations.
The endofa programor erase operation canbe
detected and any error conditions identified. The
command set requiredto control the memoryis
consistent with JEDEC standards.
M28W800CT, M28W800CB
6/49
7/49
M28W800CT, M28W800CB
M28W800CT, M28W800CB
8/49
9/49
M28W800CT, M28W800CB
SIGNAL DESCRIPTIONS

See Figure2 Logic Diagram and Table 1,Signal
Names,fora brief overviewof the signals connect-to this device.
Address Inputs (A0-A18).
The Address Inputs
select the cellsin the memory arrayto access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interfaceof the internal state machine.
Data Input/Output (DQ0-DQ15).
The Data I/O
outputs the data storedat the selected address
duringa Bus Read operationor inputsa command thedatatobeprogrammedduringa WriteBus
operation.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enableis VILand Resetisat VIH the deviceisin active
mode. When Chip Enableisat VIH the memoryis
deselected, the outputs are high impedance and
the power consumptionis reducedto the stand-by
level.
Output Enable (G).
The Output Enable controls
data outputs during the Bus Read operationof the
memory.
WriteEnable(W).
The Write Enable controls the
Bus Write operationof the memory’s Command
Interface. The data and address inputs are latched therisingedgeof ChipEnable,E, orWrite En-
able, W, whichever occurs first.
Write Protect (WP).
Write Protectis an input
that gives an additional hardware protection for
each block. When Write Protectisat VIL, the Lock-
Downis enabled and the protection statusof the
block cannotbe changed. When Write Protectisat
VIH, the Lock-Downis disabled and the block can lockedor unlocked. (referto Table6, Read Pro-
tection Register and Protection Register Lock).
Reset (RP).
The Reset input providesa hard-
ware resetofthe memory. When ResetisatVIL,
the memoryisin reset mode: the outputs are high
impedance and the current consumptionis mini-
mized. After Reset all blocks arein the Locked
state. When Resetisat VIH, the deviceisin normal
operation. Exiting reset mode the device enters
read array mode, buta negative transitionof Chip
Enableora changeof the addressis requiredto
ensure valid data outputs.
VDD Supply Voltage.
VDD provides the power
supplyto the internal coreof the memory device.is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage.
VDDQ provides the
power supplyto the I/O pins and enablesall Out-
putstobe powered independently from VDD.VDDQ
canbetied toVDDor can usea separate supply.
VPP Program Supply Voltage.
VPPis botha
control input anda power supply pin. The two
functions are selected by the voltage range ap-
pliedto the pin. The Supply Voltage VDD and the
Program Supply Voltage VPP canbe appliedin
any order. VPPis keptina low voltage range (0Vto 3.6V)
VPPis seenasa control input.In this casea volt-
age lower than VPPLK givesan absolute protection
against programor erase, while VPP >VPP1 en-
ables these functions (see Table 14, DC Charac-
teristics for the relevant values). VPPis only
sampledat the beginningofa programor erase;a
changeinits value after the operation has started
does not have any effect and programor erase op-
erations continue. VPPisin the range 11.4Vto 12.6Vit actsasa
power supply pin.In this condition VPP must be
stable until the Program/Erase algorithmis com-
pleted (see Table16 and 17).
VSS Ground.
VSSis the reference forall voltage
measurements.
Note: Each deviceina system should have
VDD,VDDQ and VPP decoupled witha 0.1μF ca-
pacitor closeto the pin. See Figure8, AC Mea-
surement Load Circuit. The PCB trace widths
should be sufficientto carry the required VPP
program and erase currents.
M28W800CT, M28W800CB
10/49
BUS OPERATIONS

There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table2, Bus Operations,fora summary.
Typically glitchesof less than 5nson Chip Enable Write Enable are ignoredby the memory anddo
not affect bus operations.
Read.
Read Bus operations are usedto output
the contentsof the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
ablemust beat VILin orderto performa read op-
eration. The Chip Enable input shouldbe usedto
enable the device. Output Enable shouldbe used gate data onto the output. The data read de-
pends on the previous command writtento the
memory (see Command Interface section). See
Figure9, Read Mode AC Waveforms, and Table
15, Read AC Characteristics, for detailsof when
the output becomes valid.
Read modeis the default stateof the device when
exiting Resetor after power-up.
Write.
Bus Write operations write Commandsto
the memoryor latch Input Datatobe programmed. write operationis initiated when Chip Enable
and Write Enable areat VIL with Output Enableat
VIH. Commands, Input Data and Addresses are
latchedon the rising edgeof Write Enableor Chip
Enable, whichever occurs first.
See Figures10 and 11, Write AC Waveforms, and
Tables 16 and 17, Write AC Characteristics, for
detailsof the timing requirements.
Output Disable.
The data outputs are high im-
pedance when the Output Enableisat VIH.
Standby.
Standby disables mostof the internal
circuitry allowinga substantial reductionof the cur-
rent consumption. The memoryisin stand-by
when Chip Enableisat VIH and thedeviceisin
read mode. The power consumptionis reducedto
the stand-by level and the outputs are setto high
impedance, independently from the Output Enable Write Enable inputs.If Chip Enable switchesto
VIH duringa programor erase operation, the de-
vice enters Standby mode when finished.
Automatic Standby.
Automatic Standby pro-
videsa low power consumption state during Read
mode. Followinga read operation, the device en-
ters Automatic Standby after 150nsof bus inactiv-
ity evenif Chip Enableis Low, VIL, and the supply
currentis reducedto IDD1. The data Inputs/Out-
puts will still output dataifa bus Read operationis progress.
Reset.
During Reset mode when Output Enable Low, VIL, the memoryis deselected and the out-
puts are high impedance. The memoryisin Reset
mode when Resetisat VIL. The power consump-
tionis reducedto the Standby level, independently
from the Chip Enable, Output Enableor Write En-
able inputs.If Resetis pulledto VSS duringa Pro-
gramor Erase, this operationis aborted and the
memory contentisno longer valid.
Table2. Bus Operations

Note:X= VILor VIH,VPPH =12V± 5%.
11/49
M28W800CT, M28W800CB
COMMAND INTERFACE

All Bus Write operationsto the memory are inter-
preted by the Command Interface. Commands
consistof oneor more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dlesall timings and verifies the correct execution the Program and Erase commands. The Pro-
gram/Erase Controller providesa Status Register
whose output maybe readat any time during,to
monitor the progressof the operation,or the Pro-
gram/Erase states. See Appendix 21, Table 32,
Write State Machine Current/Next, fora summary the Command Interface.
The Command Interfaceis resetto Read mode
when poweris first applied, when exiting from Re-
setor whenever VDDis lower than VLKO.Com-
mand sequences must be followed exactly. Any
invalid combinationof commands will reset the de-
viceto Read mode. Referto Table3, Commands, conjunction with the text descriptions below.
Read Memory Array Command

TheReadcommand returns the memoryto its
Read mode. One Bus Write cycleis requiredtois-
sue the Read Memory Array command and return
the memoryto Read mode. Subsequent read op-
erations will read the addressed location and out-
put the data. Whena device Reset occurs, the
memory defaultsto Read mode.
Read Status Register Command

The Status Register indicates whena programor
erase operationis complete and the successor
failureof the operation itself. Issuea Read Status
Register commandto read the Status Register’s
contents. Subsequent Bus Read operations read
the Status Registerat any address, until another
commandis issued. See Table 10, Status Register
Bits,for detailson the definitionsof the bits.
The Read Status Register command may beis-
suedat any time, even duringa Program/Erase
operation. Any Read attempt duringa Program/
Erase operation will automatically output the con-
tentof the Status Register.
Read Electronic Signature Command

The Read Electronic Signature command reads
the Manufacturer and Device Codes and the Block
Locking Status,or the Protection Register.
The Read Electronic Signature command consists one write cycle,a subsequent read will output
the Manufacturer Code, the Device Code, the
Block Lock and Lock-Down Status,or the Protec-
tion and Lock Register. See Tables4,5 and6for
the valid address.
Read CFI Query Command

The Read Query Commandis usedto read data
from the Common Flash Interface (CFI) Memory
Area, allowing programming equipmentor appli-
cationsto automatically match their interfaceto
the characteristicsof the device. One Bus Write
cycleis requiredto issue the Read Query Com-
mand. Once the commandis issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See AppendixB,
Common Flash Interface, Tables 26, 27, 28, 29, and31 for detailson the information contained the Common Flash Interface memory area.
Block Erase Command

TheBlock Erase command can beusedtoerase block.It setsall the bits within the selected block ’1’. All previous datain the blockis lost.If the
blockis protected then the Erase operation will
abort, the datain the block will notbe changed and
the Status Register will output the error.
Two Bus Write cycles are requiredto issue the
command. The first bus cycle setsup the Erase command. The second latches the block addressin the
internal state machine and starts the Program/
Erase Controller. the second bus cycleis not Write Erase Confirm
(D0h), Status Register bitsb4 and b5 are set and
the command aborts.
Erase abortsif Reset turnsto VIL.As data integrity
cannotbe guaranteed when the Erase operationis
aborted, the block mustbe erased again.
During Erase operations the memory will accept
the Read Status Register command and the Pro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
givenin Table7, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See AppendixC, Figure 20, Erase Flowchart and
Pseudo Code, fora suggested flowchart for using
the Erase command.
Program Command

The memory array can be programmed word-by-
word. Two bus write cycles are requiredto issue
the Program Command. The first bus cycle setsup the Program
command. The secondlatches the Address and the Datato written and starts the Program/Erase
Controller.
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are givenin Table7, Program, Erase
Times and Program/Erase Endurance Cycles.
Programming abortsif Reset goesto VIL. As data
integrity cannot be guaranteed when the program
operationis aborted, the block containing the
M28W800CT, M28W800CB
12/49
memory location must be erased and repro-
grammed.
See Appendix C, Figure 17, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program Command

This featureis offeredto improve the programming
throughput, writinga pageof two adjacent words parallel.The two words must differ only for the
address A0. Programming should not be attempt- when VPPis notat VPPH. The command canbe
executedif VPPis below VPPH but the resultis not
guaranteed.
Three bus write cycles are necessaryto issue the
Double Word Program command. The first bus cycle setsup the Double Word
Program Command. The second bus cycle latches the Address and
the Dataof the first wordtobe written. The third bus cycle latches the Address and the
Dataof the second wordtobe written and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming abortsif Reset goesto VIL. As data integrity
cannot be guaranteed when the program opera-
tionis aborted, the block containing the memory
location mustbe erased and reprogrammed.
See Appendix C, Figure 18, Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Double Word Program
command.
Clear Status Register Command

The Clear Status Register command canbe used reset bits1,3,4 and5in the Status Registerto
‘0’. One bus write cycleis requiredto issue the
Clear Status Register command.
The bitsin the Status Registerdo not automatical- returnto‘0’ whena new Programor Erase com-
mandis issued. The error bitsin the Status
Register should be cleared before attemptinga
new Programor Erase command.
Program/Erase Suspend Command

The Program/Erase Suspend commandis usedto
pausea Programor Erase operation. One bus
write cycleis requiredto issue the Program/Erase
command and pause the Program/Erase control-
ler.
During Program/Erase Suspend the CommandIn-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron- Signature and Read CFI Query commands. Ad-
ditionally,if the suspend operation was Erase then
the Program, Block Lock, Block Lock-Downor
Protection Program commands will also be ac-
cepted. The block being erased maybe protected issuing the Block Protect, Block Lockor Protec-
tion Program commands. When the Program/
Erase Resume commandis issued the operation
will complete. Only the blocks not being erased
maybe reador programmed correctly.
Duringa Program/Erase Suspend, the device can placedina pseudo-standby mode by taking
Chip Enableto VIH. Program/Eraseis abortedif
Reset turnsto VIL.
See AppendixC, Figure 19, Programor Double
Word Program Suspend& Resume Flowchart and
Pseudo Code, and Figure 21, Erase Suspend&
Resume Flowchart and Pseudo Code for flow-
chartsfor using the Program/Erase Suspend com-
mand.
Program/Erase Resume Command

The Program/Erase Resume command can be
usedto restart the Program/Erase Controller after Program/Erase Suspend operation has paused
it. One Bus Write cycleis requiredto issue the
command. Once the commandis issued subse-
quent Bus Read operations read the Status Reg-
ister.
See AppendixC, Figure 19, Programor Double
Word Program Suspend& Resume Flowchart and
Pseudo Code, and Figure 21, Erase Suspend&
Resume Flowchart and Pseudo Code for flow-
chartsfor using the Program/Erase Resume com-
mand.
Protection Register Program Command

The Protection Register Program commandis
usedto Program the 64 bit user One-Time-Pro-
grammable (OTP) segmentof the Protection Reg-
ister. The segmentis programmed 16 bitsata
time. When shippedall bitsin the segment are set ‘1’. The user can only program the bitsto ‘0’.
Two write cycles are requiredto issue the Protec-
tion Register Program command. The first bus cycle setsup the Protection
Register Program command. The secondlatches the Address and the Datato writtento the Protection Register and starts
the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
The segment canbe protectedby programmingbitof the Protection Lock Register. Bit1of the Pro-
tection Lock Register protectsbit2of the Protec-
tion Lock Register. Programming bit2 of the
Protection Lock Register will resultina permanent
protectionof the Security Block (see Figure6, Se-
curity Block and Protection Register Memory
Map). Attemptingto programa previously protect- Protection Register will resultina Status Reg-
ister error. The protection of the Protection
13/49
M28W800CT, M28W800CB

Register and/or the Security Blockis not revers-
ible.
The Protection Register Program cannot be sus-
pended. See Appendix C, Figure 23, Protection
Register Program Flowchart and Pseudo Code,
for the flowchartfor using the Protection Register
Program command.
Block Lock Command

The Block Lock commandis usedto locka block
and prevent Programor Erase operations from
changing the datainit. All blocks are lockedat
power-upor reset.
Two Bus Write cycles are requiredto issue the
Block Lock command. The first bus cycle setsup the Block Lock
command. The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table.9 shows the protection status after issuing Block Lock command.
The Block Lock bits are volatile, once set they re-
main set untila hardware resetor power-down/
power-up. They are cleared bya Blocks Unlock
command. Referto the section, Block Locking,for detailed explanation.
Block Unlock Command

The Blocks Unlock commandis usedto unlocka
block, allowing the blockto be programmedor
erased. Two Bus Write cycles are requiredtois-
sue the Blocks Unlock command. The first bus cycle setsup the Block Unlock
command. The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Table.9 shows the protection status after issuing Block Unlock command. Referto the section,
Block Locking,fora detailed explanation.
Block Lock-Down Command
locked block cannotbe Programmedor Erased, haveits protection status changed when WPis
low, VIL.When WPis high, VIH, the Lock-Down
functionis disabled and the locked blocks canbe
individually unlocked by the Block Unlock com-
mand.
Two Bus Write cycles are requiredto issue the
Block Lock-Down command. The first bus cycle setsup the Block Lock
command. The second Bus Write cycle latches the block
address.
The lock status can be monitored for each block
using the Read Electronic Signature command.
Locked-Down blocks revertto the locked (and not
locked-down) state when the deviceis reset on
power-down. Table.9 shows the protection status
after issuinga Block Lock-Down command. Refer the section, Block Locking,fora detailed expla-
nation.
M28W800CT, M28W800CB
14/49
Table3. Commands

Note:1.X= Don't Care. The signature addressesare listedin Tables4,5 and6. Addr1 and Addr2 mustbe consecutive Addresses differing onlyforA0.
Table4. Read Electronic Signature

Note: RP =VIH.
15/49
M28W800CT, M28W800CB
Table5. Read Block Lock Signature

Note:1.A Locked-Down Blockcanbe locked "DQ0=1"or unlocked "DQ0=0";see Block Locking section.
Table6. Read Protection Register and Lock Register
Table7. Program, Erase Times and Program/Erase Endurance Cycles
M28W800CT, M28W800CB
16/49
BLOCK LOCKING

The M28W800C features an instant, individual
block locking scheme that allows any blocktobe
lockedorunlockedwithnolatency. This locking
scheme has three levelsof protection. Lock/Unlock- this first level allows software-
only controlof block locking. Lock-Down- this second level requires
hardware interaction before locking canbe
changed. VPP ≤ VPPLK- the third level offersa complete
hardware protection against program and eraseall blocks.
Thelock status of eachblock canbesetto
Locked, Unlocked, and Lock-Down. Table9, de-
fines allof the possible protection states (WP,
DQ1, DQ0), and AppendixC, Figure 22, showsa
flowchartfor the locking operations.
Readinga Block’sLockStatus

The lock statusof every block can be readin the
Read Electronic Signature modeof the device.To
enter this mode write 90hto the device. Subse-
quent readsat the address specifiedin Table5,
will output the lock statusof that block. The lock
statusis representedby DQ0 and DQ1. DQ0 indi-
cates the Block Lock/Unlock status andis setby
the Lock command and cleared by the Unlock
command.Itis also automatically set when enter-
ing Lock-Down. DQ1 indicates the Lock-Down sta-
tus andis set by the Lock-Down command.It
cannotbe clearedby software, onlybya hardware
resetor power-down.
The following sections explain the operationof the
locking system.
Locked State

The default statusofall blockson power-uporaf-
tera hardware resetis Locked (states (0,0,1)or
(1,0,1)). Locked blocks are fully protected from
any programor erase. Any programor erase oper-
ations attempted ona locked block will returnan
errorin the Status Register. The Status ofa
Locked block can be changedto Unlockedor
Lock-Down using the appropriate software com-
mands. An Unlocked block canbe Lockedby issu-
ing the Lock command.
Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),
can be programmed or erased. All unlocked
blocks returnto the Locked state aftera hardware
resetor when the deviceis powered-down. The
statusof an unlocked block can be changedto
Lockedor Locked-Down using the appropriate
software commands.A locked block can be un-
lockedby issuing the Unlock command.
Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are
protected from program and erase operations (as
for Locked blocks) but their lock status cannotbe
changed using software commands alone.A
Lockedor Unlocked block canbe Locked-Downby
issuing the Lock-Down command. Locked-Down
blocks revertto the Locked state when the device resetor powered-down.
The Lock-Down functionis dependenton the WP
input pin. When WP=0 (VIL), the blocksin the
Lock-Down state (0,1,x) are protected from pro-
gram, erase and protection status changes. When
WP=1 (VIH) the Lock-Down functionis disabled
(1,1,1) and Locked-Down blocks can be individu-
ally unlockedto the (1,1,0) state by issuing the
software command, where they canbe erased and
programmed. These blocks can thenbe relocked
(1,1,1) and unlocked (1,1,0)as desired while WP
remains high. When WPis low, blocks that were
previously Locked-Down returnto the Lock-Down
state (0,1,x) regardlessof any changes made
while WP was high. Device resetor power-down
resetsall blocks, including thosein Lock-Down,to
the Locked state.
Locking Operations During Erase Suspend

Changesto block lock status can be performed
during an erase suspend by using the standard
locking command sequencesto unlock, lockor
lock-downa block. Thisis usefulin the case when
another block needstobe updated whilean erase
operationisin progress. change block locking during an erase opera-
tion, first write the Erase Suspend command, then
check the status register untilit indicates that the
erase operation has been suspended. Next write
the desired Lock command sequencetoa block
and the protection status will be changed. After
completing any desired lock, read,or program op-
erations, resume the erase operation with the
Erase Resume command.a blockis lockedor locked-down duringan erase
suspendof the same block, the locking status bits
will be changed immediately, but when the erase resumed, the erase operation will complete.
Locking operations cannotbe performed duringa
program suspend. Referto Appendix D, Com-
mand Interface and Program/Erase Controller
State, for detailed information on which com-
mands are valid during erase suspend.
17/49
M28W800CT, M28W800CB
Table8. Block Lock Status
Table9. Protection Status

Note:1. The protection statusis definedbythe write protectpin andby DQ1(‘1’fora locked-down block) and DQ0(‘1’fora locked block) readinthe Read Electronic Signature command withA1=VIH andA0=VIL.All blocksare lockedat power-up,sothe default configurationis 001or 101 accordingtoWP status.AWP transitiontoVIHona locked blockwill restorethe previous DQ0 value, givinga111or 110.
M28W800CT, M28W800CB
18/49
STATUS REGISTER

The Status Register provides information on the
currentor previous Programor Erase operation.
The various bits convey information and errorson
the operation. To read the Status register the
Read Status Register command canbe issued,re-
ferto Read Status Register Command section.To
output the contents, the Status Registeris latched the falling edgeof the Chip Enableor Output
Enable signals, and canbe read until Chip Enable Output Enable returnsto VIH. Either Chip En-
ableor Output Enable must be toggledto update
the latched data.
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
The bitsin the Status Register are summarizedin
Table 10, Status Register Bits. Referto Table10 conjunction with the following text descriptions.
Program/Erase Controller Status (Bit7).
The Pro-
gram/Erase Controller Statusbit indicates whether
the Program/Erase Controlleris activeor inactive.
When the Program/Erase Controller Statusbitis
Low (setto ‘0’), the Program/Erase Controlleris
active; when the bitis High (setto ‘1’), the Pro-
gram/Erase Controlleris inactive, and the device readyto processa new command.
The Program/Erase Controller Statusis Low im-
mediately aftera Program/Erase Suspend com-
mandis issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus- thebitis High.
During Program, Erase, operations the Program/
EraseControllerStatusbit canbepolledtofindthe
endof the operation. Other bitsin the Status Reg-
ister should notbe tested until the Program/Erase
Controller completes the operation and thebitis
High.
After the Program/Erase Controller completesits
operation the Erase Status, Program Status, VPP
Status and Block Lock Status bits shouldbe tested
for errors.
Erase Suspend Status (Bit 6).
The Erase Sus-
pend Statusbit indicates that an Erase operation
has been suspendedoris goingtobe suspended.
When the Erase Suspend Statusbitis High (setto
‘1’),a Program/Erase Suspend command has
been issued and the memoryis waiting fora Pro-
gram/Erase Resume command.
The Erase Suspend Status should onlybe consid-
ered valid when the Program/Erase Controller Sta-
tusbitis High (Program/Erase Controller inactive).
Bit7is set within 30μsof the Program/Erase Sus-
pend command being issued therefore the memo- may still complete the operation rather than
entering the Suspend mode.
Whena Program/Erase Resume commandisis-
sued the Erase Suspend Statusbit returns Low.
Erase Status (Bit5).
The Erase Statusbit canbe
usedto identifyif the memory has failedto verify
that the block has erased correctly. When the
Erase Statusbitis High (setto ‘1’), the Program/
Erase Controller has applied the maximum num-
berof pulsesto the block and still failedto verify
that the block has erased correctly. The Erase Sta-
tus bit should be read once the Program/Erase
Controller Statusbitis High (Program/Erase Con-
troller inactive).
Once set High, the Erase Statusbit can onlybere-
set Lowbya Clear Status Register commandora
hardware reset.If set Highit should be reset be-
forea new Programor Erase commandis issued,
otherwise the new command will appearto fail.
Program Status (Bit 4).
The Program Statusbit usedto identifya Program failure. When the
Program Status bitis High (setto ‘1’), the Pro-
gram/Erase Controller has applied the maximum
numberof pulsesto the byte and still failedto ver-
ify thatit has programmed correctly. The Program
Statusbit shouldbe read once the Program/Erase
Controller Statusbitis High (Program/Erase Con-
troller inactive).
Once set High, the Program Statusbit can onlybe
reset Lowbya Clear Status Register commandor hardware reset.If set Highit shouldbe reset be-
forea new commandis issued, otherwise the new
command will appearto fail.
VPP Status (Bit3).
The VPP Status bit can be
usedto identifyan invalid voltageon the VPP pin
during Program and Erase operations. The VPP
pinis only sampledat the beginningofa Program Erase operation. Indeterminate results can oc-
curif VPP becomes invalid duringan operation.
When the VPP Statusbitis Low (setto ‘0’), the volt-
ageon the VPP pin was sampledata valid voltage;
when the VPP Statusbitis High (setto ‘1’), the VPP
pin hasa voltage thatis below the VPP Lockout
Voltage, VPPLK, the memoryis protected and Pro-
gram and Erase operations cannotbe performed.
Once set High, the VPP Statusbit can onlybe reset
Low bya Clear Status Register commandora
hardware reset.If set Highit shouldbe reset be-
forea new Programor Erase commandis issued,
otherwise the new command will appearto fail.
Program Suspend Status (Bit 2).
The Program
Suspend Statusbit indicates thata Program oper-
ation has been suspended. When the Program
Suspend Statusbitis High (setto ‘1’),a Program/
Erase Suspend command has been issued and
the memoryis waiting fora Program/Erase Re-
sume command. The Program Suspend Status
should only be considered valid when the Pro-
19/49
M28W800CT, M28W800CB

gram/Erase Controller Statusbitis High (Program/
Erase Controller inactive).Bit2is set within 5μsof
the Program/Erase Suspend command beingis-
sued therefore the memory may still complete the
operation rather than entering the Suspend mode.
Whena Program/Erase Resume commandisis-
sued the Program Suspend Statusbit returns Low.
Block Protection Status (Bit1).
The Block Pro-
tectionStatusbit canbeusedtoidentifyifa Pro-
gramor Erase operation has triedto modify the
contentsofa locked block.
When the Block Protection Statusbitis High (set ‘1’),a Programor Erase operation has beenat-
temptedona locked block.
Once set High, the Block Protection Statusbit can
onlybe reset Lowbya Clear Status Register com-
mandora hardware reset.If set Highit shouldbe
reset beforea new commandis issued, otherwise
the new command will appear to fail.
Reserved (Bit 0).
Bit0of the Status Registeris
reserved.Its value mustbe masked.
Note: Refer to Appendix C, Flowcharts and
Pseudo Codes, for using the Status Register.
Table 10. Status Register Bits

Note: Logic level'1'is High,'0'is Low.
M28W800CT, M28W800CB
20/49
MAXIMUM RATING

Stressing the deviceabove therating listedinthe
Absolute Maximum Ratings table may cause per-
manent damageto the device. These are stress
ratings only and operationof the deviceat theseor
any other conditions above those indicatedin the
Operating sectionsof this specificationis not im-
plied. Exposureto Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer alsoto the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 11. Absolute Maximum Ratings

Note:1. Dependson range.
21/49
M28W800CT, M28W800CB AND AC PARAMETERS

This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristicsof the device. The parametersin the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 12,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions their circuit match the measurement conditions
when relyingon the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Table 13. Capacitance

Note: Sampled only,not 100% tested.
M28W800CT, M28W800CB
22/49
Table 14. DC Characteristics
23/49
M28W800CT, M28W800CB
M28W800CT, M28W800CB
24/49
25/49
M28W800CT, M28W800CB
Table 16. Write AC Characteristics, Write Enable Controlled

Note:1. Sampled only,not 100% tested. Applicableif VPPis seenasa logic input (VPP <3.6V).
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