M28W160BT100ZB6T ,16 MBIT (1MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYFEATURES SUMMARY■ SUPPLY VOLTAGE Figure 1. Packages–V = 2.7V to 3.6V Core Power SupplyDD–V = 1.65V ..
M28W160BT-90N6 ,16 MBIT (1MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYTABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
M28W160CB ,V(dd): -0.6 to +4.1V; 16 Mbit (1Mb x 16, boot block) 3V supply flash memoryAbsolute Maximum Ratings . . . . . . . 20DC and AC PARAMETERS . 21Table 12. Operating an ..
M28W160CB-100N6 , 16 Mbit (1Mb x16, Boot Block) 3V Supply Flash Memory
M28W160CB70N6 ,16 MBIT (1MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYAbsolute Maximum Ratings . . . . . . . 20DC and AC PARAMETERS . 21Table 12. Operating an ..
M28W160CB70N6 ,16 MBIT (1MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORYLogic Diagram1.65V. An optional 12V V power supply is pro-PPvided to speed up customer programming. ..
M4N26 ,6-Pin DIP Optoisolators Transistor Output
M4N37 ,6-Pin DIP Optoisolators Transistor Output
M4T28-BR12SH ,TIMEKEEPER SNAPHAT Battery & CrystalAbsolute Maximum Ratings . 7DC and AC PARAMETERS . . 8Table 3. DC and AC Measurement Co ..
M4T28-BR12SH1 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)M4T28-BR12SHM4T32-BR12SH® ®TIMEKEEPER SNAPHAT (Battery & Crystal)
M4T32-BR12SH1 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)Logic Diagram Table 1. Signal NamesX1 Crystal InputX2 Crystal OutputX1 X2V Negative VoltageBAT–V Po ..
M4T32-BR12SH6 ,TIMEKEEPER SNAPHAT (BATTERY & CRYSTAL)TABLE OF CONTENTSSUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... ..
M28W160BB-90N6-M28W160BT100ZB6T-M28W160BT-90N6
16 MBIT (1MB X16, BOOT BLOCK) 3V SUPPLY FLASH MEMORY
1/45May 2002
M28W160BT
M28W160BB Mbit (1Mb x16, Boot Block) Supply Flash Memory
FEATURES SUMMARY SUPPLY VOLTAGE
–VDD= 2.7Vto 3.6V Core Power Supply
–VDDQ= 1.65Vto 3.6Vfor Input/Output
–VPP= 12Vfor fast Program (optional) ACCESS TIME:70,85, 90,100ns PROGRAMMING TIME 10μs typical Double Word Programming Option COMMON FLASH INTERFACE64bit Security Code MEMORY BLOCKS Parameter Blocks (Topor Bottom location) Main Blocks BLOCK PROTECTIONon TWO PARAMETER
BLOCKS
–WPfor Block Protection AUTOMATIC STAND-BY MODE PROGRAM and ERASE SUSPEND 100,000 PROGRAM/ERASE CYCLESper
BLOCK ELECTRONIC SIGNATURE Manufacturer Code: 20h Top Device Code, M28W160BT: 90h Bottom Device Code, M28W160BB: 91h
M28W160BT, M28W160BB2/45
TABLEOF CONTENTS
SUMMARY DESCRIPTION... ...... ....... ...... ....... ...... ....... ...... ...... .....5Figure 2.LogicDiagram.. ...... ....... ...... ....... ...... ....... ...... ...... .....5
Table1. Signal Names... ...... ....... ...... ....... ...... ....... ...... ...... .....5
Figure3. TSOP Connections..... ....... ...... ....... ...... ....... ...... ...... .....6
Figure4. μBGA Connections (Top view through package).. ...... ....... ...... ...... .....7
Figure5. TFBGA Connections (Top view through package). ...... ....... ...... ...... .....8
Figure 6.Block Addresses. ...... ....... ...... ....... ...... ....... ...... ...... .....9
SIGNAL DESCRIPTIONS .... ...... ....... ...... ....... ...... ....... ...... ...... ....10Address Inputs (A0-A19).. ...... ....... ...... ....... ...... ....... ...... ...... ....10
Data Input/Output (DQ0-DQ15)... ....... ...... ....... ...... ....... ...... ...... ....10
Chip Enable (E)... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Output Enable (G). ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Write Enable (W).. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Write Protect (WP). ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
Reset(RP). ...... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
VDD Supply Voltage...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
VDDQ Supply Voltage..... ...... ....... ...... ....... ...... ....... ...... ...... ....10
VPP Program Supply Voltage .... ....... ...... ....... ...... ....... ...... ...... ....10
VSS Ground. ..... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....10
BUS OPERATIONS... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11Read. .... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Write. .... ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Output Disable.... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Standby.. ....... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Automatic Standby. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....11
Reset. ... ....... ...... ...... ....... ...... ....... ...... ....... ............ ....11
Table 2.Bus Operations.. ...... ....... ...... ....... ...... ....... ...... ...... ....11
COMMANDINTERFACE .... ...... ....... ...... ....... ...... ....... ...... ...... ....12Read Memory Array command... ....... ...... ....... ...... ....... ...... ...... ....12
Read Status Register Command.. ....... ...... ....... ...... ....... ...... ...... ....12
Read Electronic Signature Command ..... ...... ....... ...... ....... ...... ...... ....12
Read CFIQueryCommand...... ....... ...... ....... ...... ....... ...... ...... ....12
Block Erase Command... ...... ....... ...... ....... ...... ....... ...... ...... ....12
Program Command ...... ...... ....... ...... ....... ...... ....... ...... ...... ....12
Double Word Program Command. ....... ...... ....... ...... ....... ...... ...... ....13
Clear Status Register Command.. ....... ...... ....... ...... ....... ...... ...... ....13
Program/Erase Suspend Command ...... ...... ....... ...... ....... ...... ...... ....13
Program/Erase Resume Command ...... ...... ....... ...... ....... ...... ...... ....13
Block Protection... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....13
Table 3.Commands ..... ...... ....... ...... ....... ...... ....... ...... ...... ....14
Table 4.Read ElectronicSignature....... ...... ....... ...... ....... ...... ...... ....14
3/45
M28W160BT, M28W160BBTable 5.MemoryBlocks Protection Truth Table... ....... ...... ....... ...... ...... ....14
Table 6.Program,Erase Times and Program/Erase Endurance Cycles .... ...... ...... ....15
STATUS REGISTER.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16Program/Erase Controller Status(Bit7)... ...... ....... ...... ....... ...... ...... ....16
Erase Suspend Status(Bit6) .... ....... ...... ....... ...... ....... ...... ...... ....16
Erase Status(Bit5) ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Program Status(Bit4) .... ...... ....... ...... ....... ...... ....... ...... ...... ....16
VPP Status(Bit 3).. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....16
Program Suspend Status(Bit2).. ....... ...... ....... ...... ....... ...... ...... ....16
Block Protection Status(Bit 1).... ....... ...... ....... ...... ....... ...... ...... ....17
Reserved(Bit 0)... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....17
Table 7.StatusRegister Bits ..... ....... ...... ....... ...... ....... ...... ...... ....17
MAXIMUM RATING... ...... ...... ....... ...... ....... ...... ....... ...... ...... ....18Table 8.Absolute Maximum Ratings...... ...... ....... ...... ....... ...... ...... ....18
andAC PARAMETERS.. ...... ....... ...... ....... ...... ....... ...... ...... ....19Table9. Operating andAC Measurement Conditions...... ...... ....... ...... ...... ....19
Figure 7.AC MeasurementI/O Waveform. ...... ....... ...... ....... ...... ...... ....19
Figure8.AC Measurement Load Circuit... ...... ....... ...... ....... ...... ...... ....19
Table10. Device Capacitance.... ....... ...... ....... ...... ....... ...... ...... ....19
Table11.DC Characteristics..... ....... ...... ....... ...... ....... ...... ...... ....20
Figure 9.Read ModeAC Waveforms ..... ...... ....... ...... ....... ...... ...... ....21
Table12. ReadAC Characteristics ....... ...... ....... ...... ....... ...... ...... ....21
Figure10. WriteAC Waveforms, Write Enable Controlled.. ...... ....... ...... ...... ....22
Table13. WriteAC Characteristics, Write Enable Controlled ...... ....... ...... ...... ....23
Figure11. WriteAC Waveforms, Chip Enable Controlled... ...... ....... ...... ...... ....24
Table14. WriteAC Characteristics, Chip Enable Controlled ...... ....... ...... ...... ....25
Figure12. Power-Up and ResetAC Waveforms... ....... ...... ....... ...... ...... ....26
Table15. Power-Up and ResetACCharacteristics ....... ...... ....... ...... ...... ....26
PACKAGE MECHANICAL... ...... ....... ...... ....... ...... ....... ...... ...... ....27Figure13. TSOP48-48 lead Plastic Thin Small Outline,12 x20mm, Package Outline .... ....27
Table16. TSOP48-48 lead Plastic Thin Small Outline,12x 20mm, Package Mechanical Data.27
Figure14. μBGA46 6.39x6.37mm-8x6ball array, 0.75 mm pitch, Bottom View Package Outline28
Table17. μBGA46 6.39x6.37mm-8x6ball array, 0.75 mm pitch, Package Mechanical Data...28
Figure15. μBGA46 Daisy Chain- Package Connections (Top view through package) ..... ....29
Figure16. μBGA46 DaisyChain- PCBConnectionsproposal (Top viewthrough package). ....29
Figure17. TFBGA46 6.39x6.37mm- 8x6ball array, 0.75mm pitch, Bottom View Package Outline30
Table18. TFBGA46 6.39x6.37mm- 8x6ball array, 0.75mm pitch,Package Mechanical Data ...30
Figure18. TFBGA46 Daisy Chain- Package Connections (Top view through package) .... ....31
Figure19. TFBGA46 Daisy Chain- PCB Connections proposal (Top view through package) ....31
PART NUMBERING.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....32
M28W160BT, M28W160BB4/45
Table19. Ordering Information Scheme... ...... ....... ...... ....... ...... ...... ....32
Table20. DaisyChain Ordering Scheme.. ...... ....... ...... ....... ...... ...... ....32
REVISION HISTORY.. ...... ...... ....... ...... ....... ...... ....... ...... ...... ....33Table21. Document Revision History ..... ...... ....... ...... ....... ...... ...... ....33
APPENDIXA. BLOCK ADDRESS TABLES.. ...... ....... ...... ....... ...... ...... ....34Table22. Top Boot Block Addresses, M28W160BT ....... ...... ....... ...... ...... ....34
Table23. Bottom Boot Block Addresses, M28W160BB .... ...... ....... ...... ...... ....34
APPENDIXB. COMMONFLASH INTERFACE (CFI). ....... ...... ....... ...... ...... ....35Table24. Query Structure Overview ...... ...... ....... ...... ....... ...... ...... ....35
Table25. CFI Query Identification String.. ...... ....... ...... ....... ...... ...... ....35
Table26. CFIQuerySystem Interface Information. ....... ...... ....... ...... ...... ....36
Table27. Device Geometry Definition ..... ...... ....... ...... ....... ...... ...... ....37
Table28. Primary Algorithm-Specific Extended Query Table ...... ....... ...... ...... ....38
Table29. Security Code Area .... ....... ...... ....... ...... ....... ...... ...... ....38
APPENDIXC. FLOWCHARTS AND PSEUDO CODES....... ...... ....... ...... ...... ....39Figure20. Program Flowchart and Pseudo Code.. ....... ...... ....... ...... ...... ....39
Figure21. Double Word Program Flowchart and Pseudo Code .... ....... ...... ...... ....40
Figure22. Program Suspend& Resume Flowchart and Pseudo Code ..... ...... ...... ....41
Figure23. Erase Flowchart and Pseudo Code .... ....... ...... ....... ...... ...... ....42
Figure24. Erase Suspend& Resume Flowchart and Pseudo Code. ....... ...... ...... ....43
APPENDIXD. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE... ....44Table30. Write State Machine Current/Next...... ....... ...... ....... ...... ...... ....44
5/45
M28W160BT, M28W160BB
SUMMARY DESCRIPTIONThe M28W160Bisa16 Mbit(1 Mbitx16) non-vol-
atileFlash memory that canbeerasedelectricallythe block level and programmed in-systemona
Word-by-Word basis. These operations canbe
performed usinga singlelow voltage (2.7to 3.6V)
supply. VDDQ allowsto drivetheI/Opin downto
1.65V.An optional 12V VPP power supplyis pro-
videdto speedup customer programming.
The device featuresan asymmetrical blockedar-
chitecture. The M28W160B hasan arrayof39
blocks:8 Parameter Blocksof4 KWord and31
Main Blocksof32 KWord. M28W160BT hasthe
Parameter Blocksatthetopofthe memory ad-
dress space while the M28W160BB locatesthe
Parameter Blocks starting fromthe bottom. The
memory mapsare shownin Figure6, Block Ad-
dresses.
Parameter blocks0 and1 canbe protected from
accidental programmingor erasure. Each block
canbe erased separately. Erase canbe suspend-in orderto perform either reador programin
any other block and then resumed. Program can suspendedto read datain any other block and
then resumed. Each block canbe programmed
and erased over 100,000 cycles.
Program and Erase commandsare writtentothe
Command Interfaceof the memory.An on-chip
Program/Erase Controller takes careofthe tim-
ings necessaryfor program and erase operations.
The endofa programor erase operation canbe
detected and any error conditions identified. The
commandset requiredto controlthe memoryis
consistent with JEDEC standards.
The memoryis offeredin TSOP48(10X 20mm),
μBGA46 (6.39x 6.37mm, 0.75mm pitch) and
TFBGA46 (6.39x 6.37mm, 0.75mm pitch) packag- andis supplied withallthe bits erased (setto
’1’).
M28W160BT, M28W160BB6/45
7/45
M28W160BT, M28W160BB
M28W160BT, M28W160BB8/45
9/45
M28W160BT, M28W160BB
M28W160BT, M28W160BB10/45
SIGNAL DESCRIPTIONSSee Figure2 Logic Diagram and Table 1,Signal
Names,fora brief overviewofthe signals connect-tothis device.
Address Inputs (A0-A19). The Address Inputs
selectthe cellsinthe memory arrayto access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sentto the
Command Interfaceofthe internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data storedat the selected address
duringa Bus Read operationor inputsa command datatobe programmed duringa Write Busop-
eration.
Chip Enable (E). The Chip Enable input acti-
vatesthe memory control logic, input buffers,de-
codersand sense amplifiers. When Chip Enableis VILand ResetisatVIHthe deviceisin active
mode. When Chip EnableisatVIHthe memoryis
deselected,the outputsare high impedance and
the power consumptionis reducedtothe stand-by
level.
Output Enable (G). The Output Enable controls
data outputs duringthe Bus Read operationofthe
memory.
WriteEnable(W). The Write Enable controlsthe
Bus Write operationofthe memory’s Command
Interface. The data and address inputsare latched therisingedgeof ChipEnable,E, orWriteEn-
able,W, whichever occurs first.
Write Protect (WP). Write Protectisan inputto
protector unprotect the two lockable parameter
blocks. When Write Protectisat VIL,the lockable
blocksare protected and Programor Erase oper-
ationsarenot possible. When Write Protectisat
VIH,the lockable blocksare unprotected and can programmedor erased (referto Table4, Mem-
ory Blocks Protection Truth).
Reset (RP). The Reset input providesa hard-
ware resetofthe memory. When ResetisatVIL,
the memoryisin reset mode:the outputsare high
impedance andthe current consumptionis mini-
mized. When Resetisat VIH,the deviceisin nor-
mal operation. Exiting reset mode the device
enters read array mode,buta negative transition Chip Enableora changeofthe addressisre-
quiredto ensure valid data outputs.
VDD Supply Voltage. VDD provides the power
supplytothe internal coreofthe memory device.is the main power supplyforall operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the
power supplytotheI/O pins and enablesall Out-
putstobe powered independently from VDD.VDDQ
canbetied toVDDor can usea separate supply.
VPP Program Supply Voltage. VPPis botha
control input anda power supply pin. The two
functions are selectedbythe voltage range ap-
pliedtothe pin. The Supply Voltage VDD andthe
Program Supply Voltage VPP canbe appliedin
any order. VPPis keptinalow voltage range (0Vto 3.6V)
VPPis seenasa control input.Inthis casea volt-
age lower than VPPLK givesan absolute protection
against programor erase, while VPP >VPP1en-
ables these functions (see Table11,DC Charac-
teristics for the relevant values). VPPis only
sampledatthe beginningofa programor erase;a
changeinits value afterthe operation has started
doesnot haveany effect and programor eraseop-
erations continue. VPPisinthe range 11.4Vto 12.6Vit actsasa
power supply pin.In this condition VPP mustbe
stable untilthe Program/Erase algorithmis com-
pleted (see Table13 and 14).
VSS Ground. VSSisthe referenceforall voltage
measurements.
Note: Each deviceina system should have
VDD,VDDQ and VPP decoupled witha 0.1μFca-
pacitor closetothe pin. See Figure8,AC Mea-
surement Load Circuit. The PCB trace widths
shouldbe sufficientto carry the required VPP
Program and Erase currents.
11/45
M28W160BT, M28W160BB
BUS OPERATIONSTherearesix standard bus operations that control
the device. Theseare Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table2, Bus Operations,fora summary.
Typically glitchesof less than 5nson Chip Enable Write Enableare ignoredbythe memory anddo
not affect bus operations.
Read. Read Bus operationsare usedto output
the contentsofthe Memory Array,the Electronic
Signature,the Status Register andthe Common
Flash Interface. Both Chip Enable and OutputEn-
ablemust beatVILin orderto performa readop-
eration. The Chip Enable input shouldbe usedto
enablethe device. Output Enable shouldbe used gate data ontothe output. The data readde-
pendson the previous command writtentothe
memory (see Command Interface section). See
Figure9, Read ModeAC Waveforms, and Table
12, ReadAC Characteristics,for detailsof when
the output becomes valid.
Read modeisthe default stateofthe device when
exiting Resetor after power-up.
Write. Bus Write operations write Commandsto
the memoryor latch Input Datatobe programmed. write operationis initiated when Chip Enable
and Write EnableareatVIL with Output Enableat
VIH. Commands, Input Data and Addresses are
latchedonthe rising edgeof Write Enableor Chip
Enable, whichever occurs first.
See Figures10 and11, WriteAC Waveforms, and
Tables13 and14, WriteAC Characteristics,for
detailsofthe timing requirements.
Output Disable. The data outputs are highim-
pedance whenthe Output Enableisat VIH.
Standby. Standby disables mostofthe internal
circuitry allowinga substantial reductionofthe cur-
rent consumption. The memoryisin stand-by
when Chip Enableisat VIH and thedeviceisin
read mode. The power consumptionis reducedto
the stand-by level andthe outputsaresetto high
impedance, independently fromthe Output Enable Write Enable inputs.If Chip Enable switchesto
VIH duringa programor erase operation,thede-
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
videsalow power consumption state during Read
mode. Followinga read operation,the deviceen-
ters Automatic Standby after 150nsof bus inactiv-
ity, evenif Chip Enableis low, VIL, andthe supply
currentis reducedto IDD1. The data Inputs/Out-
putswillstill output data.
Reset. During Reset mode, when Output Enable low, VIL,the memoryis deselected andthe out-
putsare high impedance. The memoryisin Reset
mode when Resetisat VIL. The power consump-
tionis reducedtothe Standby level, independently
fromthe Chip Enable, Output Enableor WriteEn-
able inputs.If Resetis pulledto VSS duringa Pro-
gramor Erase, this operationis aborted andthe
memory contentisno longer valid.
Table2. Bus OperationsNote:X= VILor VIH,VPPH =12V±5%.
M28W160BT, M28W160BB12/45
COMMAND INTERFACEAll Bus Write operationstothe memoryare inter-
pretedby the Command Interface. Commands
consistof oneor more sequential Bus Write oper-
ations.An internal Program/Erase Controller han-
dlesall timings and verifiesthe correct executionthe Program and Erase commands. The Pro-
gram/Erase Controller providesa Status Register
whose output maybe readatany time,to monitor
the progressofan operation,or the Program/
Erase states. See AppendixD, Table30, Write
State Machine Current/Next,fora summaryofthe
Command Interface.
The Command Interfaceis resetto Read mode
when poweris first applied, when exiting from Re-
setor whenever VDDis lower than VLKO.Com-
mand sequences mustbe followed exactly. Any
invalid combinationof commandswill resetthede-
viceto Read mode. Referto Table3, Commands, conjunction withthe text descriptions below.
Read Memory Array commandTheReadcommand returns the memorytoits
Read mode. One Bus Write cycleis requiredtois-
suethe Read Memory Array command and return
the memoryto Read mode. Subsequent readop-
erationswill readthe addressed location and out-
put the data. Whena device Reset occurs,the
memory defaultsto Read mode.
Read Status Register CommandThe Status Register indicates whena programor
erase operationis complete and the successor
failureofthe operation itself. Issuea Read Status
Register commandto readthe Status Register’s
contents. Subsequent Bus Read operations read
the Status Register,at any address, until another
commandis issued. See Table7, Status Register
Bits,for detailsonthe definitionsofthe bits.
The Read Status Register command maybeis-
suedat any time, even duringa Program/Erase
operation. Any Read attempt duringa Program/
Erase operationwill automatically outputthe con-
tentofthe Status Register.
Read Electronic Signature CommandThe Read Electronic Signature command reads
the Manufacturer and Device Codes.
The Read Electronic Signature command consists one write cycle,a subsequent readwill output
the Manufacturerorthe Device Code dependingthe levelsofA0. The Manufacturer Codeis out-
put whenthe address lineA0isat VIL,the Device
Codeis output whenA0isat VIH. Addresses A1- mustbe keptto VIL, other addressesareig-
nored. The codes are outputon DQ0-DQ7 with
DQ8-DQ15at 00h. (see Table4)
Read CFI Query CommandThe Read Query Commandis usedto read data
from theCommonFlash Interface(CFI) Memory
Area, allowing programming equipmentor appli-
cationsto automatically match their interfaceto
the characteristicsofthe device.
One Bus Write cycleis requiredto issuethe Read
Query Command. Oncethe commandis issued
subsequent Bus Read operations read fromthe
Common Flash Interface Memory Area. See Ap-
pendixB, Common Flash Interface, Tables24,25,
26,27,28 and29for detailsonthe information
containedinthe Common Flash Interface memory
area.
Block Erase CommandTheBlock Erase command can beusedtoerase block.It setsallthebits withinthe selected block’1’.All previous datainthe blockis lost.Ifthe
blockis protected then the Erase operationwill
abort,the datainthe blockwillnotbe changed and
the Status Registerwill outputthe error.
Two Bus Write cycles are requiredto issuethe
command. The first bus cycle setsupthe Erase command. The second latchesthe block addressinthe
internal state machine and startsthe Program/
Erase Controller.the second bus cycleisnot Write Erase Confirm
(D0h), Status Register bitsb4 andb5areset and
the command aborts.
Erase abortsif Reset turnstoVIL.As data integrity
cannotbe guaranteed whenthe Erase operationis
aborted,the block mustbe erased again.
During Erase operationsthe memorywill onlyac-
ceptthe Read Status Register command andthe
Program/Erase Suspend command,all other com-
mandswillbe ignored. Typical Erase times are
givenin Table6, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See AppendixC, Figure23, Erase Flowchart and
Pseudo Code,forthe flowchartfor usingthe Erase
command.
Program CommandThe memory array canbe programmed word-by-
word. Two bus write cyclesare requiredto issue
the Program command. The first bus cycle setsupthe Program
command. The secondlatchesthe Address andthe Datato written and startsthe Program/Erase
Controller.
During Program operationsthe memorywill only
acceptthe Read Status Register command and
the Program/Erase Suspend command.All other
13/45
M28W160BT, M28W160BBcommandswillbe ignored. Typical Program times
are givenin Table6, Program, Erase Times and
Program/Erase Endurance Cycles.
Programming abortsif Reset goesto VIL.As data
integrity cannotbe guaranteed whenthe program
operationis aborted, the block containing the
memory location mustbe erased and repro-
grammed.
See AppendixC, Figure20, Program Flowchart
and Pseudo Code,forthe flowchartfor usingthe
Program command.
Double Word Program CommandThis featureis offeredto improvethe programming
throughput, writinga pageof two adjacent words parallel.The two words must differ onlyforthe
addressA0. Programming shouldnotbe attempt- when VPPisnotat VPPH. The command canbe
executedif VPPis below VPPHbutthe resultisnot
guaranteed.
Three bus write cyclesare necessaryto issuethe
Double Word Program command. The first bus cycle setsupthe Double Word
Program command. The second bus cycle latchesthe Address and
the Dataofthe first wordtobe written. The third bus cycle latchesthe Address andthe
Dataofthe second wordtobe written and starts
the Program/Erase Controller.
Read operations outputthe Status Register con-
tent afterthe programming has started. Program-
ming abortsif Reset goesto VIL.As data integrity
cannotbe guaranteed whenthe program opera-
tionis aborted,the block containingthe memory
location mustbe erased and reprogrammed.
See AppendixC, Figure21, Double Word Pro-
gram Flowchart and Pseudo Code,forthe flow-
chart for using the Double Word Program
command.
Clear Status Register CommandThe Clear Status Register command canbe used resetbits1,3,4 and5inthe Status Registerto
‘0’. One bus write cycleis requiredto issuethe
Clear Status Register command.
Thebitsinthe Status Registerdonot automatical- returnto‘0’ whena new Programor Erase com-
mandis issued. The error bitsin the Status
Register shouldbe cleared before attemptinga
new Programor Erase command.
Program/Erase Suspend CommandThe Program/Erase Suspend commandis usedto
pausea Programor Erase operation. One bus
write cycleis requiredto issuethe Program/Erase
command and pausethe Program/Erase control-
ler.
During Program/Erase Suspendthe CommandIn-
terface will accept the Program/Erase Resume,
Read Array, Read Status Register, Read Electron- Signature and Read CFI Query commands.Ad-
ditionally,ifthe suspend operation was Erase then
the Program commandwill alsobe accepted. Only
the blocksnot being erased maybe reador pro-
grammed correctly.
Duringa Program/Erase Suspend,the device can placedina pseudo-standby modeby taking
Chip Enableto VIH. Program/Eraseis abortedif
Reset turnsto VIL.
See AppendixC, Figure22, Program Suspend&
Resume Flowchart and Pseudo Code, and Figure
24, Erase Suspend& Resume Flowchart and
Pseudo Codefor flowchartsfor usingthe Program/
Erase Suspend command.
Program/Erase Resume CommandThe Program/Erase Resume command canbe
usedto restartthe Program/Erase Controller after Program/Erase Suspend operation has paused
it. One Bus Write cycleis requiredto issuethe
command. Oncethe commandis issued subse-
quent Bus Read operations readthe Status Reg-
ister.
See AppendixC, Figure22, Programor Double
Word Program Suspend& Resume Flowchart and
Pseudo Code, and Figure24, Erase Suspend&
Resume Flowchart and Pseudo Codefor flow-
chartsfor usingthe Program/Erase Resume com-
mand.
Block ProtectionTwo parameter/lockable blocks (blocks#0 and#1)
canbe protected against Programor Erase oper-
ations. Unprotected blockscanbe programmedor
erased. protectthe two lockable blocksset Write Pro-
tectto VIL. When VPPis below VPPLKall blocksare
protected. Any attemptto Programor Erase pro-
tected blockswill abort,the datainthe blockwill
notbe changed andthe Status Register outputs
the error.
Table5, Memory Blocks Protection Truth Table,
definesthe protection methods.
M28W160BT, M28W160BB14/45
Table3. CommandsNote:1.X= Don't Care. A0=VIL outputs Manufacturer code, A0=VIH outputs Device code. Address A7-A1 mustbeVIL. Addr1andAddr2 mustbe consecutive Addresses differingonlyforA0.
Table4. Read Electronic SignatureNote: RP =VIH.
Table5. Memory Blocks Protection Truth TableNote:1.X= Don't Care VPPmustalsobe greaterthanthe Program VoltageLockOut VPPLK.
15/45
M28W160BT, M28W160BB
Table6. Program, Erase Times and Program/Erase Endurance Cycles
M28W160BT, M28W160BB16/45
STATUS REGISTERThe Status Register provides informationonthe
currentor previous Programor Erase operation.
The variousbits convey information and errorson
the operation.To read the Status register the
Read Status Register command canbe issued,re-
fertothe Read Status Register Command section. output the contents, the Status Registeris
latchedonthe falling edgeofthe Chip Enableor
Output Enable signals, and canbe read until Chip
Enableor Output Enable returnsto VIH. Either
Chip Enableor Output Enable mustbe toggledto
updatethe latched data.
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
Thebitsinthe Status Registerare summarizedin
Table7, Status Register Bits. Referto Table7in
conjunction withthe following text descriptions.
Program/Erase Controller Status(Bit7). The Pro-
gram/Erase Controller Statusbit indicates whether
the Program/Erase Controlleris activeor inactive.
Whenthe Program/Erase Controller Statusbitis
Low (setto ‘0’),the Program/Erase Controlleris
active; whenthebitis High (setto ‘1’),the Pro-
gram/Erase Controlleris inactive, andthe device readyto processa new command.
The Program/Erase Controller Statusis Lowim-
mediately aftera Program/Erase Suspend com-
mandis issued untilthe Program/Erase Controller
pauses. Afterthe Program/Erase Controller paus-thebitis High.
During Program, Erase, operationsthe Program/
EraseControllerStatusbit canbepolledtofindthe
endofthe operation. Otherbitsinthe Status Reg-
ister shouldnotbe tested untilthe Program/Erase
Controller completesthe operation andthebitis
High.
Afterthe Program/Erase Controller completesits
operationthe Erase Status, Program Status, VPP
Status and Block Protection Status bits shouldbe
testedfor errors.
Erase Suspend Status (Bit6). The Erase Sus-
pend Statusbit (setto‘1’) indicates thatan Erase
operation has been suspendedoris goingtobe
suspended.
The Erase Suspend Status should onlybe consid-
ered valid whenthe Program/Erase Controller Sta-
tusbitis High (Program/Erase Controller inactive).
Bit7isset within 30μsofthe Program/Erase Sus-
pend command being issued thereforethe memo- may still complete the operation rather than
enteringthe Suspend mode.
Whena Program/Erase Resume commandisis-
suedthe Erase Suspend Statusbit returns Low.
Erase Status (Bit5). The Erase Statusbitcanbe
usedto identifyifthe memory has failedto verify
that the block has erased correctly. When the
Erase Statusbitis High (setto ‘1’),the Program/
Erase Controller has appliedthe maximum num-
berof pulsestothe block and still failedto verify
thatthe blockhas erased correctly. The Erase Sta-
tusbit shouldbe read oncethe Program/Erase
Controller Statusbitis High (Program/Erase Con-
troller inactive).
Onceset High,the Erase Statusbit can onlybere-
set Lowbya Clear Status Register commandora
hardware reset.Ifset Highit shouldbe resetbe-
forea new Programor Erase commandis issued,
otherwisethe new commandwill appearto fail.
Program Status (Bit4). The Program Statusbit usedto identifya Program failure. Whenthe
Program Statusbitis High (setto ‘1’), the Pro-
gram/Erase Controller has appliedthe maximum
numberof pulsestothe byte andstill failedto ver-
ify thatithas programmed correctly. The Program
Statusbit shouldbe read oncethe Program/Erase
Controller Statusbitis High (Program/Erase Con-
troller inactive).
Onceset High,the Program Statusbit can onlybe
reset Lowbya Clear Status Register commandor hardware reset.Ifset Highit shouldbe resetbe-
forea new commandis issued, otherwisethe new
commandwill appeartofail.
VPP Status (Bit3). The VPP Statusbit canbe
usedto identifyan invalid voltageonthe VPPpin
during Program and Erase operations. The VPP
pinis only sampledatthe beginningofa Program Erase operation. Indeterminate results canoc-
curif VPP becomes invalid duringan operation.
Whenthe VPP Statusbitis Low (setto‘0’),the volt-
ageonthe VPPpin was sampledata valid voltage;
whenthe VPP Statusbitis High (setto‘1’),the VPP
pin hasa voltage thatis belowthe VPP Lockout
Voltage, VPPLK,the memoryis protected and Pro-
gram and Erase operations cannotbe performed.
Onceset High,the VPP Statusbitcan onlybe reset
Lowbya Clear Status Register commandora
hardware reset.Ifset Highit shouldbe resetbe-
forea new Programor Erase commandis issued,
otherwisethe new commandwill appearto fail.
Program Suspend Status (Bit2). The Program
Suspend Statusbit (setto‘1’) indicates thata Pro-
gram operation has been suspendedoris goingto suspended.
The Program Suspend Status should onlybe con-
sidered valid whenthe Program/Erase Controller
Statusbitis High (Program/Erase Controller inac-
tive).Bit2isset within 5μsofthe Program/Erase
Suspend command being issued therefore the
17/45
M28W160BT, M28W160BBmemory may still complete the operation rather
than entering the Suspend mode.
Whena Program/Erase Resume commandisis-
suedthe Program Suspend Statusbit returns Low.
Block Protection Status (Bit1). The Block Pro-
tectionStatusbit canbeusedtoidentifyifa Pro-
gramor Erase operation has triedto modifythe
contentsofa protected block.
Whenthe Block Protection Statusbitis High (set ‘1’),a Programor Erase operation has beenat-
temptedona protected block.
Onceset High,the Block Protection Statusbitcan
onlybe reset Lowbya Clear Status Register com-
mandora hardware reset.Ifset Highit shouldbe
reset beforea new commandis issued, otherwise
the new command will appear to fail.
Reserved (Bit0).Bit0ofthe Status Registeris
reserved.Its value mustbe masked.
Note: Referto AppendixC, Flowcharts and
Pseudo Codes,for usingthe Status Register.
Table7. Status Register BitsNote: Logiclevel'1'is High,'0'isLow.
M28W160BT, M28W160BB18/45
MAXIMUM RATINGStressingthe deviceabove therating listedinthe
Absolute Maximum Ratings table may cause per-
manent damagetothe device. Exposureto Abso-
lute Maximum Rating conditionsfor extended
periods may affect device reliability. These are
stress ratings only and operationofthe deviceat
theseorany other conditions above those indicat-inthe Operating sectionsofthis specificationis
not implied. Refer alsotothe STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table8. Absolute Maximum RatingsNote:1. Dependson range.
19/45
M28W160BT, M28W160BB ANDAC PARAMETERSThis section summarizesthe operating and mea-
surement conditions, andtheDC andAC charac-
teristicsofthe device. The parametersintheDC
andAC characteristics Tables that follow,arede-
rived from tests performed under the Measure-
ment Conditions summarized in Table 9,
Operating andAC Measurement Conditions. De-
signers should check thatthe operating conditions their circuit matchthe measurement conditions
when relyingonthe quoted parameters.
Table9. Operating andAC Measurement Conditions
Table10. Device CapacitanceNote: Sampledonly,not 100% tested.
M28W160BT, M28W160BB20/45
Table11.DC Characteristics
21/45
M28W160BT, M28W160BB
M28W160BT, M28W160BB22/45
23/45
M28W160BT, M28W160BB
Table13. WriteAC Characteristics, Write Enable ControlledNote:1. Sampledonly,not 100% tested. ApplicableifVPPis seenasalogic input(VPP <3.6V).
