M28C64-30WNS6T Fast Delivery |IC PHOENIX CO.,LIMITED

M28C64-30WNS6T ,64 Kbit 8K x 8 Parallel EEPROM With Software Data ProtectionLogic Diagram– 10 Years for M28C64-AVCCTable 1. Signal Names13 8A0-A12 Address InputA0-A12 DQ0-DQ7D ..
M28F101-100K1 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYM28F1011 Mb (128K x 8, Chip Erase) FLASH MEMORY5V ±10% SUPPLY VOLTAGE12V PROGRAMMING VOLTAGEFAST AC ..
M28F101-100K1 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYLogic Diagramchip level and programmed byte-by-byte. It is or-ganisedas 128K bytes of 8 bits.It use ..
M28F101-120K1 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYM28F1011 Mb (128K x 8, Chip Erase) FLASH MEMORY5V ±10% SUPPLY VOLTAGE12V PROGRAMMING VOLTAGEFAST AC ..
M28F101-120K6 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYLogic Diagramchip level and programmed byte-by-byte. It is or-ganisedas 128K bytes of 8 bits.It use ..
M28F101-120N1 ,1 Mb 128K x 8/ Chip Erase FLASH MEMORYM28F1011 Mb (128K x 8, Chip Erase) FLASH MEMORY5V ±10% SUPPLY VOLTAGE12V PROGRAMMING VOLTAGEFAST AC ..
M48Z512AY-70PM1 ,4 Mbit (512Kb x8) ZEROPOWER SRAMBlock Diagram . . 5Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution . ..
M48Z512AY-85PM9 ,4 MBIT (512KB X 8) ZEROPOWER SRAMFEATURES SUMMARY■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. 32-pin PMDIP ModulePOWER-FAIL CONTROL ..
M48Z58-70PC1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMFEATURES SUMMARY■ INTEGRATED, ULTRA LOW POWER SRAM, Figure 1. CAPHAT™ DIP SolutionPOWER-FAIL CONTRO ..
M48Z58-70PC1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMAbsolute Maximum Ratings . . . . . . . 10DC AND AC PARAMETERS . 11Table 6. Operating and ..
M48Z58-70PC1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMBlock Diagram . . 5OPERATING MODES . . . . . . . 6Table 2. Operating Modes 6RE ..
M48Z58Y-70MH1 ,64 Kbit (8Kb X 8) ZEROPOWER SRAMM48Z58M48Z58Y®5V, 64 Kbit (8 Kbit x8) ZEROPOWER SRAM

M28C64-30WNS6T
64 Kbit 8K x 8 Parallel EEPROM With Software Data Protection
1/24June 2000
M28C64 Kbit (8Kx 8) Parallel EEPROM
With Software Data Protection Fast Access Time:
–90nsat VCC=5V forM28C64 and M28C64-A 120nsat VCC=3Vfor M28C64-xxW Single Supply Voltage: 4.5Vto5.5Vfor M28C64 and M28C64-A 2.7Vto3.6Vfor M28C64-xxW Low Power Consumption Fast BYTE and PAGE WRITE(upto64 Bytes)1msat VCC=4.5Vfor M28C64-A3msat VCC=4.5Vfor M28C645msat VCC=2.7Vfor M28C64-xxW Enhanced Write Detection and Monitoring: Ready/Busy Open Drain Output Data Polling ToggleBit Page Load Timer Status JEDEC Approved Bytewide Pin-Out Software Data Protection 100000 Erase/Write Cycles (minimum) Data Retention (minimum):40 Yearsfor M28C64 and M28C64-xxW10 Yearsfor M28C64-A Figure1. Logic Diagram
AI01350C
A0-A12
DQ0-DQ7CC
M28C64
VSS
Table1. Signal Names
A0-A12 Address Input
DQ0-DQ7 Data Input/ Output Write Enable Chip Enable Output Enable Ready/ Busy
VCC Supply Voltage
VSS Ground
PDIP28 (BS)
SO28 (MS)
300mil width
PLCC32 (KA)
TSOP28 (NS)x 13.4mm
M28C64
2/24
Figure2A. DIP Connections
Note:1.NC=Not Connected
Figure2B. PLLC Connections
Note:1.NC=Not ConnectedDU=DoNotUse
DQ0
A10
DQ7
A11
DQ5DQ1
DQ2
DQ3VSS
DQ4
DQ6
A12 VCC
AI01351C
M28C648
AI01352D
A10
DQ4
DQ0
DQ1DQ2
DQ3
A11
DQ6
DQ7V
M28C64
A12
DQ5
Figure2C.SO Connections
Note:1.NC=Not Connected
Figure2D. TSOP Connections
Note:1.NC=Not Connected
DQ0
DQ1
A10
DQ7
DQ5
VCC
DQ4
AI01353C
M28C648
DQ2
VSS
DQ6 A11
DQ3
A12
DQ0
A11
DQ7
DQ5
DQ1
DQ2
DQ3
DQ4
DQ6
A12CC
AI01354C
M28C6428
VSS
A10
DESCRIPTION
The M28C64 devices consistof 8192x8bitsoflow
power, parallel EEPROM, fabricated with
STMicroelectronics’ proprietary single polysilicon
CMOS technology. The devices offer fast access
time, with low power dissipation, and requirea
single voltage supply(5Vor3V, dependingonthe
option chosen).
The device has been designedto offera flexible
microcontroller interface, featuring both hardware
and software handshaking, with Ready/Busy,
Data Polling and ToggleBit. The device supports64 byte Page Write operation. Software Data
Protection (SDP)is also supported, using the
standard JEDEC algorithm.
3/24
M28C64
Figure3. Block Diagram
AI01355
ADDRESS
LATCHA6-A12
(Page Address)
DECODE
CONTROL LOGIC
64K ARRAY
ADDRESS
LATCHA0-A5 DECODEPP GEN RESET
SENSEAND DATA LATCH
I/O BUFFERS E G W
PAGE LOAD
TIMER STATUS
TOGGLEBIT
DATA POLLING
DQ0-DQ7
Table2. Absolute Maximum Ratings1
Note:1. Exceptforthe rating “Operating Temperature Range”, stresses above those listedinthe Table “Absolute Maximum Ratings”may
cause permanent damage tothe device. These arestress ratingsonly,and operationof thedeviceat theseorany other conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposure toAbsolute Maximum Rating condi-
tionsfor extended periodsmay affect device reliability. ReferalsototheST SURE Programand other relevant quality documents. MIL-STD-883C, 3015.7(100pF,1500Ω)
Symbol Parameter Value Unit Ambient Operating Temperature -40to125 °C
TSTG Storage Temperature -65to150 °C
VCC Supply Voltage -0.3 toVCC+1 V
VIO Inputor Output Voltage -0.6to VCC+0.6 V Input Voltage -0.3to6.5 V
VESD Electrostatic Discharge Voltage (Human Body model)2 4000 V
M28C64
4/24
Table3. Operating Modes1
Note:1. 0=VIL;1=VIH;X=VIHorVIL; V=12V±5%.
Mode E G W DQ0-DQ7
Stand-by 1 X X Hi-Z
Output Disable X 1 X Hi-Z
Write Disable X X 1 Hi-Z
Read 0 0 1 DataOut
Write 0 1 0 DataIn
Chip Erase 0 V 0 Hi-Z
SIGNAL DESCRIPTION
The external connectionsto the device are
summarizedin Table1, and their usein Table3.
Addresses (A0-A12). The address inputs are
usedto select one byte fromthe memory array
duringa reador write operation.
Data In/Out (DQ0-DQ7). The contentsofthe data
byteare writtento,or read from,the memory array
throughthe DataI/O pins.
Chip Enable (E). The chip enable input mustbe
held lowto enable read and write operations.
When Chip Enableis high, power consumptionis
reduced.
Output Enable (G). The Output Enable input
controls the data output buffers, andis usedto
initiate read operations.
Write Enable (W). The Write Enable input controls
whetherthe addressed locationistobe read, from writtento.
Ready/Busy (RB). Ready/Busyisan open drain
output that canbe usedto detectthe endofthe
internal write cycle.
DEVICE OPERATION orderto prevent data corruption and inadvertent
write operations,an internal VCC comparator
inhibitsthe Write operationsifthe VCC voltageis
lower than VWI (see Table4Aand Table 4B). Once
the voltage appliedonthe VCCpin goes overthe
VWI threshold (VCC>VWI), write accessto the
memoryis allowed aftera time-out tPUW,as
specifiedin Table4A and Table4B.
Further protection against data corruptionis
offeredbytheE andWlow pass filters:any glitch,theE andW inputs, witha pulse width less thanns (typical)is internally filteredoutto prevent
inadvertent write operationstothe memory.
Table4A. Power-Up Timing1for M28C64 (5V range)
(TA=0to70°Cor –40to85°Cor –40to 125°C; VCC=4.5to5.5V)
Note:1. Sampledonly,not 100% tested.
Table4B. Power-Up Timing1for M28C64-xxW (3V range)
(TA=0to70°Cor –40to85°C; VCC=2.7to3.6V)
Note:1. Sampledonly,not 100% tested.
Symbol Parameter Min. Max. Unit
tPUR Time Delayto Read Operation 1 μs
tPUW Time Delayto Write Operation (onceVCC≥ VWI)10 ms
VWI Write Inhibit Threshold 3.0 4.2 V
Symbol Parameter Min. Max. Unit
tPUR Time Delayto Read Operation 1 μs
tPUW Time Delayto Write Operation (onceVCC≥ VWI)15 ms
VWI Write Inhibit Threshold 1.5 2.5 V
5/24
M28C64
Read
The deviceis accessedlikea static RAM. WhenE
andGare low, andWis high,the contentsofthe
addressed locationare presentedontheI/O pins.
Otherwise, when eitherGorEis high,theI/O pins
revertto their high impedance state.
Write
Write operationsare initiated when bothW andE
are low andGis high. The device supports both
W-controlled and E-controlled write cycles (as
shownin Figure11 and Figure 12). The addressis
latched duringthe falling edgeofWorE (which
ever occurs later) andthe datais latchedonthe
rising edgeofWorE (which ever occurs first).
Aftera delay, tWLQ5H, that cannotbe shorter than
the value specifiedin Table 10Ato Table 10C,the
internal write cycle starts.It continues, under
internal timing control, untilthe write operationis
complete. The commencementof this period can detectedby reading the Page Load Timer
Statuson DQ5. The endof the cycle canbe
detectedby readingthe statusofthe Data Polling
andthe ToggleBit functionson DQ7 and DQ6.
Page Write
The Page Write mode allowsupto64 bytestobe
writtenona single pageina singlego. Thisis
achieved througha seriesof successive Write
operations,notwoof whichare separatedby more
thanthe tWLQ5H value(as specifiedin Table 10A Table 10C).
All bytes mustbe locatedon the same page
address (A12-A6 mustbethe sameforall bytes).
The internal write cycle can startat any instant
after tWLQ5H. Once initiated,the write operationis
internally timed, and continues, uninterrupted,
until completion. withthe single byte Write operation, described
above,the DQ5, DQ6 and DQ7 lines canbe used detectthe beginning and endof the internally
controlled phaseofthe Page Write cycle.
Software Data Protection (SDP)
The device offersa software-controlled write-
protection mechanism that allows the userto
inhibitall write operationstothe device. This can useful for protecting the memory from
inadvertent write cycles that may occur during
periodsof instability (uncontrolled bus conditions
when excessive noiseis detected,or when power
supply levelsare outside their specified values). default, the deviceis shippedin the
“unprotected” state:the memory contents canbe
freely changedbythe user. Oncethe Software
Data Protection Modeis enabled,all write
commandsare ignored,and haveno effectonthe
memory contents.
The device remainsin this mode untila valid
Software Data Protection disable sequenceis
received. The device revertstoits “unprotected”
state.
The statusof the Software Data Protection
(enabledor disabled)is representedbya non-
Figure4. Software Data Protection Enable Algorithm and Memory Write
Note:1.The most significant addressbits(A12toA6)differ during these specific Page Write operations.
AI01356C
WriteAAhin
Address 1555h
Write55hin
Address 0AAAh
Write A0hin
Address 1555h
SDPisset
WriteAAhin
Address 1555h
Write55hin
Address 0AAAh
WriteA0hin
Address 1555h
Page Write upto64 bytes)
Writeto Memory
WhenSDPisSET
SDP Enable Algorithm
Page Write
Timing
(seenote1)
Page Write
Timing
(seenote1)
Write enabled
Physical
Page Write
Instruction
M28C64
6/24
volatile latch, andis remembered across periodsthe power beingoff.
The Software Data Protection Enable command
consistsofthe writingof three specific data bytes three specific memory locations (each location
beingona different page),as shownin Figure4.
Similarlyto disablethe Software Data Protection,
the user hasto write specific data bytes intosix
different locations,as shownin Figure5. This
complex seriesof operations protects againstthe
chanceof inadvertent enablingor disablingofthe
Software Data Protection mechanism.
When SDPis enabled,the memory array canstill
have data writtentoit,butthe sequenceis more
complex (and hence better protected from
inadvertent use). The sequenceisas shownin
Figure4. This consistsofan unlock key,to enable
the write action,at the endof which the SDP
continuestobe enabled. This allowsthe SDPto enabled, and datatobe written, withina single
Write cycle (tWC).
Software Chip Erase
Using this function, availableonthe M28C64but
not on the M28C64-Aor M28C64-xxW, the
contentsofthe entire memoryare erased (setto
FFh)by holding Chip Enable(E) low, and holding
Output Enable (G)at VCC+7.0V. The chipis
cleared whena10mslow pulseis appliedtothe
Write Enable(W) signal (see Figure7 and Table5
for details).
Status Bits
The devices provide three statusbits (DQ7, DQ6
and DQ5), and one outputpin (RB),foruse during
write operations. These allow the applicationto
usethe write time latencyofthe devicefor getting with other work. These signalsare availableon
theI/O port bits DQ7, DQ6 and DQ5 (but only
during programming cycle, oncea byteor more
has been latched intothe memory)or continuouslytheRB output pin.
Data Pollingbit (DQ7). The internally timed write
cycle starts after tWLQ5H (definedin Table 10Ato
Table 10C) has elapsed sincethe previous byte
was latchedintothe memory. The valueofthe
DQ7bitof this last byte,is usedasa signal
Figure5. Software Data Protection Disable Algorithm
AI01357B
WriteAAhin
Address 1555h
Write55hin
Address 0AAAh
Write80hin
Address 1555h
Unprotected State
WriteAAhin
Address 1555h
Write55hin
Address 0AAAh
Write20hin
Address 1555h
Page Write
Timing
Figure6. StatusBit Assignment
AI02815 TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DP
TB
PLTS
Hi-Z
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0Data Polling ToggleBit Page Load Timer Status High impedance
7/24
M28C64
Table5. Chip EraseAC Characteristics1for M28C64 and M28C64-xxW
(TA=0to70°Cor –40to85°Cor –40to 125°C; VCC=4.5to5.5V)
(TA=0to70°Cor –40to85°C; VCC=2.7to3.6V)
Note:1. Sampledonly,not 100% tested.
Symbol Parameter Test Condition Min. Max. Unit
tELWL Chip Enable Lowto Write EnableLow G=VCC +7V 1 μs
tWHEH Write Enable Highto Chip Enable High G=VCC +7V 0 ns
tWLWH2 Write Enable Lowto WriteEnable High G=VCC +7V 10 ms
tGLWH Output EnableLowto Write Enable High G=VCC +7V 1 μs
tWHRH Write Enable Highto WriteEnable Low G=VCC +7V 3 ms
throughout this write operation:itis inverted while
the internal write operationis underway, andis
inverted backtoits original value once the
operationis complete.
Togglebit (DQ6). The device offers another way
for determining when the internal write cycleis
completed. Duringthe internal Erase/Write cycle,
DQ6 toggles from’0’to’1’ and’1’to’0’ (the first
read value being’0’)on subsequent attemptsto
read any byteofthe memory. Whenthe internal
write cycleis complete,the togglingis stopped,
andthe values readon DQ7-DQ0are thoseofthe
addressed memory byte. This indicates that the
deviceis again availablefor new Read and Write
operations.
Page Load Timer Statusbit (DQ5).An internal
timeris usedto measure the period between
successive Write operations, upto tWLQ5H
(definedin Table 10Ato Table 10C). The DQ5 line held lowto show when this timeris running
(hence showing thatthe device has received one
write operation, andis waitingforthe next). The
DQ5 lineis held high when the counter has
overflowed (hence showing thatthe deviceis now
startingthe internal writetothe memory array).
Ready/Busy pin. The RBpinisan open drain
output thatis heldlow duringthe erase/write cycle,
and thatis released (allowedto float)at the
completionofthe programming cycle.
Figure7. Chip EraseAC Waveforms (M28C64 and M28C64-xxW)
AI01484B
tWLWH2tELWL
tGLWH
tWHRH
tWHEH
M28C64
8/24
Table6A. Read ModeDC Characteristicsfor M28C64 and M28C64-A(5V range)
(TA=0to70°Cor –40to85°Cor –40to 125°C; VCC=4.5to5.5V)
Note:1.All inputsand outputs open circuit.
Table6B. Read ModeDC Characteristicsfor M28C64-xxW(3V range)
(TA=0to70°Cor –40to85°C; VCC=2.7to3.6V)
Note:1.All inputsand outputs open circuit.
Symbol Parameter TestCondition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN≤VCC 10 μA
ILO Output Leakage Current 0V≤ VOUT≤VCC 10 μA
ICC1 Supply Current (TTL inputs) E= VIL,G=VIL,f=5 MHz 30 mA
Supply Current (CMOS inputs) E= VIL,G=VIL,f=5 MHz 25 mA
ICC11 Supply Current (Stand-by)TTL E=VIH 1mA
ICC21 Supply Current (Stand-by) CMOS E>VCC- 0.3V 100 μA
VIL InputLow Voltage -0.3 0.8 V
VIH Input High Voltage 2 VCC+0.5 V
VOL Output Low Voltage IOL=2.1mA 0.4 V
VOH Output High Voltage IOH= -400μA 2.4 V
Symbol Parameter TestCondition Min. Max. Unit
ILI Input Leakage Current 0V ≤ VIN≤VCC 10 μA
ILO Output Leakage Current 0V≤ VOUT≤VCC 10 μA
ICC1 Supply Current (CMOS inputs)
E=VIL,G=VIL,f=5 MHz,VCC= 3.3V 8 mA
E=VIL,G=VIL,f=5 MHz,VCC= 3.6V 10 mA
ICC21 Supply Current (Stand-by) CMOS E>VCC- 0.3V 20 μA
VIL InputLow Voltage -0.3 0.6 V
VIH Input High Voltage 2 VCC+0.5 V
VOL Output Low Voltage IOL=1.6mA 0.2VCC V
VOH Output High Voltage IOH= -400μA 0.8VCC V
9/24
M28C64
Table7. Input and Output Parameters1(TA =25°C,f=1 MHz)
Note:1. Sampledonly,not 100% tested.
Table8.AC Measurement Conditions
Symbol Parameter Test Condition Min. Max. Unit
CIN Input Capacitance VIN=0V 6 pF
COUT Output Capacitance VOUT=0V 12 pF
Input RiseandFall Times ≤20ns
Input Pulse Voltages (M28C64, M28C64-A) 0.4Vto2.4V
Input Pulse Voltages (M28C64-xxW) 0Vto VCC-0.3V
Inputand Output Timing Reference Voltages (M28C64, M28C64-A) 0.8Vto2.0V
Inputand Output Timing Reference Voltages (M28C64-xxW) 0.5 VCC
Figure8.AC Testing Input Output Waveforms
AI02101B
4.5Vto5.5V Operating Voltage
2.7Vto3.6V Operating Voltage
VCC–0.3V
0.5VCC
2.4V
0.4V
2.0V
0.8V
Figure9.AC Testing Equivalent Load Circuit
AI02102B
OUTL= 100pFL includesJIG capacitance
IOL
DEVICE
UNDER
TEST
IOH
M28C64
10/24
Table9A. Read ModeAC Characteristicsfor M28C64 and M28C64-A(5V range)
(TA=0to70°Cor –40to85°C; VCC=4.5to5.5V)
Note:1. OutputHi-Zis definedasthepointat which dataisno longer driven.
Table9B. Read ModeAC Characteristicsfor M28C64 (5V range)
(TA= –40to 125°C; VCC=4.5to5.5V)
Note:1. OutputHi-Zis definedasthepointat which dataisno longer driven.
Symbol Alt. Parameter
Test
Condit
ion
M28C64
Unit-90 -12 -15
Min Max Min Max Min Max
tAVQV tACC Address Validto Output Valid E=VIL,VIL 90 120 150 ns
tELQV tCE Chip Enable Lowto Output Valid G=VIL 90 120 150 ns
tGLQV tOE Output EnableLowto Output ValidE=VIL 40 45 50 ns
tEHQZ1 tDF Chip Enable Highto OutputHi-Z G=VIL 040 0 45050 ns
tGHQZ1 tDF Output Enable Highto OutputHi-Z E=VIL 040 0 45050 ns
tAXQX tOH Address Transitionto Output
Transition
E=VIL,VIL 000 ns
Symbol Alt. Parameter
Test
Condit
ion
M28C64
Unit-12
Min Max
tAVQV tACC Address Validto Output Valid E=VIL,VIL 120 ns
tELQV tCE Chip Enable Lowto Output Valid G=VIL 120 ns
tGLQV tOE Output EnableLowto Output Valid E=VIL 45 ns
tEHQZ1 tDF Chip Enable Highto OutputHi-Z G=VIL 065 ns
tGHQZ1 tDF Output Enable Highto OutputHi-Z E=VIL 065 ns
tAXQX tOH Address Transitionto Output
Transition
E=VIL,VIL 0ns
11/24
M28C64
Table9C. Read ModeAC Characteristicsfor M28C64-xxW(3V range)
(TA=0to70°Cor –40to85°C; VCC=2.7to3.6V)
Note:1. OutputHi-Zis definedasthepointat which dataisno longer driven.
Symbol Alt. Parameter
Test
Condit
ion
M28C64-xxW
Unit-12 -15 -20 -25 -30
Min Max Min Max Min Max Min Max Min Max
tAVQV tACC Address Validto
Output Valid
E=VIL,VIL 120 150 200 250 300 ns
tELQV tCE Chip EnableLowto
Output Valid G=VIL 120 150 200 250 300 ns
tGLQV tOE Output Enable Low Output Valid E=VIL 80 80 100 150 150 ns
tEHQZ1 tDF Chip EnableHighto
Output Hi-Z G=VIL 045 0 50 055 0 60 060 ns
tGHQZ1 tDF Output Enable High Output Hi-Z E=VIL 045 0 50 055 0 60 060 ns
tAXQX tOH Address Transition Output Transition
E=VIL,VIL 0 0 000 ns
Figure10. Read ModeAC Waveforms (with Write Enable,W, high)
Note:1. Write Enable(W)=VIH
AI00749B
VALID
tAVQV tAXQX
tGLQV tEHQZ
tGHQZ
DATAOUT
A0-A12
DQ0-DQ7
tELQV
Hi-Z
M28C64
12/24
Table 10A. Write ModeAC Characteristicsfor M28C64 and M28C64-A(5V range)
(TA=0to70°Cor –40to85°C; VCC=4.5to5.5V)
Note:1. Witha3.3kΩ pull-up resistor.
Symbol Alt. Parameter Test Condition
M28C64
Unit
Min Max
tAVWL tAS Address Validto Write EnableLow E= VIL,G=VIH 0ns
tAVEL tAS Address Validto Chip EnableLow G= VIH,W=VIL 0ns
tELWL tCES Chip Enable Lowto Write EnableLow G=VIH 0ns
tGHWL tOES Output Enable Highto Write Enable Low E=VIL 0ns
tGHEL tOES Output Enable Highto Chip EnableLow W=VIL 0ns
tWLEL tWES Write Enable Lowto Chip EnableLow G=VIH 0ns
tWLAX tAH Write Enable Lowto Address Transition 50 ns
tELAX tAH Chip Enable Lowto Address Transition 50 ns
tWLDV tDV Write Enable Lowto Input Valid E= VIL,G=VIH 1 μs
tELDV tDV Chip Enable Lowto Input Valid G= VIH,W=VIL 1 μs
tELEH tWP Chip Enable Lowto Chip Enable High 50 ns
tWHEH tCEH Write Enable Highto Chip Enable High 0 ns
tWHGL tOEH Write Enable Highto Output Enable Low 0 ns
tEHGL tOEH Chip Enable Highto Output EnableLow 0 ns
tEHWH tWEH Chip Enable Highto Write Enable High 0 ns
tWHDX tDH Write Enable Highto Input Transition 0 ns
tEHDX tDH Chip Enable Highto Input Transition 0 ns
tWHWL tWPH Write Enable Highto WriteEnable Low 50 1000 ns
tWLWH tWP Write Enable Lowto WriteEnable High 50 ns
tWLQ5H tBLC
Time-out afterlast byte write (M28C64) 100 μs
Time-out afterlast byte write (M28C64-A) 20 μs
tQ5HQ5X tWC
Write Cycle Time (M28C64) 3 ms
Write Cycle Time (M28C64-A) 1 ms
tWHRL tDB Write Enable Highto Ready/Busy Low Note1 150 ns
tEHRL tDB Chip Enable Highto Ready/BusyLow Note1 150 ns
tDVWH tDS Data Valid before Write Enable High 50 ns
tDVEH tDS Data Valid before Chip Enable High 50 ns

Partno	Mfg	Dc	Qty	Available	Descript
M28C64-30WNS6T \|M28C6430WNS6T	ST	N/a	575	avai	64 Kbit 8K x 8 Parallel EEPROM With Software Data Protection