M27W512-100K6TR Fast Delivery |IC PHOENIX CO.,LIMITED

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M27W512-100K6TR
4 Mbit 256Kb x16 Low Voltage UV EPROM and OTP EPROM
1/16March 2000
M27W512
512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM 2.7Vto 3.6V SUPPLY VOLTAGEin READ
OPERATION ACCESS TIME:
–70nsat VCC= 3.0Vto 3.6V
–80nsat VCC= 2.7Vto 3.6V PIN COMPATIBLE with M27C512 LOW POWER CONSUMPTION:
–15μA max Standby Current 15mA max Active Currentat 5MHz PROGRAMMING TIME 100μs/byte HIGH RELIABILITY CMOS TECHNOLOGY 2,000V ESD Protection 200mA Latchup Protection Immunity ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 3Dh
DESCRIPTION
The M27W512isa low voltage 512 Kbit EPROM
offeredin the two range UV (ultra violet erase) and
OTP (one time programmable).Itis ideally suited
for microprocessor systems andis organizedas
65,536by8 bits.
The M27W512 operatesin the read mode witha
supply voltageas lowas 2.7Vat –40to 85°C tem-
perature range. The decreasein operating power
allows eithera reductionof the sizeof the battery an increasein the time between battery re-
charges.
The FDIP28W (window ceramic frit-seal package)
has transparentlid which allows the userto ex-
pose the chipto ultraviolet lightto erase thebit pat-
tern.A new pattern can then be writtento the
deviceby following the programming procedure.
For applications where the contentis programmed
only one time and erasureis not required, the
M27W512is offeredin PDIP28, PLCC32 and
TSOP28(8x 13.4 mm) packages.
Figure1. Logic Diagram
AI01584
Q0-Q7
VCC
M27W512
GVPP
VSS
A0-A15 28
FDIP28W(F) PDIP28(B)
PLCC32 (K) TSOP28 (N)x 13.4 mm
M27W512
2/16
Figure 2B. LCC Connections
AI01585
A13
A10Q2
A14
A15
A11V
M27W512
A12
GVPP
Figure 2A. DIP Connections
A13
A10
A14
A11
GVPPQ1VSS
A12
A15 VCC
AI02679
M27W5128
Table1. Signal Names
A0-A15 Address Inputs
Q0-Q7 Data Outputs Chip Enable
GVPP Output Enable/ Program Supply
VCC Supply Voltage
VSS Ground Not Connected Internally Don’t Use
Figure 2C. TSOP Connections
A11PP
A13
A14
A12
A15
VCC
AI01586
M27W51228
VSS
A10
3/16
M27W512
Table2. Absolute Maximum Ratings(1)
Note:1. Exceptforthe rating ”Operating Temperature Range”, stressesabove those listedinthe Table ”Absolute Maximum Ratings” may
cause permanent damagetothe device. Theseare stress ratings only and operationofthe device attheseor anyother conditions
above those indicatedinthe Operating sectionsofthis specificationisnot implied. Exposure toAbsolute Maximum Rating condi-
tionsfor extended periods may affect device reliability. Referalsotothe STMicroelectronics SUREProgram andotherrelevant qual-
ity documents. MinimumDC voltageon Inputor Outputis –0.5V with possible undershootto –2.0Vfora period less than 20ns. MaximumDC
voltageon Outputis VCC +0.5V with possible overshootto VCC +2Vfora period less than20ns. Dependson range.
Table3. Operating Modes
Note:X=VIHor VIL,VID= 12V± 0.5V.
Table4. Electronic Signature
Symbol Parameter Value Unit Ambient Operating Temperature(3) –40to 125 °C
TBIAS Temperature Under Bias –50to 125 °C
TSTG Storage Temperature –65to 150 °C
VIO(2) Inputor Output Voltage (except A9) –2to7 V
VCC Supply Voltage –2to7 V
VA9(2) A9 Voltage –2to 13.5 V
VPP Program Supply Voltage –2to14 V
Mode E GVPP A9 Q7-Q0
Read VIL VIL X Data Out
Output Disable VIL VIH X Hi-Z
Program VIL Pulse VPP XDataIn
Program Inhibit VIH VPP X Hi-Z
Standby VIH X X Hi-Z
Electronic Signature VIL VIL VID Codes
Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’sCode VIL 001 000 00 20h
Device Code VIH 001 111 01 3Dh
M27W512
4/16
DEVICE OPERATION
The modesof operationsof the M27W512 are list-in the Operating Modes table.A single power
supplyis requiredin the read mode.All inputs are
TTL levels except for GVPP and 12V on A9 for
Electronic Signature.
Read Mode
The M27W512 has two control functions, bothof
which must be logically activein orderto obtain
dataat the outputs. Chip Enable (E)is the power
control and should be used for device selection.
Output Enable(G)is the output control and should usedto gate datato the output pins, indepen-
dentof device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV)is equalto the delay fromEto output
(tELQV). Datais availableat the output aftera delay tGLQV from the falling edgeofG, assuming that has been low and the addresses have been sta-
bleforat least tAVQV-tGLQV.
Standby Mode
The M27W512 hasa standby mode which reduc- the supply current from 15mAto 15μA with low
voltage operation VCC≤ 3.6V, see Read Mode DC
Characteristics table for details. The M27W512is
placedin the standby modeby applyinga CMOS
high signalto theE input. Whenin the standby
mode, the outputs areina high impedance state,
independentof the GVPP input.
Table5. AC Measurement Conditions
High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns
Input Pulse Voltages 0to3V 0.4Vto 2.4V
Input and Output Timing Ref. Voltages 1.5V 0.8V and2V
Figure3. AC Testing Input Output Waveform
AI01822
High Speed
1.5V
2.4V
Standard
0.4V
2.0V
0.8V
Figure4. AC Testing Load Circuit
AI01823B
1.3V
OUTL= 30pFfor HighSpeedL= 100pFfor StandardL includesJIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table6. Capacitance(1) (TA =25 °C,f=1 MHz)
Note:1. Sampled only,not 100% tested.
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN =0V 6pF
COUT Output Capacitance VOUT =0V 12 pF
5/16
M27W512
Table7. Read Mode DC Characteristics(1)
(TA= –40to 85°C; VCC= 2.7Vto 3.6V; VPP =VCC)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. MaximumDC voltageon Outputis VCC +0.5V.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V≤ VIN≤ VCC ±10 μA
ILO Output Leakage Current 0V≤ VOUT≤ VCC ±10 μA
ICC Supply Current VIL,G= VIL,
IOUT= 0mA,f= 5MHz
VCC ≤ 3.6V mA
ICC1 Supply Current (Standby) TTL E= VIH 1mA
ICC2 Supply Current (Standby) CMOS E>VCC– 0.2V,
VCC ≤ 3.6V 15 μA
IPP Program Current VPP =VCC 10 μA
VIL Input Low Voltage –0.6 0.2 VCC V
VIH(2) Input High Voltage 0.7 VCC VCC+ 0.5 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output High Voltage TTL IOH= –1mA 2.4 V
System Considerations
The power switching characteristicsof Advanced
CMOS EPROMs require careful decouplingof the
devices. The supply current, ICC, has three seg-
ments that areof interestto the system designer:
the standby current level, the active current level,
and transient current peaks that are producedby
the falling and rising edgesofE. The magnitudeof
the transient current peaksis dependent on the
capacitive and inductive loadingof the deviceat
the output.
The associated transient voltage peaks can be
suppressedby complying with the two line output
control and by properly selected decoupling ca-
pacitors.Itis recommended thata 0.1μF ceramic
capacitor be used on every device between VCC
and VSS. This shouldbea high frequency capaci-
tor of low inherent inductance and should be
placedas closeto the deviceas possible.In addi-
tion,a 4.7μF bulk electrolytic capacitor shouldbe
used between VCC and VSS for every eight devic-
es. The bulk capacitor shouldbe located near the
power supply connection point.The purposeof the
bulk capacitoristo overcome the voltage drop
causedby the inductive effectsof PCB traces.
Two Line Output Control
Because EPROMs are usually usedin larger
memory arrays, the product featuresa2 line con-
trol function which accommodates the useof mul-
tiple memory connection. The two line control
function allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the most efficient useof these two control
lines,E shouldbe decoded and usedas the prima- device selecting function, whileG should be
madea common connectiontoall devicesin the
array and connectedto the READ line from the
system control bus. This ensures thatall deselect- memory devices arein their low power standby
mode and that the output pins are only active
when datais required froma particular memory
device.
M27W512
6/16
Figure5. Read Mode AC Waveforms
AI00735B
tAXQX
tEHQZ
A0-A15
Q0-Q7
tAVQV
tGHQZ
tGLQV
tELQV
VALID
Hi-Z
VALID
Table8. Read Mode AC Characteristics(1)
(TA= –40to 85°C; VCC= 2.7Vto 3.6V; VPP =VCC)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. Sampled only,not 100% tested. Speed obtained with High SpeedAC measurement conditions.
Symbol Alt Parameter Test
Condition
M27W102
Unit-80(3) -100
(-120/-150/-200)
VCC= 3.0Vto 3.6V VCC= 2.7Vto 3.6V VCC= 2.7Vto 3.6V
Min Max Min Max Min Max
tAVQV tACC Address Validto
Output Valid VIL,VIL 70 80 100 ns
tELQV tCE Chip Enable Lowto
Output Valid G=VIL 70 80 100 ns
tGLQV tOE Output Enable Low Output Valid E=VIL 40 50 60 ns
tEHQZ(2) tDF Chip Enable High Output Hi-Z G=VIL 0 40 0 50 0 60 ns
tGHQZ(2) tDF Output EnableHigh Output Hi-Z E=VIL 0 40 0 50 0 60 ns
tAXQX tOH Address Transition Output Transition VIL,VIL 000 ns
7/16
M27W512
Table9. Programming Mode DC Characteristics(1)
(TA =25 °C; VCC= 6.25V± 0.25V; VPP= 12.75V± 0.25V)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP.
Table 10. MARGIN MODE AC Characteristics(1)
(TA =25 °C; VCC= 6.25V± 0.25V; VPP= 12.75V± 0.25V)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP.
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current VIL≤ VIN≤ VIH ±10 μA
ICC Supply Current 50 mA
IPP Program Current E=VIL 50 mA
VIL Input Low Voltage –0.3 0.8 V
VIH Input High Voltage 2 VCC+ 0.5 V
VOL Output Low Voltage IOL= 2.1mA 0.4 V
VOH Output High Voltage TTL IOH= –1mA 3.6 V
VID A9 Voltage 11.5 12.5 V
Symbol Alt Parameter Test Condition Min Max Unit
tA9HVPH tAS9 VA9 Highto VPP High 2 μs
tVPHEL tVPS VPP Highto Chip Enable Low 2 μs
tA10HEH tAS10 VA10 Highto Chip Enable High (Set) 1 μs
tA10LEH tAS10 VA10 Lowto Chip Enable High (Reset) 1 μs
tEXA10X tAH10 Chip Enable Transitionto VA10 Transition 1 μs
tEXVPX tVPH Chip Enable Transitionto VPP Transition 2 μs
tVPXA9X tAH9 VPP Transitionto VA9 Transition 2 μs
Programming
The M27W512 hasbeen designedtobe fully com-
patible with the M27C512 and has the same elec-
tronic signature.Asa result the M27W512 canbe
programmed as the M27C512 on the same pro-
gramming equipmentapplying 12.75Von VPP and
6.25Von VCC. The M27W512 can use PRESTO
IIB Programming Algorithm that drastically reduc- the programming time. Neverthelessto achieve
compatibility with all programming equipments,
PRESTOII Programming Algorithm can be used well. When delivered (and after each ‘1’s era-
sure for UV EPROM),all bitsof the M27W512 are the’1’ state. Datais introduced by selectively
programming ’0’s into the desiredbit locations. Al-
though only ’0’s willbe programmed, both ’1’s and
’0’s canbe presentin the data word. The only way changea‘0’toa ‘1’sby die exposureto ultravi-
olet light (UV EPROM). The M27W512isin the
programming mode when VPP inputisat 12.75V
andEis pulsedto VIL. The datatobe programmed appliedto8 bitsin parallelto the data output
pins. The levels requiredfor the address and data
inputs are TTL. VCCis specifiedto be 6.25V±
0.25V.
M27W512
8/16
Table 11. Programming Mode AC Characteristics(1)
(TA =25 °C; VCC= 6.25V± 0.25V; VPP= 12.75V± 0.25V)
Note:1. VCC mustbe applied simultaneously withor before VPP and removed simultaneouslyor after VPP. Sampled only,not 100% tested.
Symbol Alt Parameter Test Condition Min Max Unit
tAVEL tAS Address Validto Chip Enable Low 2 μs
tQVEL tDS Input Validto Chip Enable Low 2 μs
tVCHEL tVCS VCC Highto Chip Enable Low 2 μs
tVPHEL tOES VPP Highto Chip Enable Low 2 μs
tVPLVPH tPRT VPP Rise Time 50 ns
tELEH tPW Chip Enable Program Pulse Width (Initial) 95 105 μs
tEHQX tDH Chip Enable Highto Input Transition 2 μs
tEHVPX tOEH Chip Enable Highto VPP Transition 2 μs
tVPLEL tVR VPP Lowto Chip Enable Low 2 μs
tELQV tDV Chip Enable Lowto Output Valid 1 μs
tEHQZ(2) tDFP Chip Enable Highto Output Hi-Z 0 130 ns
tEHAX tAH Chip Enable Highto Address Transition 0 ns
Figure6. MARGIN MODE AC Waveforms
Note:A8 Highlevel=5V;A9 High level= 12V.
AI00736B
tA9HVPH tVPXA9X
GVPP
A10SetCC
tVPHEL
tA10LEH
tEXVPX
tA10HEH
A10 Reset
tEXA10X

Partno	Mfg	Dc	Qty	Available	Descript
M27W512-100K6TR \|M27W512100K6TR	ST	N/a	50	avai	512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM