M27W064 Fast Delivery |IC PHOENIX CO.,LIMITED

M27W064 ,64 MBIT (4MB X16) 3V SUPPLY FLEXIBLEROM?MEMORYAbsolute Maximum Ratings 14DC and AC PARAMETERS . 15Table 8. Operating and AC Measuremen ..
M27W064-100M1 ,64 MBIT (4MB X16) 3V SUPPLY FLEXIBLEROM™ MEMORYAbsolute Maximum Ratings 14DC and AC PARAMETERS . 15Table 8. Operating and AC Measuremen ..
M27W10180K6 ,1 MBIT (128KB X8) LOW VOLTAGE UV EPROM AND OTP EPROMLogic DiagramDESCRIPTIONThe M27W101 is a low voltage 1 Mbit EPROM of-fered in two range UV (ultra v ..
M27W10180K6 ,1 MBIT (128KB X8) LOW VOLTAGE UV EPROM AND OTP EPROMAbsolute Maximum Ratings Symbol Parameter Value Unit(3)T –40 to 85 °CA Ambient Operating Temperatur ..
M27W101-80K6 ,1 MBIT (128KB X8) LOW VOLTAGE UV EPROM AND OTP EPROMAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M27W101-80K6 ,1 MBIT (128KB X8) LOW VOLTAGE UV EPROM AND OTP EPROMAbsolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only an ..
M48T35AV-10PC1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMLogic Diagram Table 1. Signal NamesVCC A0-A14 Address InputsDQ0-DQ7 Data Inputs / Outputs15 8E Chip ..
M48T35Y-70MH1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMLogic Diagram Table 1. Signal NamesV A0-A14 Address InputsCCDQ0-DQ7 Data Inputs / Outputs15 8E Chip ..
M48T35Y-70MH6 ,256 KBIT (32KB X8) TIMEKEEPER SRAMLogic Diagram . . 4Table 1. Signal Names . . 4Figure 4. DIP Connections 5Figur ..
M48T35Y-70PC1 ,256 KBIT (32KB X8) TIMEKEEPER SRAMM48T35M48T35Y® 5V, 256 Kbit (32 Kb x8) TIMEKEEPER SRAM
M48T35Y-70PC1. ,256 KBIT (32KB X8) TIMEKEEPER SRAMFEATURES SUMMARY . . . . . 1Figure 1. 28-pin PCDIP, CAPHAT™ Package . 1Figure 2. 28-pin ..
M48T37V-10MH1 ,3.3V-5V 256 KBIT (32KB X8) TIMEKEEPER SRAMBlock Diagram . . 6OPERATION MODES . . . . . . . 7Table 2. Operating Modes 7RE ..

M27W064
64 MBIT (4MB X16) 3V SUPPLY FLEXIBLEROM?MEMORY
1/23
PRELIMINARY DATA
November 2002
M27W064
64 Mbit (4Mb x16) 3V Supply FlexibleROM™ Memory
FEATURES SUMMARY ONE TIME PROGRAMMABLE SUPPLY VOLTAGE
–VCC= 2.7 to 3.6V for Read
–VPP= 11.4 to 12.6V for Program ACCESS TIME 90ns at VCC= 3.0 to 3.6V 100, 110ns at VCC= 2.7 to 3.6V PROGRAMMING TIME 9μs per Word typical Multiple Word Programming Option
(8s typical Chip Program) SUITABLE FOR ON-BOARD PROGRAMMING PROGRAM CONTROLLER Embedded Word Program algorithms ELECTRONIC SIGNATURE Manufacturer Code: 0020h Device Code : 888Ah
Figure 1. Packages
M27W064
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Setup Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Program Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Verify Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 4. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. Program Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 5. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3/23
M27W064
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
VPP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 6. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 11. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 12. Chip Enable Controlled, Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . . . . . . . . . .19
SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data . . . . . . . . .19
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . . . . . . . . . .20
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . . . . . . . . .20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
M27W064
SUMMARY DESCRIPTION
The M27W064 is a 64 Mbit (4Mb x16) non-volatile,
One Time Programmable (OTP), FlexibleROM™
Memory. Read operations can be performed using
a single low voltage (2.7 to 3.6V) supply. Program
operations require an additional VPP (11.4 to
12.6V) power supply. On power-up the memory
defaults to Read mode where it can be read in the
same way as a ROM or EPROM.
Program commands are written to the Command
Interface of the memory. An on-chip Program Con-
troller (PC) simplifies the process of programming
the memory by taking care of all of the special op-
erations that are required to update the memory
contents.
The M27W064 features an innovative command,
Multiple Word Program, used to program large
streams of data. It greatly reduces the total pro-
gramming time when a large number of Words are
written to the memory at any one time. Using this
command the entire memory can be programmed
in 8s, compared to 36s using the standard Word
Program.
The end of a program operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Chip Enable and Output Enable signals control the
bus operation of the memory. They allow simple
connection to most microprocessors, often without
additional logic.
The memory is offered in SO44 and TSOP48 (12
x 20mm) packages. The memory is supplied with
all the bits set to ’1’.
Figure 2. Logic Diagram Table 1. Signal Names
5/23
M27W064
Figure 3. SO Connections Figure 4. TSOP Connections
M27W064
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program Controller.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the command
sent to the Command Interface of the Program
Controller. When reading the Status Register they
report the status of the ongoing algorithm.
Data Inputs/Outputs (DQ8-DQ15). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations the Command Interface does not
use these bits. When reading the Status Register
these bits should be ignored.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read operations to be
performed. It also controls the Bus Write opera-
tions, when VPP is in the VHH range.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operations of the memory. It
also allows Bus Write operations, when VPP is in
the VHH range.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for Read operations.
A 0.1μF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program opera-
tions, ICC3.
VPP Program Supply Voltage. VPP is both a
power supply and Write Protect pin. The two func-
tions are selected by the voltage range applied to
the pin.
When the VPP is in the VHH range (see Table 10,
DC Characteristic, for the relevant values) the Pro-
gram operation is enabled. During such opera-
tions the VPP must be stable in the VHH range.
If the VPP is kept under the VHH range, particularly
in the voltage range 0 to 3.6V, any Program oper-
ation is disabled or stopped.
Note that VPP must not be left floating or uncon-
nected as the device may become unreliable.
Vss Ground. The VSS Ground is the reference
for all voltage measurements.
7/23
M27W064
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 2, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs and applying a Low signal, VIL, to Chip En-
able and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 10, Read AC
Waveforms, and Table 11, Read AC Characteris-
tics, for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
when VPP is set to VHH. A valid Bus Write opera-
tion begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Enable. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure
11, Write AC Waveforms, and Table 12, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 10, DC Characteristics.
During program operation the memory will contin-
ue to use the Program Supply Current, ICC3, for
Program operation until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2, Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Table 2. Bus Operations
Note:1. X = VIL or VIH. XX = VIL, VIHor VHH When reading Status Register during Program algorithm execution VPP must be kept at VHH.
M27W064
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
Refer to Tables 3 and 4, for a summary of the com-
mands.
Read/Reset Command.
The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM, unless otherwise stated. It also resets
the errors in the Status Register. Either one or
three Bus Write operations can be used to issue
the Read/Reset command.
VPP must be set to VHH during the Read/Reset
command. If VPP is set to either VIL or VIH the com-
mand will be ignored. The command can be is-
sued, between Bus Write cycles before the start of
a program operation, to return the device to read
mode. Once the program operation has started the
Read/Reset command is no longer accepted.
Auto Select Command.
The Auto Select command is used to read the
Manufacturer Code and the Device Code. VPP
must be set to VHH during the Auto Select com-
mand. If VPP is set to either VIL or VIH the com-
mand will be ignored. Three consecutive Bus
Write operations are required to issue the Auto Se-
lect command. Once the Auto Select command is
issued the memory remains in Auto Select mode
until a Read/Reset command is issued, all other
commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = VIL and A1 = VIL. The other address bits
may be set to either VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH.
Word Program Command.
The Word Program command can be used to pro-
gram a Word to the memory array. VPP must be
set to VHH during Word Program. If VPP is set to ei-
ther VIL or VIH the command will be ignored, the
data will remain unchanged and the device will re-
vert to Read/Reset mode. The command requires
four Bus Write operations, the final write operation
latches the address and data in the internal state
machine and starts the PC.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 5. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’.
Multiple Word Program Command
The Multiple Word Program command can be
used to program large streams of data. It greatly
reduces the total programming time when a large
number of Words are written in the memory at
once. VPP must be set to VHH during Multiple Word
Program. If VPP is set either VIL or VIH the com-
mand will be ignored, the data will remain un-
changed and the device will revert to Read mode.
It has four phases: the Setup Phase to initiate the
command, the Program Phase to program the
data to the memory, the Verify Phase to check that
the data has been correctly programmed and re-
program if necessary and the Exit Phase.
Setup Phase. The Multiple Word Program com-
mand requires three Bus Write operations to ini-
tiate the command (refer to Table 4, Multiple Word
Program Command and Figure 8, Multiple Word
Program Flowchart).
The Status Register must be read in order to
check that the PC has started (see Table 6 and
Figure 6).
Program Phase. The Program Phase requires
n+1 Bus Write operations, where n is the number
of Words, to execute the programming phase (re-
fer to Table 4, Multiple Word Program and Figure
5, Multiple Word Program Flowchart).
Before any Bus Write operation of the Program
Phase, the Status Register must be read in order
to check that the PC is ready to accept the opera-
tion (see Table 6 and Figure 6).
The Program Phase is executed in three different
sub-phases: The first Bus Write operation of the Program
Phase (the 4th of the command) latches the
Start Address and the first Word to be
programmed. Each subsequent Bus Write operation latches
the next Word to be programmed and
automatically increments the internal Address
Bus. It is not necessary to provide the address
of the location to be programmed but only a
Continue Address, CA (A17 to A21 equal to the
9/23
M27W064
Start Address), that indicates to the PC that the
Program Phase has to continue. A0 to A16 are
‘don’t care’. Finally, after all Words have been programmed,
a Bus Write operation (the (n+1)th ) with a Final
Address, FA (A17 or a higher address pin
different from the Start Address), ends the
Program Phase.
The memory is now set to enter the Verify Phase.
Verify Phase. The Verify Phase is similar to the
Program Phase in that all Words must be resent to
the memory for them to be checked against the
programmed data.
Before any Bus Write Operation of the Verify
Phase, the Status Register must be read in order
to check that the PC is ready for the next operation
or if the reprogram of the location has failed (see
Table 6 and Figure 6).
Three successive steps are required to execute
the Verify Phase of the command: The first Bus Write operation of the Verify Phase
latches the Start Address and the Word to be
verified. Each subsequent Bus Write operation latches
the next Word to be verified and automatically
increments the internal Address Bus. As in the
Program Phase, it is not necessary to provide
the address of the location to be programmed
but only a Continue Address, CA (A17 to A21
equal to the Start Address). Finally, after all Words have been verified, a Bus
Write cycle with a Final Address, FA (A17 or a
higher address pin different from the Start
Address) ends the Verify Phase.
Exit Phase. After the Verify Phase ends, the Sta-
tus Register must be read to check if the command
has successfully completed or not (see Table 6
and Figure 6).
If the Verify Phase is successful, the memory re-
turns to Read mode and DQ6 stops toggling.
If the PC fails to reprogram a given location, the
Verify Phase terminates, DQ6 continues toggling
and error bit DQ5 is set in the Status Register. If
the error is due to a VPP failure DQ4 is also set.
When the operation fails a Read/Reset command
must be issued to return the device to Read mode.
During the Multiple Word Program operation the
memory will ignore all commands. It is not possible
to issue any command to abort or pause the oper-
ation. Typical program times are given in Table 5.
Bus Read operations during the program opera-
tion will output the Status Register on the Data In-
puts/Outputs. See the section on the Status
Register for more details.
Note that the Multiple Word Program command
cannot change a bit set to ’0’ back to ’1’.
M27W064
Table 3. Standard Commands
Note: X Don’t Care, PA Program Address, PD Program Data. All values in the table are in hexadecimal. The Command Interface only uses
A0-A10 and DQ0-DQ7 to verify the commands; A11-A21, DQ8-DQ15 are Don’t Care.
Table 4. Multiple Word Program Command
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check
that the memory is ready to accept the next data. SA is the Start Address. CA is the Continue Address. FA is the Final Address. X Don’t
Care, n = number of Words to be programmed.
Table 5. Program Times
Note:1. TA = 25°C, VPP = 12V.
11/23
M27W064
Figure 5. Multiple Word Program Flowchart
M27W064
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program opera-
tions. The bits in the Status Register are summa-
rized in Table 6, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program Controller
has successfully completed its operation. The
Data Polling Bit is output on DQ7 when the Status
Register is read.
During a Word Program operation the Data Polling
Bit outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Word Program operation the memory returns
to Read mode and Bus Read operations from the
address just programmed output DQ7, not its com-
plement.
Figure 6, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program Controller has suc-
cessfully completed its operation. The Toggle Bit
is output on DQ6 when the Status Register is read.
During Program operations the Toggle Bit chang-
es from ’0’ to ’1’ to ’0’, etc., with successive Bus
Read operations at any address. After successful
completion of the operation the memory returns to
Read mode.
Figure 7, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program Controller.
The Error Bit is set to ’1’ when a Program opera-
tion fails to write the correct data to the memory. If
the Error Bit is set a Read/Reset command must
be issued before other commands are issued. The
Error bit is output on DQ5 when the Status Regis-
ter is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’.
VPP Status Bit (DQ4). The VPP Status Bit can be
used to identify if any Program operation has failed
due to a VPP error. If VPP falls below VHH during
any Program operation, the operation aborts and
DQ4 is set to ‘1’. If VPP remains at VHH throughout
the Program operation, the operation completes
and DQ4 is set to ‘0’.
Multiple Word Program Bit (DQ0). The Multiple
Word Program Bit can be used to indicate whether
the Program Controller is active or inactive during
Multiple Word Program. When the Program Con-
troller has written one Word and is ready to accept
the next Word, the bit is set to ‘0’.
Status Register Bit DQ1 is reserved.

Partno	Mfg	Dc	Qty	Available	Descript
M27W064	ST	N/a	12	avai	64 MBIT (4MB X16) 3V SUPPLY FLEXIBLEROM?MEMORY