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M27V256
256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM
1/15
NOT FOR NEW DESIGNJuly 2000
M27V256256 Kbit (32Kb x 8) Low Voltage UV EPROM and OTP EPROM
M27V256 is replaced by the M27W256 3V to 3.6V LOW VOLTAGE in READ
OPERATION ACCESS TIME: 90ns LOW POWER CONSUMPTION: Active Current 10mA at 5MHz Standby Current 10μA PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100μs/word ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 8Dh
DESCRIPTIONThe M27V256 is a low voltage 256 Kbit EPROM
offered in the two ranges UV (ultra violet erase)
and OTP (one time programmable). It is ideally
suited for microprocessor systems and is orga-
nized as 32,768 by 8 bits.
The M27V256 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V256 is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
M27V256
Table 1. Signal Names
3/15
M27V256
Table 2. Absolute Maximum Ratings (1)Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. Depends on range.
Table 3. Operating ModesNote: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic Signature
M27V256
DEVICE OPERATION The modes of operation of the M27V256 are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL lev-
els except for VPP and 12V on A9 for Electronic
Signature.
Read Mode The M27V256 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after delay
of tGLQV from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least tAVQV-tGLQV.
Standby Mode The M27V256 has a standby mode which reduces
the supply current from 10mA to 10μA with low
voltage operation VCC ≤ 3.6V, see Read Mode DC
Characteristics table for details. The M27V256 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Table 5. AC Measurement Conditions
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Note:1. Sampled only, not 100% tested.
5/15
M27V256
Table 7. Read Mode DC Characteristics (1)(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)(TA = 0 to 70 °C or –40 to 85°; VCC = 3.3V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested. Speed obtained with High Speed AC measurement conditions.
Two Line Output Control Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and hat the output pins are only active when
data is desired from a particular memory device.
M27V256
Table 8B. Read Mode AC Characteristics (1)(TA = 0 to 70°C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = Vcc)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested.
System Considerations The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1μF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7μF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
7/15
M27V256
Table 9. Programming Mode DC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note: VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1)(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V
Note: VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Programming The M27V256 has been designed to be fully com-
patible with the M27C256B and has the same
electronic signature. As a result the M27V256 can
be programmed as the M27C256B on the same
programming equipments applying 12.75V on VPP
and 6.25V on VCC by the use of the same PRES-
TO II algorithm. When delivered (and after each
erasure for UV EPROM), all bits of the M27V256
are in the ’1’ state. Data is introduced by selective-
ly programming ’0’s into the desired bit locations.
Although only ’0’s will be programmed, both ’1’s
and ’0’s can be present in the data word. The only
way to change a ’0’ to a ’1’ is by die exposure to ul-
traviolet light (UV EPROM). The M27V256 is in the
programming mode when VPP input is at 12.75V,
G is at VIH and E is pulsed to VIL. The data to be
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. VCC is specified to
be 6.25 V ± 0.25 V.
M27V256
PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows to pro-
gram the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100μs program pulses to each byte until a cor-
rect verify occurs (see Figure 7). During program-
ming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE at VCC much higher than
3.6V provides necessary margin to each pro-
grammed cell.
Program Inhibit Programming of multiple M27V256s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27V256 may be common. A TTL low level pulse
applied to a M27V256's E input, with VPP at 12.75
V, will program that M27V256. A high level E input
inhibits the other M27V256s from being pro-
grammed.
Program Verify A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.
