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M27C256B- - 12F6-M27C256B-10 F1-M27C256B-10B6-M27C256B-10C1-M27C256B-10C6 Fast Delivery,Good Price
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M27C256B- - 12F6 |M27C256B12F6STN/a1301avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-10 F1 |M27C256B10F1STMN/a158avai256 Kbit (32Kb x 8) EPROM, 5V, 100ns
M27C256B-10B6 |M27C256B10B6STN/a199avai256 Kbit (32Kb x 8) EPROM, 5V, 100ns
M27C256B-10C1 |M27C256B10C1STN/a140avai256 KBIT (32KB X8) UV EPROM AND OTP EPROM
M27C256B-10C6 |M27C256B10C6STN/a1080avai256 Kbit (32Kb x 8) EPROM, 5V, 100ns
M27C256B-10C6 |M27C256B10C6STMN/a119avai256 Kbit (32Kb x 8) EPROM, 5V, 100ns
M27C256B-10F1 |M27C256B10F1STN/a6670avai256 Kbit (32Kb x 8) EPROM, 5V, 100ns
M27C256B-12B1 |M27C256B12B1STN/a2899avai256 KBIT (32KB X8) UV EPROM AND OTP EPROM
M27C256B12C1STN/a106avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-12C1 |M27C256B12C1STN/a717avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-12C1 |M27C256B12C1STMN/a2637avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-12C1 |M27C256B12C1N/a1994avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B12C6N/a7avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-12C6 |M27C256B12C6STN/a200avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-12F1 |M27C256B12F1N/a1715avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-12F6 |M27C256B12F6STMN/a21320avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-12F6 |M27C256B12F6STN/a6100avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B--12F6 |M27C256B12F6STN/a2002avai256 Kbit (32Kb x 8) EPROM, 5V, 120ns
M27C256B-45XF1 |M27C256B45XF1STN/a5704avai256 KBIT (32KB X8) UV EPROM AND OTP EPROM
M27C256B70C1STN/a2avai256 Kbit (32Kb x 8) EPROM, 5V, 70ns
M27C256B-70C1 |M27C256B70C1STN/a800avai256 Kbit (32Kb x 8) EPROM, 5V, 70ns
M27C256B-70XF1 |M27C256B70XF1STN/a4130avai256 KBIT (32KB X8) UV EPROM AND OTP EPROM
M27C256B-90B1 |M27C256B90B1STN/a318avai256 Kbit (32Kb x 8) EPROM, 5V, 90ns
M27C256B-90C1 |M27C256B90C1STN/a120avai256 Kbit (32Kb x 8) EPROM, 5V, 90ns
M27C256B-90C6 |M27C256B90C6STN/a75avai256 KBIT (32KB X8) UV EPROM AND OTP EPROM
M27C256B90F6STN/a3020avai256 Kbit (32Kb x 8) EPROM, 5V, 90ns
M27C256B-90F6 |M27C256B90F6STN/a4980avai256 Kbit (32Kb x 8) EPROM, 5V, 90ns
M27C256B--90F6 |M27C256B90F6STN/a153avai256 Kbit (32Kb x 8) EPROM, 5V, 90ns


M27C256B-12F6 ,256 Kbit (32Kb x 8) EPROM, 5V, 120nsLogic DiagramThe FDIP28W (window ceramic frit-seal package)has a transparent lid which allows the u ..
M27C256B-12F6 ,256 Kbit (32Kb x 8) EPROM, 5V, 120nsM27C256B256 Kbit (32Kb x 8) UV EPROM and OTP EPROM■ 5V ± 10% SUPPLY VOLTAGE in READ OPERATION■ ACCE ..
M27C256B--12F6 ,256 Kbit (32Kb x 8) EPROM, 5V, 120nsAbsolute Maximum Ratings Symbol Parameter Value Unit(3)T –40 to 125 °CA Ambient Operating Temperatu ..
M27C256B-15C1TR ,256 Kbit (32Kb x 8) EPROM, 5V, 150nsapplications where the content is programmedonly one time and erasure is not required, the15 8M27C2 ..
M27C256B15F1 ,256 Kbit (32Kb x 8) UV EPROM and OTP EPROMAbsolute Maximum Ratings”may cause permanent damage to the device. These are stress ratings only an ..
M27C256B-15F1 ,256 Kbit (32Kb x 8) UV EPROM and OTP EPROMAbsolute Maximum Ratings”may cause permanent damage to the device. These are stress ratings only an ..
M41ST84W ,512 BIT (64 X 8) SERIAL RTC WITH SUPERVISORY FUNCTIONSFEATURES SUMMARY■ 5.0 OR 3.0V OPERATING VOLTAGE Figure 1. 16-pin SOIC Package2■ SERIAL INTERFACE SU ..
M41ST84W. ,512 BIT (64 X 8) SERIAL RTC WITH SUPERVISORY FUNCTIONSLogic Diagram Table 1. Signal Names(1) (1)Oscillator InputXIV VCC BAT(1)XO Oscillator OutputInterru ..
M41ST84WMQ6 ,512 Bit (64 X8) Serial RTC with Supervisory FunctionsFEATURES SUMMARY . . . . . 1Figure 1. 16-pin SOIC Package . . . . 1Figure 2. 28-pin SO ..
M41ST84WMQ6E ,512 Bit (64 X8) Serial RTC with Supervisory FunctionsLogic Diagram Table 1. Signal Names (1) (1)XI Oscillator InputV VCC BAT (1)Oscillator OutputXOInter ..
M41ST84WMQ6F ,512 Bit (64 X8) Serial RTC with Supervisory FunctionsFEATURES SUMMARY■ 5.0 OR 3.0V OPERATING VOLTAGE Figure 1. 16-pin SOIC Package2■ SERIAL INTERFACE SU ..
M41ST84WMQ6TR ,512 Bit (64 X8) Serial RTC with Supervisory FunctionsBlock Diagram . . 5Figure 7. Hardware Hookup . . . . . . . 6OPERATING MODES . . ..


M27C256B- - 12F6-M27C256B-10 F1-M27C256B-10B6-M27C256B-10C1-M27C256B-10C6-M27C256B-10F1-M27C256B-12B1-M27C256B12C1-M27C256B-12C1-M27C256B12C6-M27C256B-12C6-M27C256B-12F1-M27C256B-12F6-M27C256B--12F6-M27C256B-45XF1-M27C256B70C1-M27C256B-70C1-M27C256B-70XF1-M27C256B-90B1-M2
256 KBIT (32KB X8) UV EPROM AND OTP EPROM
1/16August 2002
M27C256B

256 Kbit (32Kb x 8) UV EPROM and OTP EPROM 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION ACCESS TIME: 45ns LOW POWER CONSUMPTION: Active Current 30mA at 5MHz Standby Current 100μA PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100μs/word ELECTRONIC SIGNATURE Manufacturer Code: 20h Device Code: 8Dh
DESCRIPTION

The M27C256B is a 256 Kbit EPROM offered in
the two ranges UV (ultra violet erase) and OTP
(one time programmable). It is ideally suited for mi-
croprocessor systems and is organized as 32,768
by 8 bits.
The FDIP28W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C256B is offered in PDIP28, PLCC32 and
TSOP28 (8 x 13.4 mm) packages.
M27C256B
2/16
Table 1. Signal Names
3/16
M27C256B
Table 2. Absolute Maximum Ratings (1)

Note:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. Depends on range.
Table 3. Operating Modes

Note: X = VIH or VIL, VID = 12V ± 0.5V.
Table 4. Electronic Signature
M27C256B
4/16
DEVICE OPERATION

The operating modes of the M27C256B are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL lev-
els except for VPP and 12V on A9 for Electronic
Signature.
Read Mode

The M27C256B has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-
dent of device selection. Assuming that the ad-
dresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after delay
of tGLQV from the falling edge of G, assuming that
E has been low and the addresses have been sta-
ble for at least tAVQV-tGLQV.
Standby Mode

The M27C256B has a standby mode which reduc-
es the supply current from 30mA to 100μA. The
M27C256B is placed in the standby mode by ap-
plying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high imped-
ance state, independent of the G input.
Table 5. AC Measurement Conditions
Table 6. Capacitance (1)
(TA = 25 °C, f = 1 MHz)
Note:1. Sampled only, not 100% tested.
5/16
M27C256B
Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested. Speed obtained with High Speed AC measurement conditions.
Two Line Output Control

Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows: the lowest possible memory power dissipation, complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is desired from a particular memory de-
vice.
M27C256B
6/16
Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Note:1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Sampled only, not 100% tested.
System Considerations

The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1μF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7μF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
7/16
M27C256B
Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note: VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V
Note: VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Programming

When delivered (and after each erasure for UV
EPROM), all bits of the M27C256B are in the "1"
state. Data is introduced by selectively program-
ming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
change a '0' to a '1' is by die exposure to ultraviolet
light (UV EPROM). The M27C256B is in the pro-
gramming mode when VPP input is at 12.75V, G is
at VIH and E is pulsed to VIL. The data to be pro-
grammed is applied to 8 bits in parallel to the data
output pins. The levels required for the address
and data inputs are TTL. VCC is specified to be
6.25V ± 0.25 V.
M27C256B
8/16
PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows to pro-
gram the whole array with a guaranteed margin, in
a typical time of 3.5 seconds. Programming with
PRESTO II involves the application of a sequence
of 100μs program pulses to each byte until a cor-
rect verify occurs (see Figure 7). During program-
ming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE provides necessary mar-
gin to each programmed cell.
Program Inhibit

Programming of multiple M27C256Bs in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C256B may be common. A TTL low level
pulse applied to a M27C256B's E input, with VPP
at 12.75V, will program that M27C256B. A high
level E input inhibits the other M27C256Bs from
being programmed.
Program Verify

A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with G
at VIL, E at VIH, VPP at 12.75V and VCC at 6.25V.
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